[J-u-boot.git] / drivers / mmc / zynq_sdhci.c

// SPDX-License-Identifier: GPL-2.0+
/*
 * (C) Copyright 2013 - 2015 Xilinx, Inc.
 *
 * Xilinx Zynq SD Host Controller Interface
 */

#include <clk.h>
#include <common.h>
#include <dm.h>
#include <fdtdec.h>
#include <linux/delay.h>
#include "mmc_private.h"
#include <log.h>
#include <dm/device_compat.h>
#include <linux/err.h>
#include <linux/libfdt.h>
#include <malloc.h>
#include <sdhci.h>
#include <zynqmp_tap_delay.h>

struct arasan_sdhci_plat {
	struct mmc_config cfg;
	struct mmc mmc;
};

struct arasan_sdhci_priv {
	struct sdhci_host *host;
	u8 deviceid;
	u8 bank;
};

#if defined(CONFIG_ARCH_ZYNQMP)
#define MMC_HS200_BUS_SPEED	5

static const u8 mode2timing[] = {
	[MMC_LEGACY] = UHS_SDR12_BUS_SPEED,
	[MMC_HS] = HIGH_SPEED_BUS_SPEED,
	[SD_HS] = HIGH_SPEED_BUS_SPEED,
	[MMC_HS_52] = HIGH_SPEED_BUS_SPEED,
	[MMC_DDR_52] = HIGH_SPEED_BUS_SPEED,
	[UHS_SDR12] = UHS_SDR12_BUS_SPEED,
	[UHS_SDR25] = UHS_SDR25_BUS_SPEED,
	[UHS_SDR50] = UHS_SDR50_BUS_SPEED,
	[UHS_DDR50] = UHS_DDR50_BUS_SPEED,
	[UHS_SDR104] = UHS_SDR104_BUS_SPEED,
	[MMC_HS_200] = MMC_HS200_BUS_SPEED,
};

#define SDHCI_TUNING_LOOP_COUNT	40

static void arasan_zynqmp_dll_reset(struct sdhci_host *host, u8 deviceid)
{
	u16 clk;
	unsigned long timeout;

	clk = sdhci_readw(host, SDHCI_CLOCK_CONTROL);
	clk &= ~(SDHCI_CLOCK_CARD_EN);
	sdhci_writew(host, clk, SDHCI_CLOCK_CONTROL);

	/* Issue DLL Reset */
	zynqmp_dll_reset(deviceid);

	/* Wait max 20 ms */
	timeout = 100;
	while (!((clk = sdhci_readw(host, SDHCI_CLOCK_CONTROL))
				& SDHCI_CLOCK_INT_STABLE)) {
		if (timeout == 0) {
			dev_err(mmc_dev(host->mmc),
				": Internal clock never stabilised.\n");
			return;
		}
		timeout--;
		udelay(1000);
	}

	clk |= SDHCI_CLOCK_CARD_EN;
	sdhci_writew(host, clk, SDHCI_CLOCK_CONTROL);
}

static int arasan_sdhci_execute_tuning(struct mmc *mmc, u8 opcode)
{
	struct mmc_cmd cmd;
	struct mmc_data data;
	u32 ctrl;
	struct sdhci_host *host;
	struct arasan_sdhci_priv *priv = dev_get_priv(mmc->dev);
	char tuning_loop_counter = SDHCI_TUNING_LOOP_COUNT;
	u8 deviceid;

	debug("%s\n", __func__);

	host = priv->host;
	deviceid = priv->deviceid;

	ctrl = sdhci_readw(host, SDHCI_HOST_CONTROL2);
	ctrl |= SDHCI_CTRL_EXEC_TUNING;
	sdhci_writew(host, ctrl, SDHCI_HOST_CONTROL2);

	mdelay(1);

	arasan_zynqmp_dll_reset(host, deviceid);

	sdhci_writel(host, SDHCI_INT_DATA_AVAIL, SDHCI_INT_ENABLE);
	sdhci_writel(host, SDHCI_INT_DATA_AVAIL, SDHCI_SIGNAL_ENABLE);

	do {
		cmd.cmdidx = opcode;
		cmd.resp_type = MMC_RSP_R1;
		cmd.cmdarg = 0;

		data.blocksize = 64;
		data.blocks = 1;
		data.flags = MMC_DATA_READ;

		if (tuning_loop_counter-- == 0)
			break;

		if (cmd.cmdidx == MMC_CMD_SEND_TUNING_BLOCK_HS200 &&
		    mmc->bus_width == 8)
			data.blocksize = 128;

		sdhci_writew(host, SDHCI_MAKE_BLKSZ(SDHCI_DEFAULT_BOUNDARY_ARG,
						    data.blocksize),
			     SDHCI_BLOCK_SIZE);
		sdhci_writew(host, data.blocks, SDHCI_BLOCK_COUNT);
		sdhci_writew(host, SDHCI_TRNS_READ, SDHCI_TRANSFER_MODE);

		mmc_send_cmd(mmc, &cmd, NULL);
		ctrl = sdhci_readw(host, SDHCI_HOST_CONTROL2);

		if (cmd.cmdidx == MMC_CMD_SEND_TUNING_BLOCK)
			udelay(1);

	} while (ctrl & SDHCI_CTRL_EXEC_TUNING);

	if (tuning_loop_counter < 0) {
		ctrl &= ~SDHCI_CTRL_TUNED_CLK;
		sdhci_writel(host, ctrl, SDHCI_HOST_CONTROL2);
	}

	if (!(ctrl & SDHCI_CTRL_TUNED_CLK)) {
		printf("%s:Tuning failed\n", __func__);
		return -1;
	}

	udelay(1);
	arasan_zynqmp_dll_reset(host, deviceid);

	/* Enable only interrupts served by the SD controller */
	sdhci_writel(host, SDHCI_INT_DATA_MASK | SDHCI_INT_CMD_MASK,
		     SDHCI_INT_ENABLE);
	/* Mask all sdhci interrupt sources */
	sdhci_writel(host, 0x0, SDHCI_SIGNAL_ENABLE);

	return 0;
}

static void arasan_sdhci_set_tapdelay(struct sdhci_host *host)
{
	struct arasan_sdhci_priv *priv = dev_get_priv(host->mmc->dev);
	struct mmc *mmc = (struct mmc *)host->mmc;
	u8 uhsmode;

	uhsmode = mode2timing[mmc->selected_mode];

	if (uhsmode >= UHS_SDR25_BUS_SPEED)
		arasan_zynqmp_set_tapdelay(priv->deviceid, uhsmode,
					   priv->bank);
}

static void arasan_sdhci_set_control_reg(struct sdhci_host *host)
{
	struct mmc *mmc = (struct mmc *)host->mmc;
	u32 reg;

	if (!IS_SD(mmc))
		return;

	if (mmc->signal_voltage == MMC_SIGNAL_VOLTAGE_180) {
		reg = sdhci_readw(host, SDHCI_HOST_CONTROL2);
		reg |= SDHCI_CTRL_VDD_180;
		sdhci_writew(host, reg, SDHCI_HOST_CONTROL2);
	}

	if (mmc->selected_mode > SD_HS &&
	    mmc->selected_mode <= UHS_DDR50)
		sdhci_set_uhs_timing(host);
}
#endif

#if defined(CONFIG_ARCH_ZYNQMP)
const struct sdhci_ops arasan_ops = {
	.platform_execute_tuning	= &arasan_sdhci_execute_tuning,
	.set_delay = &arasan_sdhci_set_tapdelay,
	.set_control_reg = &arasan_sdhci_set_control_reg,
};
#endif

static int arasan_sdhci_probe(struct udevice *dev)
{
	struct arasan_sdhci_plat *plat = dev_get_platdata(dev);
	struct mmc_uclass_priv *upriv = dev_get_uclass_priv(dev);
	struct arasan_sdhci_priv *priv = dev_get_priv(dev);
	struct sdhci_host *host;
	struct clk clk;
	unsigned long clock;
	int ret;

	host = priv->host;

	ret = clk_get_by_index(dev, 0, &clk);
	if (ret < 0) {
		dev_err(dev, "failed to get clock\n");
		return ret;
	}

	clock = clk_get_rate(&clk);
	if (IS_ERR_VALUE(clock)) {
		dev_err(dev, "failed to get rate\n");
		return clock;
	}

	debug("%s: CLK %ld\n", __func__, clock);

	ret = clk_enable(&clk);
	if (ret && ret != -ENOSYS) {
		dev_err(dev, "failed to enable clock\n");
		return ret;
	}

	host->quirks = SDHCI_QUIRK_WAIT_SEND_CMD |
		       SDHCI_QUIRK_BROKEN_R1B;

#ifdef CONFIG_ZYNQ_HISPD_BROKEN
	host->quirks |= SDHCI_QUIRK_BROKEN_HISPD_MODE;
#endif

	plat->cfg.f_max = CONFIG_ZYNQ_SDHCI_MAX_FREQ;

	ret = mmc_of_parse(dev, &plat->cfg);
	if (ret)
		return ret;

	host->max_clk = clock;

	host->mmc = &plat->mmc;
	host->mmc->dev = dev;
	host->mmc->priv = host;

	ret = sdhci_setup_cfg(&plat->cfg, host, plat->cfg.f_max,
			      CONFIG_ZYNQ_SDHCI_MIN_FREQ);
	if (ret)
		return ret;
	upriv->mmc = host->mmc;

	return sdhci_probe(dev);
}

static int arasan_sdhci_ofdata_to_platdata(struct udevice *dev)
{
	struct arasan_sdhci_priv *priv = dev_get_priv(dev);

	priv->host = calloc(1, sizeof(struct sdhci_host));
	if (!priv->host)
		return -1;

	priv->host->name = dev->name;

#if defined(CONFIG_ARCH_ZYNQMP)
	priv->host->ops = &arasan_ops;
#endif

	priv->host->ioaddr = (void *)dev_read_addr(dev);
	if (IS_ERR(priv->host->ioaddr))
		return PTR_ERR(priv->host->ioaddr);

	priv->deviceid = dev_read_u32_default(dev, "xlnx,device_id", -1);
	priv->bank = dev_read_u32_default(dev, "xlnx,mio-bank", 0);

	return 0;
}

static int arasan_sdhci_bind(struct udevice *dev)
{
	struct arasan_sdhci_plat *plat = dev_get_platdata(dev);

	return sdhci_bind(dev, &plat->mmc, &plat->cfg);
}

static const struct udevice_id arasan_sdhci_ids[] = {
	{ .compatible = "arasan,sdhci-8.9a" },
	{ }
};

U_BOOT_DRIVER(arasan_sdhci_drv) = {
	.name		= "arasan_sdhci",
	.id		= UCLASS_MMC,
	.of_match	= arasan_sdhci_ids,
	.ofdata_to_platdata = arasan_sdhci_ofdata_to_platdata,
	.ops		= &sdhci_ops,
	.bind		= arasan_sdhci_bind,
	.probe		= arasan_sdhci_probe,
	.priv_auto_alloc_size = sizeof(struct arasan_sdhci_priv),
	.platdata_auto_alloc_size = sizeof(struct arasan_sdhci_plat),
};
Commit	Line	Data
83d290c5	1	// SPDX-License-Identifier: GPL-2.0+
293eb33f	2	/*
d9ae52c8	3	* (C) Copyright 2013 - 2015 Xilinx, Inc.
293eb33f MS	4	*
293eb33f MS	5	* Xilinx Zynq SD Host Controller Interface
293eb33f MS	6	*/
293eb33f MS	7
e0f4de1a	8	#include <clk.h>
293eb33f	9	#include <common.h>
d9ae52c8	10	#include <dm.h>
345d3c0f	11	#include <fdtdec.h>
c05ed00a	12	#include <linux/delay.h>
d1f4e39d	13	#include "mmc_private.h"
f7ae49fc	14	#include <log.h>
336d4615	15	#include <dm/device_compat.h>
61b29b82	16	#include <linux/err.h>
b08c8c48	17	#include <linux/libfdt.h>
293eb33f MS	18	#include <malloc.h>
293eb33f MS	19	#include <sdhci.h>
d1f4e39d	20	#include <zynqmp_tap_delay.h>
293eb33f	21
329a449f SG	22	struct arasan_sdhci_plat {
	23	struct mmc_config cfg;
	24	struct mmc mmc;
	25	};
	26
d1f4e39d SDPP	27	struct arasan_sdhci_priv {
	28	struct sdhci_host *host;
	29	u8 deviceid;
	30	u8 bank;
d1f4e39d SDPP	31	};
	32
	33	#if defined(CONFIG_ARCH_ZYNQMP)
84333708 SDPP	34	#define MMC_HS200_BUS_SPEED 5
84333708 SDPP	35
d1f4e39d	36	static const u8 mode2timing[] = {
84333708	37	[MMC_LEGACY] = UHS_SDR12_BUS_SPEED,
84333708 SDPP	38	[MMC_HS] = HIGH_SPEED_BUS_SPEED,
	39	[SD_HS] = HIGH_SPEED_BUS_SPEED,
	40	[MMC_HS_52] = HIGH_SPEED_BUS_SPEED,
	41	[MMC_DDR_52] = HIGH_SPEED_BUS_SPEED,
	42	[UHS_SDR12] = UHS_SDR12_BUS_SPEED,
	43	[UHS_SDR25] = UHS_SDR25_BUS_SPEED,
	44	[UHS_SDR50] = UHS_SDR50_BUS_SPEED,
	45	[UHS_DDR50] = UHS_DDR50_BUS_SPEED,
	46	[UHS_SDR104] = UHS_SDR104_BUS_SPEED,
	47	[MMC_HS_200] = MMC_HS200_BUS_SPEED,
d1f4e39d SDPP	48	};
d1f4e39d SDPP	49
d1f4e39d SDPP	50	#define SDHCI_TUNING_LOOP_COUNT 40
	51
	52	static void arasan_zynqmp_dll_reset(struct sdhci_host *host, u8 deviceid)
	53	{
	54	u16 clk;
	55	unsigned long timeout;
	56
	57	clk = sdhci_readw(host, SDHCI_CLOCK_CONTROL);
	58	clk &= ~(SDHCI_CLOCK_CARD_EN);
	59	sdhci_writew(host, clk, SDHCI_CLOCK_CONTROL);
	60
	61	/* Issue DLL Reset */
	62	zynqmp_dll_reset(deviceid);
	63
	64	/* Wait max 20 ms */
	65	timeout = 100;
	66	while (!((clk = sdhci_readw(host, SDHCI_CLOCK_CONTROL))
	67	& SDHCI_CLOCK_INT_STABLE)) {
	68	if (timeout == 0) {
	69	dev_err(mmc_dev(host->mmc),
	70	": Internal clock never stabilised.\n");
	71	return;
	72	}
	73	timeout--;
	74	udelay(1000);
	75	}
	76
	77	clk \|= SDHCI_CLOCK_CARD_EN;
	78	sdhci_writew(host, clk, SDHCI_CLOCK_CONTROL);
	79	}
	80
	81	static int arasan_sdhci_execute_tuning(struct mmc *mmc, u8 opcode)
	82	{
	83	struct mmc_cmd cmd;
	84	struct mmc_data data;
	85	u32 ctrl;
	86	struct sdhci_host *host;
	87	struct arasan_sdhci_priv *priv = dev_get_priv(mmc->dev);
b6911780	88	char tuning_loop_counter = SDHCI_TUNING_LOOP_COUNT;
d1f4e39d SDPP	89	u8 deviceid;
	90
	91	debug("%s\n", __func__);
	92
	93	host = priv->host;
	94	deviceid = priv->deviceid;
	95
d1c0a220	96	ctrl = sdhci_readw(host, SDHCI_HOST_CONTROL2);
d1f4e39d	97	ctrl \|= SDHCI_CTRL_EXEC_TUNING;
d1c0a220	98	sdhci_writew(host, ctrl, SDHCI_HOST_CONTROL2);
d1f4e39d SDPP	99
	100	mdelay(1);
	101
	102	arasan_zynqmp_dll_reset(host, deviceid);
	103
	104	sdhci_writel(host, SDHCI_INT_DATA_AVAIL, SDHCI_INT_ENABLE);
	105	sdhci_writel(host, SDHCI_INT_DATA_AVAIL, SDHCI_SIGNAL_ENABLE);
	106
	107	do {
	108	cmd.cmdidx = opcode;
	109	cmd.resp_type = MMC_RSP_R1;
	110	cmd.cmdarg = 0;
	111
	112	data.blocksize = 64;
	113	data.blocks = 1;
	114	data.flags = MMC_DATA_READ;
	115
	116	if (tuning_loop_counter-- == 0)
	117	break;
	118
	119	if (cmd.cmdidx == MMC_CMD_SEND_TUNING_BLOCK_HS200 &&
	120	mmc->bus_width == 8)
	121	data.blocksize = 128;
	122
	123	sdhci_writew(host, SDHCI_MAKE_BLKSZ(SDHCI_DEFAULT_BOUNDARY_ARG,
	124	data.blocksize),
	125	SDHCI_BLOCK_SIZE);
	126	sdhci_writew(host, data.blocks, SDHCI_BLOCK_COUNT);
	127	sdhci_writew(host, SDHCI_TRNS_READ, SDHCI_TRANSFER_MODE);
	128
	129	mmc_send_cmd(mmc, &cmd, NULL);
d1c0a220	130	ctrl = sdhci_readw(host, SDHCI_HOST_CONTROL2);
d1f4e39d SDPP	131
	132	if (cmd.cmdidx == MMC_CMD_SEND_TUNING_BLOCK)
	133	udelay(1);
	134
	135	} while (ctrl & SDHCI_CTRL_EXEC_TUNING);
	136
	137	if (tuning_loop_counter < 0) {
	138	ctrl &= ~SDHCI_CTRL_TUNED_CLK;
d1c0a220	139	sdhci_writel(host, ctrl, SDHCI_HOST_CONTROL2);
d1f4e39d SDPP	140	}
	141
	142	if (!(ctrl & SDHCI_CTRL_TUNED_CLK)) {
	143	printf("%s:Tuning failed\n", __func__);
	144	return -1;
	145	}
	146
	147	udelay(1);
	148	arasan_zynqmp_dll_reset(host, deviceid);
	149
	150	/* Enable only interrupts served by the SD controller */
	151	sdhci_writel(host, SDHCI_INT_DATA_MASK \| SDHCI_INT_CMD_MASK,
	152	SDHCI_INT_ENABLE);
	153	/* Mask all sdhci interrupt sources */
	154	sdhci_writel(host, 0x0, SDHCI_SIGNAL_ENABLE);
	155
	156	return 0;
	157	}
	158
	159	static void arasan_sdhci_set_tapdelay(struct sdhci_host *host)
	160	{
	161	struct arasan_sdhci_priv *priv = dev_get_priv(host->mmc->dev);
	162	struct mmc mmc = (struct mmc )host->mmc;
	163	u8 uhsmode;
	164
d1f4e39d SDPP	165	uhsmode = mode2timing[mmc->selected_mode];
	166
	167	if (uhsmode >= UHS_SDR25_BUS_SPEED)
	168	arasan_zynqmp_set_tapdelay(priv->deviceid, uhsmode,
	169	priv->bank);
	170	}
	171
	172	static void arasan_sdhci_set_control_reg(struct sdhci_host *host)
	173	{
	174	struct mmc mmc = (struct mmc )host->mmc;
	175	u32 reg;
	176
84333708 SDPP	177	if (!IS_SD(mmc))
	178	return;
	179
d1f4e39d	180	if (mmc->signal_voltage == MMC_SIGNAL_VOLTAGE_180) {
d1c0a220 FA	181	reg = sdhci_readw(host, SDHCI_HOST_CONTROL2);
	182	reg \|= SDHCI_CTRL_VDD_180;
	183	sdhci_writew(host, reg, SDHCI_HOST_CONTROL2);
d1f4e39d SDPP	184	}
	185
	186	if (mmc->selected_mode > SD_HS &&
d1c0a220 FA	187	mmc->selected_mode <= UHS_DDR50)
d1c0a220 FA	188	sdhci_set_uhs_timing(host);
d1f4e39d SDPP	189	}
	190	#endif
	191
c95b19ac	192	#if defined(CONFIG_ARCH_ZYNQMP)
d1f4e39d SDPP	193	const struct sdhci_ops arasan_ops = {
	194	.platform_execute_tuning = &arasan_sdhci_execute_tuning,
	195	.set_delay = &arasan_sdhci_set_tapdelay,
	196	.set_control_reg = &arasan_sdhci_set_control_reg,
	197	};
	198	#endif
	199
d9ae52c8	200	static int arasan_sdhci_probe(struct udevice *dev)
293eb33f	201	{
329a449f	202	struct arasan_sdhci_plat *plat = dev_get_platdata(dev);
d9ae52c8	203	struct mmc_uclass_priv *upriv = dev_get_uclass_priv(dev);
d1f4e39d SDPP	204	struct arasan_sdhci_priv *priv = dev_get_priv(dev);
d1f4e39d SDPP	205	struct sdhci_host *host;
e0f4de1a SH	206	struct clk clk;
e0f4de1a SH	207	unsigned long clock;
329a449f	208	int ret;
293eb33f	209
d1f4e39d SDPP	210	host = priv->host;
d1f4e39d SDPP	211
e0f4de1a SH	212	ret = clk_get_by_index(dev, 0, &clk);
	213	if (ret < 0) {
	214	dev_err(dev, "failed to get clock\n");
	215	return ret;
	216	}
	217
	218	clock = clk_get_rate(&clk);
	219	if (IS_ERR_VALUE(clock)) {
	220	dev_err(dev, "failed to get rate\n");
	221	return clock;
	222	}
d1f4e39d	223
e0f4de1a SH	224	debug("%s: CLK %ld\n", __func__, clock);
	225
	226	ret = clk_enable(&clk);
	227	if (ret && ret != -ENOSYS) {
	228	dev_err(dev, "failed to enable clock\n");
	229	return ret;
	230	}
	231
eddabd16	232	host->quirks = SDHCI_QUIRK_WAIT_SEND_CMD \|
f9ec45d1	233	SDHCI_QUIRK_BROKEN_R1B;
b2156146 SDPP	234
b2156146 SDPP	235	#ifdef CONFIG_ZYNQ_HISPD_BROKEN
47819216	236	host->quirks \|= SDHCI_QUIRK_BROKEN_HISPD_MODE;
b2156146 SDPP	237	#endif
b2156146 SDPP	238
942b5fc0 BG	239	plat->cfg.f_max = CONFIG_ZYNQ_SDHCI_MAX_FREQ;
	240
	241	ret = mmc_of_parse(dev, &plat->cfg);
	242	if (ret)
	243	return ret;
d1f4e39d	244
e0f4de1a	245	host->max_clk = clock;
6d0e34bf	246
3148a3c2 MK	247	host->mmc = &plat->mmc;
	248	host->mmc->dev = dev;
	249	host->mmc->priv = host;
	250
942b5fc0	251	ret = sdhci_setup_cfg(&plat->cfg, host, plat->cfg.f_max,
14bed52d	252	CONFIG_ZYNQ_SDHCI_MIN_FREQ);
329a449f SG	253	if (ret)
329a449f SG	254	return ret;
329a449f	255	upriv->mmc = host->mmc;
d9ae52c8	256
329a449f	257	return sdhci_probe(dev);
293eb33f	258	}
d9ae52c8 MS	259
	260	static int arasan_sdhci_ofdata_to_platdata(struct udevice *dev)
	261	{
d1f4e39d SDPP	262	struct arasan_sdhci_priv *priv = dev_get_priv(dev);
	263
	264	priv->host = calloc(1, sizeof(struct sdhci_host));
	265	if (!priv->host)
	266	return -1;
d9ae52c8	267
d1f4e39d	268	priv->host->name = dev->name;
d1f4e39d	269
c95b19ac	270	#if defined(CONFIG_ARCH_ZYNQMP)
d1f4e39d SDPP	271	priv->host->ops = &arasan_ops;
d1f4e39d SDPP	272	#endif
d9ae52c8	273
458e8d80 MS	274	priv->host->ioaddr = (void *)dev_read_addr(dev);
	275	if (IS_ERR(priv->host->ioaddr))
	276	return PTR_ERR(priv->host->ioaddr);
61e745d1	277
458e8d80	278	priv->deviceid = dev_read_u32_default(dev, "xlnx,device_id", -1);
e8deb221	279	priv->bank = dev_read_u32_default(dev, "xlnx,mio-bank", 0);
458e8d80	280
d9ae52c8 MS	281	return 0;
	282	}
	283
329a449f SG	284	static int arasan_sdhci_bind(struct udevice *dev)
	285	{
	286	struct arasan_sdhci_plat *plat = dev_get_platdata(dev);
329a449f	287
24f5aec3	288	return sdhci_bind(dev, &plat->mmc, &plat->cfg);
329a449f SG	289	}
329a449f SG	290
d9ae52c8 MS	291	static const struct udevice_id arasan_sdhci_ids[] = {
	292	{ .compatible = "arasan,sdhci-8.9a" },
	293	{ }
	294	};
	295
	296	U_BOOT_DRIVER(arasan_sdhci_drv) = {
	297	.name = "arasan_sdhci",
	298	.id = UCLASS_MMC,
	299	.of_match = arasan_sdhci_ids,
	300	.ofdata_to_platdata = arasan_sdhci_ofdata_to_platdata,
329a449f SG	301	.ops = &sdhci_ops,
329a449f SG	302	.bind = arasan_sdhci_bind,
d9ae52c8	303	.probe = arasan_sdhci_probe,
d1f4e39d	304	.priv_auto_alloc_size = sizeof(struct arasan_sdhci_priv),
329a449f	305	.platdata_auto_alloc_size = sizeof(struct arasan_sdhci_plat),
d9ae52c8	306	};