[J-u-boot.git] / include / configs / da850evm.h

/* SPDX-License-Identifier: GPL-2.0+ */
/*
 * Copyright (C) 2010 Texas Instruments Incorporated - http://www.ti.com/
 *
 * Based on davinci_dvevm.h. Original Copyrights follow:
 *
 * Copyright (C) 2007 Sergey Kubushyn <[email protected]>
 */

#ifndef __CONFIG_H
#define __CONFIG_H

/*
 * Board
 */
/* check if direct NOR boot config is used */
#ifndef CONFIG_DIRECT_NOR_BOOT
#define CONFIG_USE_SPIFLASH
#endif

/*
 * SoC Configuration
 */
#define CONFIG_SYS_EXCEPTION_VECTORS_HIGH
#define CONFIG_SYS_CLK_FREQ		clk_get(DAVINCI_ARM_CLKID)
#define CONFIG_SYS_OSCIN_FREQ		24000000
#define CONFIG_SYS_TIMERBASE		DAVINCI_TIMER0_BASE
#define CONFIG_SYS_HZ_CLOCK		clk_get(DAVINCI_AUXCLK_CLKID)
#define CONFIG_SKIP_LOWLEVEL_INIT_ONLY

#ifdef CONFIG_DIRECT_NOR_BOOT
#define CONFIG_ARCH_CPU_INIT
#define CONFIG_SYS_DV_NOR_BOOT_CFG	(0x11)
#endif

/*
 * Memory Info
 */
#define CONFIG_SYS_MALLOC_LEN	(0x10000 + 1*1024*1024) /* malloc() len */
#define PHYS_SDRAM_1		DAVINCI_DDR_EMIF_DATA_BASE /* DDR Start */
#define PHYS_SDRAM_1_SIZE	(64 << 20) /* SDRAM size 64MB */
#define CONFIG_MAX_RAM_BANK_SIZE (512 << 20) /* max size from SPRS586*/
#define CONFIG_SPL_BSS_START_ADDR DAVINCI_DDR_EMIF_DATA_BASE
#define CONFIG_SPL_BSS_MAX_SIZE 0x1080000
/* memtest start addr */
#define CONFIG_SYS_MEMTEST_START	(PHYS_SDRAM_1 + 0x2000000)

/* memtest will be run on 16MB */
#define CONFIG_SYS_MEMTEST_END 	(PHYS_SDRAM_1 + 0x2000000 + 16*1024*1024)

#define CONFIG_SYS_DA850_SYSCFG_SUSPSRC (	\
	DAVINCI_SYSCFG_SUSPSRC_TIMER0 |		\
	DAVINCI_SYSCFG_SUSPSRC_SPI1 |		\
	DAVINCI_SYSCFG_SUSPSRC_UART2 |		\
	DAVINCI_SYSCFG_SUSPSRC_EMAC |		\
	DAVINCI_SYSCFG_SUSPSRC_I2C)

/*
 * PLL configuration
 */

#define CONFIG_SYS_DA850_PLL0_PLLM     24
#define CONFIG_SYS_DA850_PLL1_PLLM     21

/*
 * DDR2 memory configuration
 */
#define CONFIG_SYS_DA850_DDR2_DDRPHYCR (DV_DDR_PHY_PWRDNEN | \
					DV_DDR_PHY_EXT_STRBEN | \
					(0x4 << DV_DDR_PHY_RD_LATENCY_SHIFT))

#define CONFIG_SYS_DA850_DDR2_SDBCR (		\
	(1 << DV_DDR_SDCR_MSDRAMEN_SHIFT) |	\
	(1 << DV_DDR_SDCR_DDREN_SHIFT) |	\
	(1 << DV_DDR_SDCR_SDRAMEN_SHIFT) |	\
	(1 << DV_DDR_SDCR_BUS_WIDTH_SHIFT) |	\
	(0x3 << DV_DDR_SDCR_CL_SHIFT) |		\
	(0x2 << DV_DDR_SDCR_IBANK_SHIFT) |	\
	(0x2 << DV_DDR_SDCR_PAGESIZE_SHIFT))

/* SDBCR2 is only used if IBANK_POS bit in SDBCR is set */
#define CONFIG_SYS_DA850_DDR2_SDBCR2 0

#define CONFIG_SYS_DA850_DDR2_SDTIMR (		\
	(14 << DV_DDR_SDTMR1_RFC_SHIFT) |	\
	(2 << DV_DDR_SDTMR1_RP_SHIFT) |		\
	(2 << DV_DDR_SDTMR1_RCD_SHIFT) |	\
	(1 << DV_DDR_SDTMR1_WR_SHIFT) |		\
	(5 << DV_DDR_SDTMR1_RAS_SHIFT) |	\
	(8 << DV_DDR_SDTMR1_RC_SHIFT) |		\
	(1 << DV_DDR_SDTMR1_RRD_SHIFT) |	\
	(0 << DV_DDR_SDTMR1_WTR_SHIFT))

#define CONFIG_SYS_DA850_DDR2_SDTIMR2 (		\
	(7 << DV_DDR_SDTMR2_RASMAX_SHIFT) |	\
	(0 << DV_DDR_SDTMR2_XP_SHIFT) |		\
	(0 << DV_DDR_SDTMR2_ODT_SHIFT) |	\
	(17 << DV_DDR_SDTMR2_XSNR_SHIFT) |	\
	(199 << DV_DDR_SDTMR2_XSRD_SHIFT) |	\
	(0 << DV_DDR_SDTMR2_RTP_SHIFT) |	\
	(0 << DV_DDR_SDTMR2_CKE_SHIFT))

#define CONFIG_SYS_DA850_DDR2_SDRCR    0x00000494
#define CONFIG_SYS_DA850_DDR2_PBBPR    0x30

/*
 * Serial Driver info
 */
#define CONFIG_SYS_NS16550_CLK	clk_get(DAVINCI_UART2_CLKID)

#define CONFIG_SYS_SPI_CLK		clk_get(DAVINCI_SPI1_CLKID)

#ifdef CONFIG_USE_SPIFLASH
#define CONFIG_SYS_SPI_U_BOOT_OFFS	0x8000
#define CONFIG_SYS_SPI_U_BOOT_SIZE	0x40000
#endif

/*
 * I2C Configuration
 */
#ifndef CONFIG_SPL_BUILD
#define CONFIG_SYS_I2C_EXPANDER_ADDR   0x20
#endif

/*
 * Flash & Environment
 */
#ifdef CONFIG_NAND
#ifdef CONFIG_ENV_IS_IN_NAND
#define CONFIG_ENV_OFFSET		0x0 /* Block 0--not used by bootcode */
#define CONFIG_ENV_SIZE			(128 << 10)
#define CONFIG_ENV_SECT_SIZE	(128 << 10)
#endif
#define	CONFIG_SYS_NAND_USE_FLASH_BBT
#define CONFIG_SYS_NAND_4BIT_HW_ECC_OOBFIRST
#define	CONFIG_SYS_NAND_PAGE_2K
#define CONFIG_SYS_NAND_CS		3
#define CONFIG_SYS_NAND_BASE		DAVINCI_ASYNC_EMIF_DATA_CE3_BASE
#define CONFIG_SYS_NAND_MASK_CLE		0x10
#define CONFIG_SYS_NAND_MASK_ALE		0x8
#undef CONFIG_SYS_NAND_HW_ECC
#define CONFIG_SYS_MAX_NAND_DEVICE	1 /* Max number of NAND devices */
#define CONFIG_SYS_NAND_HW_ECC_OOBFIRST
#define CONFIG_SYS_NAND_5_ADDR_CYCLE
#define CONFIG_SYS_NAND_PAGE_SIZE	(2 << 10)
#define CONFIG_SYS_NAND_BLOCK_SIZE	(128 << 10)
#define CONFIG_SYS_NAND_U_BOOT_SIZE	0x40000
#define CONFIG_SYS_NAND_U_BOOT_DST	0xc1080000
#define CONFIG_SYS_NAND_U_BOOT_START	CONFIG_SYS_NAND_U_BOOT_DST
#define CONFIG_SYS_NAND_U_BOOT_RELOC_SP	(CONFIG_SYS_NAND_U_BOOT_DST - \
					CONFIG_SYS_NAND_U_BOOT_SIZE - \
					CONFIG_SYS_MALLOC_LEN -       \
					GENERATED_GBL_DATA_SIZE)
#define CONFIG_SYS_NAND_ECCPOS		{				\
				24, 25, 26, 27, 28, \
				29, 30, 31, 32, 33, 34, 35, 36, 37, 38, \
				39, 40, 41, 42, 43, 44, 45, 46, 47, 48, \
				49, 50, 51, 52, 53, 54, 55, 56, 57, 58, \
				59, 60, 61, 62, 63 }
#define CONFIG_SYS_NAND_PAGE_COUNT	64
#define CONFIG_SYS_NAND_BAD_BLOCK_POS	0
#define CONFIG_SYS_NAND_ECCSIZE		512
#define CONFIG_SYS_NAND_ECCBYTES	10
#define CONFIG_SYS_NAND_OOBSIZE		64
#define CONFIG_SPL_NAND_BASE
#define CONFIG_SPL_NAND_DRIVERS
#define CONFIG_SPL_NAND_ECC
#define CONFIG_SPL_NAND_LOAD

#ifndef CONFIG_SPL_BUILD
#define CONFIG_SYS_NAND_SELF_INIT
#endif
#endif

/*
 * Network & Ethernet Configuration
 */
#ifdef CONFIG_DRIVER_TI_EMAC
#define CONFIG_BOOTP_DNS2
#define CONFIG_BOOTP_SEND_HOSTNAME
#define CONFIG_NET_RETRY_COUNT	10
#endif

#ifdef CONFIG_USE_NOR
#define CONFIG_SYS_MAX_FLASH_BANKS	1 /* max number of flash banks */
#define CONFIG_SYS_FLASH_SECT_SZ	(128 << 10) /* 128KB */
#define CONFIG_ENV_OFFSET		(SZ_1M)
#define CONFIG_ENV_SIZE			(10 << 10) /* 10KB */
#define CONFIG_SYS_FLASH_BASE		DAVINCI_ASYNC_EMIF_DATA_CE2_BASE
#define PHYS_FLASH_SIZE			(8 << 20) /* Flash size 8MB */
#define CONFIG_SYS_MAX_FLASH_SECT ((PHYS_FLASH_SIZE/CONFIG_SYS_FLASH_SECT_SZ)\
	       + 3)
#define CONFIG_ENV_SECT_SIZE		CONFIG_SYS_FLASH_SECT_SZ
#endif

#ifdef CONFIG_USE_SPIFLASH
#ifdef CONFIG_ENV_IS_IN_SPI_FLASH
#define CONFIG_ENV_SIZE			(64 << 10)
#define CONFIG_ENV_OFFSET		(512 << 10)
#define CONFIG_ENV_SECT_SIZE	(64 << 10)
#endif
#ifdef CONFIG_SPL_BUILD
#undef CONFIG_SPI_FLASH_MTD
#endif
#endif

/*
 * U-Boot general configuration
 */
#define CONFIG_BOOTFILE		"uImage" /* Boot file name */
#define CONFIG_SYS_CBSIZE	1024 /* Console I/O Buffer Size	*/
#define CONFIG_SYS_BARGSIZE	CONFIG_SYS_CBSIZE /* Boot Args Buffer Size */
#define CONFIG_SYS_LOAD_ADDR	(PHYS_SDRAM_1 + 0x700000)
#define CONFIG_MX_CYCLIC

/*
 * Linux Information
 */
#define LINUX_BOOT_PARAM_ADDR	(PHYS_SDRAM_1 + 0x100)
#define CONFIG_HWCONFIG		/* enable hwconfig */
#define CONFIG_CMDLINE_TAG
#define CONFIG_REVISION_TAG
#define CONFIG_SETUP_MEMORY_TAGS

#define CONFIG_BOOTCOMMAND \
		"run envboot; " \
		"run mmcboot; "

#define DEFAULT_LINUX_BOOT_ENV \
	"loadaddr=0xc0700000\0" \
	"fdtaddr=0xc0600000\0" \
	"scriptaddr=0xc0600000\0"

#include <environment/ti/mmc.h>

#define CONFIG_EXTRA_ENV_SETTINGS \
	DEFAULT_LINUX_BOOT_ENV \
	DEFAULT_MMC_TI_ARGS \
	"bootpart=0:2\0" \
	"bootdir=/boot\0" \
	"bootfile=zImage\0" \
	"fdtfile=da850-evm.dtb\0" \
	"boot_fdt=yes\0" \
	"boot_fit=0\0" \
	"console=ttyS2,115200n8\0" \
	"hwconfig=dsp:wake=yes"

#ifdef CONFIG_CMD_BDI
#define CONFIG_CLOCKS
#endif

#if !defined(CONFIG_NAND) && \
	!defined(CONFIG_USE_NOR) && \
	!defined(CONFIG_USE_SPIFLASH)
#define CONFIG_ENV_SIZE		(16 << 10)
#endif

/* USB Configs */
#define CONFIG_USB_OHCI_NEW
#define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS	15

#ifndef CONFIG_DIRECT_NOR_BOOT
/* defines for SPL */
#define CONFIG_SYS_SPL_MALLOC_START	(CONFIG_SYS_TEXT_BASE - \
						CONFIG_SYS_MALLOC_LEN)
#define CONFIG_SYS_SPL_MALLOC_SIZE	CONFIG_SYS_MALLOC_LEN
#define CONFIG_SPL_STACK	0x8001ff00
#define CONFIG_SPL_MAX_FOOTPRINT	32768
#define CONFIG_SPL_PAD_TO	32768
#endif

/* Load U-Boot Image From MMC */

/* additions for new relocation code, must added to all boards */
#define CONFIG_SYS_SDRAM_BASE		0xc0000000

#ifdef CONFIG_DIRECT_NOR_BOOT
#define CONFIG_SYS_INIT_SP_ADDR		0x8001ff00
#else
#define CONFIG_SYS_INIT_SP_ADDR		(CONFIG_SYS_SDRAM_BASE + 0x1000 - /* Fix this */ \
					GENERATED_GBL_DATA_SIZE)
#endif /* CONFIG_DIRECT_NOR_BOOT */

#include <asm/arch/hardware.h>

#endif /* __CONFIG_H */
Commit	Line	Data
83d290c5	1	/* SPDX-License-Identifier: GPL-2.0+ */
89b765c7 SR	2	/*
	3	* Copyright (C) 2010 Texas Instruments Incorporated - http://www.ti.com/
	4	*
	5	* Based on davinci_dvevm.h. Original Copyrights follow:
	6	*
	7	* Copyright (C) 2007 Sergey Kubushyn <[email protected]>
89b765c7 SR	8	*/
	9
	10	#ifndef __CONFIG_H
	11	#define __CONFIG_H
	12
	13	/*
	14	* Board
	15	*/
63777665 LP	16	/* check if direct NOR boot config is used */
63777665 LP	17	#ifndef CONFIG_DIRECT_NOR_BOOT
d73a8a1b	18	#define CONFIG_USE_SPIFLASH
63777665	19	#endif
89b765c7 SR	20
	21	/*
	22	* SoC Configuration
	23	*/
b67d8816	24	#define CONFIG_SYS_EXCEPTION_VECTORS_HIGH
89b765c7 SR	25	#define CONFIG_SYS_CLK_FREQ clk_get(DAVINCI_ARM_CLKID)
	26	#define CONFIG_SYS_OSCIN_FREQ 24000000
	27	#define CONFIG_SYS_TIMERBASE DAVINCI_TIMER0_BASE
	28	#define CONFIG_SYS_HZ_CLOCK clk_get(DAVINCI_AUXCLK_CLKID)
66e2637b	29	#define CONFIG_SKIP_LOWLEVEL_INIT_ONLY
89b765c7	30
63777665 LP	31	#ifdef CONFIG_DIRECT_NOR_BOOT
63777665 LP	32	#define CONFIG_ARCH_CPU_INIT
63777665	33	#define CONFIG_SYS_DV_NOR_BOOT_CFG (0x11)
63777665 LP	34	#endif
63777665 LP	35
89b765c7 SR	36	/*
	37	* Memory Info
	38	*/
	39	#define CONFIG_SYS_MALLOC_LEN (0x10000 + 110241024) /* malloc() len */
89b765c7 SR	40	#define PHYS_SDRAM_1 DAVINCI_DDR_EMIF_DATA_BASE /* DDR Start */
89b765c7 SR	41	#define PHYS_SDRAM_1_SIZE (64 << 20) /* SDRAM size 64MB */
97003756	42	#define CONFIG_MAX_RAM_BANK_SIZE (512 << 20) /* max size from SPRS586*/
15b8c750 AF	43	#define CONFIG_SPL_BSS_START_ADDR DAVINCI_DDR_EMIF_DATA_BASE
15b8c750 AF	44	#define CONFIG_SPL_BSS_MAX_SIZE 0x1080000
89b765c7 SR	45	/* memtest start addr */
	46	#define CONFIG_SYS_MEMTEST_START (PHYS_SDRAM_1 + 0x2000000)
	47
	48	/* memtest will be run on 16MB */
	49	#define CONFIG_SYS_MEMTEST_END (PHYS_SDRAM_1 + 0x2000000 + 1610241024)
	50
3d2c8e6c CR	51	#define CONFIG_SYS_DA850_SYSCFG_SUSPSRC ( \
	52	DAVINCI_SYSCFG_SUSPSRC_TIMER0 \| \
	53	DAVINCI_SYSCFG_SUSPSRC_SPI1 \| \
	54	DAVINCI_SYSCFG_SUSPSRC_UART2 \| \
	55	DAVINCI_SYSCFG_SUSPSRC_EMAC \| \
	56	DAVINCI_SYSCFG_SUSPSRC_I2C)
	57
	58	/*
	59	* PLL configuration
	60	*/
3d2c8e6c CR	61
	62	#define CONFIG_SYS_DA850_PLL0_PLLM 24
	63	#define CONFIG_SYS_DA850_PLL1_PLLM 21
	64
	65	/*
	66	* DDR2 memory configuration
	67	*/
	68	#define CONFIG_SYS_DA850_DDR2_DDRPHYCR (DV_DDR_PHY_PWRDNEN \| \
	69	DV_DDR_PHY_EXT_STRBEN \| \
	70	(0x4 << DV_DDR_PHY_RD_LATENCY_SHIFT))
	71
	72	#define CONFIG_SYS_DA850_DDR2_SDBCR ( \
	73	(1 << DV_DDR_SDCR_MSDRAMEN_SHIFT) \| \
	74	(1 << DV_DDR_SDCR_DDREN_SHIFT) \| \
	75	(1 << DV_DDR_SDCR_SDRAMEN_SHIFT) \| \
	76	(1 << DV_DDR_SDCR_BUS_WIDTH_SHIFT) \| \
	77	(0x3 << DV_DDR_SDCR_CL_SHIFT) \| \
	78	(0x2 << DV_DDR_SDCR_IBANK_SHIFT) \| \
	79	(0x2 << DV_DDR_SDCR_PAGESIZE_SHIFT))
	80
	81	/* SDBCR2 is only used if IBANK_POS bit in SDBCR is set */
	82	#define CONFIG_SYS_DA850_DDR2_SDBCR2 0
	83
	84	#define CONFIG_SYS_DA850_DDR2_SDTIMR ( \
	85	(14 << DV_DDR_SDTMR1_RFC_SHIFT) \| \
	86	(2 << DV_DDR_SDTMR1_RP_SHIFT) \| \
	87	(2 << DV_DDR_SDTMR1_RCD_SHIFT) \| \
	88	(1 << DV_DDR_SDTMR1_WR_SHIFT) \| \
	89	(5 << DV_DDR_SDTMR1_RAS_SHIFT) \| \
	90	(8 << DV_DDR_SDTMR1_RC_SHIFT) \| \
	91	(1 << DV_DDR_SDTMR1_RRD_SHIFT) \| \
	92	(0 << DV_DDR_SDTMR1_WTR_SHIFT))
	93
	94	#define CONFIG_SYS_DA850_DDR2_SDTIMR2 ( \
	95	(7 << DV_DDR_SDTMR2_RASMAX_SHIFT) \| \
	96	(0 << DV_DDR_SDTMR2_XP_SHIFT) \| \
	97	(0 << DV_DDR_SDTMR2_ODT_SHIFT) \| \
	98	(17 << DV_DDR_SDTMR2_XSNR_SHIFT) \| \
	99	(199 << DV_DDR_SDTMR2_XSRD_SHIFT) \| \
	100	(0 << DV_DDR_SDTMR2_RTP_SHIFT) \| \
	101	(0 << DV_DDR_SDTMR2_CKE_SHIFT))
	102
	103	#define CONFIG_SYS_DA850_DDR2_SDRCR 0x00000494
	104	#define CONFIG_SYS_DA850_DDR2_PBBPR 0x30
	105
89b765c7 SR	106	/*
	107	* Serial Driver info
	108	*/
89b765c7	109	#define CONFIG_SYS_NS16550_CLK clk_get(DAVINCI_UART2_CLKID)
89b765c7	110
d73a8a1b	111	#define CONFIG_SYS_SPI_CLK clk_get(DAVINCI_SPI1_CLKID)
d73a8a1b	112
42612104	113	#ifdef CONFIG_USE_SPIFLASH
42612104	114	#define CONFIG_SYS_SPI_U_BOOT_OFFS 0x8000
2a10f8b9	115	#define CONFIG_SYS_SPI_U_BOOT_SIZE 0x40000
42612104 LP	116	#endif
42612104 LP	117
89b765c7 SR	118	/*
	119	* I2C Configuration
	120	*/
c774207f	121	#ifndef CONFIG_SPL_BUILD
d2607401	122	#define CONFIG_SYS_I2C_EXPANDER_ADDR 0x20
c774207f	123	#endif
89b765c7	124
6b2c6468 BG	125	/*
	126	* Flash & Environment
	127	*/
8d0d6bc1	128	#ifdef CONFIG_NAND
93f33627	129	#ifdef CONFIG_ENV_IS_IN_NAND
6b2c6468 BG	130	#define CONFIG_ENV_OFFSET 0x0 /* Block 0--not used by bootcode */
6b2c6468 BG	131	#define CONFIG_ENV_SIZE (128 << 10)
93f33627 AF	132	#define CONFIG_ENV_SECT_SIZE (128 << 10)
93f33627 AF	133	#endif
6b2c6468 BG	134	#define CONFIG_SYS_NAND_USE_FLASH_BBT
	135	#define CONFIG_SYS_NAND_4BIT_HW_ECC_OOBFIRST
	136	#define CONFIG_SYS_NAND_PAGE_2K
	137	#define CONFIG_SYS_NAND_CS 3
	138	#define CONFIG_SYS_NAND_BASE DAVINCI_ASYNC_EMIF_DATA_CE3_BASE
34fa0706 EB	139	#define CONFIG_SYS_NAND_MASK_CLE 0x10
34fa0706 EB	140	#define CONFIG_SYS_NAND_MASK_ALE 0x8
6b2c6468 BG	141	#undef CONFIG_SYS_NAND_HW_ECC
6b2c6468 BG	142	#define CONFIG_SYS_MAX_NAND_DEVICE 1 /* Max number of NAND devices */
122f9c9b LP	143	#define CONFIG_SYS_NAND_HW_ECC_OOBFIRST
	144	#define CONFIG_SYS_NAND_5_ADDR_CYCLE
	145	#define CONFIG_SYS_NAND_PAGE_SIZE (2 << 10)
	146	#define CONFIG_SYS_NAND_BLOCK_SIZE (128 << 10)
93f33627	147	#define CONFIG_SYS_NAND_U_BOOT_SIZE 0x40000
122f9c9b LP	148	#define CONFIG_SYS_NAND_U_BOOT_DST 0xc1080000
	149	#define CONFIG_SYS_NAND_U_BOOT_START CONFIG_SYS_NAND_U_BOOT_DST
	150	#define CONFIG_SYS_NAND_U_BOOT_RELOC_SP (CONFIG_SYS_NAND_U_BOOT_DST - \
	151	CONFIG_SYS_NAND_U_BOOT_SIZE - \
	152	CONFIG_SYS_MALLOC_LEN - \
	153	GENERATED_GBL_DATA_SIZE)
	154	#define CONFIG_SYS_NAND_ECCPOS { \
	155	24, 25, 26, 27, 28, \
	156	29, 30, 31, 32, 33, 34, 35, 36, 37, 38, \
	157	39, 40, 41, 42, 43, 44, 45, 46, 47, 48, \
	158	49, 50, 51, 52, 53, 54, 55, 56, 57, 58, \
	159	59, 60, 61, 62, 63 }
	160	#define CONFIG_SYS_NAND_PAGE_COUNT 64
	161	#define CONFIG_SYS_NAND_BAD_BLOCK_POS 0
	162	#define CONFIG_SYS_NAND_ECCSIZE 512
	163	#define CONFIG_SYS_NAND_ECCBYTES 10
	164	#define CONFIG_SYS_NAND_OOBSIZE 64
6f2f01b9 SW	165	#define CONFIG_SPL_NAND_BASE
	166	#define CONFIG_SPL_NAND_DRIVERS
	167	#define CONFIG_SPL_NAND_ECC
122f9c9b	168	#define CONFIG_SPL_NAND_LOAD
95cffd99 BG	169
	170	#ifndef CONFIG_SPL_BUILD
	171	#define CONFIG_SYS_NAND_SELF_INIT
	172	#endif
6b2c6468 BG	173	#endif
6b2c6468 BG	174
3d248d37 BG	175	/*
	176	* Network & Ethernet Configuration
	177	*/
	178	#ifdef CONFIG_DRIVER_TI_EMAC
3d248d37 BG	179	#define CONFIG_BOOTP_DNS2
	180	#define CONFIG_BOOTP_SEND_HOSTNAME
	181	#define CONFIG_NET_RETRY_COUNT 10
3d248d37 BG	182	#endif
3d248d37 BG	183
1506b0a8	184	#ifdef CONFIG_USE_NOR
1506b0a8 NN	185	#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of flash banks */
1506b0a8 NN	186	#define CONFIG_SYS_FLASH_SECT_SZ (128 << 10) /* 128KB */
d2c30190	187	#define CONFIG_ENV_OFFSET (SZ_1M)
1506b0a8 NN	188	#define CONFIG_ENV_SIZE (10 << 10) /* 10KB */
	189	#define CONFIG_SYS_FLASH_BASE DAVINCI_ASYNC_EMIF_DATA_CE2_BASE
	190	#define PHYS_FLASH_SIZE (8 << 20) /* Flash size 8MB */
	191	#define CONFIG_SYS_MAX_FLASH_SECT ((PHYS_FLASH_SIZE/CONFIG_SYS_FLASH_SECT_SZ)\
	192	+ 3)
	193	#define CONFIG_ENV_SECT_SIZE CONFIG_SYS_FLASH_SECT_SZ
	194	#endif
	195
d73a8a1b	196	#ifdef CONFIG_USE_SPIFLASH
93f33627	197	#ifdef CONFIG_ENV_IS_IN_SPI_FLASH
d73a8a1b	198	#define CONFIG_ENV_SIZE (64 << 10)
2a10f8b9	199	#define CONFIG_ENV_OFFSET (512 << 10)
93f33627 AF	200	#define CONFIG_ENV_SECT_SIZE (64 << 10)
93f33627 AF	201	#endif
f4fad716 AF	202	#ifdef CONFIG_SPL_BUILD
	203	#undef CONFIG_SPI_FLASH_MTD
	204	#endif
d73a8a1b SB	205	#endif
d73a8a1b SB	206
89b765c7 SR	207	/*
	208	* U-Boot general configuration
	209	*/
	210	#define CONFIG_BOOTFILE "uImage" /* Boot file name */
89b765c7	211	#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
89b765c7 SR	212	#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Args Buffer Size */
89b765c7 SR	213	#define CONFIG_SYS_LOAD_ADDR (PHYS_SDRAM_1 + 0x700000)
89b765c7 SR	214	#define CONFIG_MX_CYCLIC
	215
	216	/*
	217	* Linux Information
	218	*/
59e0d611	219	#define LINUX_BOOT_PARAM_ADDR (PHYS_SDRAM_1 + 0x100)
cf2c24e3	220	#define CONFIG_HWCONFIG /* enable hwconfig */
89b765c7	221	#define CONFIG_CMDLINE_TAG
4f6fc15b	222	#define CONFIG_REVISION_TAG
89b765c7	223	#define CONFIG_SETUP_MEMORY_TAGS
a4670f8e AF	224
	225	#define CONFIG_BOOTCOMMAND \
	226	"run envboot; " \
	227	"run mmcboot; "
	228
	229	#define DEFAULT_LINUX_BOOT_ENV \
	230	"loadaddr=0xc0700000\0" \
	231	"fdtaddr=0xc0600000\0" \
	232	"scriptaddr=0xc0600000\0"
	233
	234	#include <environment/ti/mmc.h>
	235
	236	#define CONFIG_EXTRA_ENV_SETTINGS \
	237	DEFAULT_LINUX_BOOT_ENV \
	238	DEFAULT_MMC_TI_ARGS \
	239	"bootpart=0:2\0" \
	240	"bootdir=/boot\0" \
	241	"bootfile=zImage\0" \
	242	"fdtfile=da850-evm.dtb\0" \
	243	"boot_fdt=yes\0" \
	244	"boot_fit=0\0" \
	245	"console=ttyS2,115200n8\0" \
	246	"hwconfig=dsp:wake=yes"
89b765c7	247
8f5d4687 HM	248	#ifdef CONFIG_CMD_BDI
	249	#define CONFIG_CLOCKS
	250	#endif
	251
8d0d6bc1	252	#if !defined(CONFIG_NAND) && \
89b765c7 SR	253	!defined(CONFIG_USE_NOR) && \
89b765c7 SR	254	!defined(CONFIG_USE_SPIFLASH)
89b765c7	255	#define CONFIG_ENV_SIZE (16 << 10)
89b765c7 SR	256	#endif
89b765c7 SR	257
95468e6c	258	/* USB Configs */
95468e6c	259	#define CONFIG_USB_OHCI_NEW
95468e6c	260	#define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS 15
95468e6c	261
63777665	262	#ifndef CONFIG_DIRECT_NOR_BOOT
3d2c8e6c	263	/* defines for SPL */
3f7f2414 TR	264	#define CONFIG_SYS_SPL_MALLOC_START (CONFIG_SYS_TEXT_BASE - \
	265	CONFIG_SYS_MALLOC_LEN)
	266	#define CONFIG_SYS_SPL_MALLOC_SIZE CONFIG_SYS_MALLOC_LEN
3d2c8e6c	267	#define CONFIG_SPL_STACK 0x8001ff00
b7b5f1a1	268	#define CONFIG_SPL_MAX_FOOTPRINT 32768
532d5318	269	#define CONFIG_SPL_PAD_TO 32768
63777665	270	#endif
0d986e61 LP	271
0d986e61 LP	272	/* Load U-Boot Image From MMC */
0d986e61	273
ab86f72c	274	/* additions for new relocation code, must added to all boards */
ab86f72c	275	#define CONFIG_SYS_SDRAM_BASE 0xc0000000
63777665 LP	276
	277	#ifdef CONFIG_DIRECT_NOR_BOOT
	278	#define CONFIG_SYS_INIT_SP_ADDR 0x8001ff00
	279	#else
ab86f72c	280	#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_SDRAM_BASE + 0x1000 - /* Fix this */ \
25ddd1fb	281	GENERATED_GBL_DATA_SIZE)
63777665	282	#endif /* CONFIG_DIRECT_NOR_BOOT */
89f5eaa1 SG	283
	284	#include <asm/arch/hardware.h>
	285
89b765c7	286	#endif /* __CONFIG_H */