[J-u-boot.git] / drivers / pinctrl / rockchip / pinctrl_rk322x.c

/*
 * (C) Copyright 2017 Rockchip Electronics Co., Ltd.
 *
 * SPDX-License-Identifier:     GPL-2.0+
 */

#include <common.h>
#include <dm.h>
#include <errno.h>
#include <syscon.h>
#include <asm/io.h>
#include <asm/arch/clock.h>
#include <asm/arch/grf_rk322x.h>
#include <asm/arch/hardware.h>
#include <asm/arch/periph.h>
#include <dm/pinctrl.h>

DECLARE_GLOBAL_DATA_PTR;

struct rk322x_pinctrl_priv {
	struct rk322x_grf *grf;
};

static void pinctrl_rk322x_pwm_config(struct rk322x_grf *grf, int pwm_id)
{
	u32 mux_con = readl(&grf->con_iomux);

	switch (pwm_id) {
	case PERIPH_ID_PWM0:
		if (mux_con & CON_IOMUX_PWM0SEL_MASK)
			rk_clrsetreg(&grf->gpio3c_iomux, GPIO3C5_MASK,
				     GPIO3C5_PWM10 << GPIO3C5_SHIFT);
		else
			rk_clrsetreg(&grf->gpio0d_iomux, GPIO0D2_MASK,
				     GPIO0D2_PWM0 << GPIO0D2_SHIFT);
		break;
	case PERIPH_ID_PWM1:
		if (mux_con & CON_IOMUX_PWM1SEL_MASK)
			rk_clrsetreg(&grf->gpio0d_iomux, GPIO0D6_MASK,
				     GPIO0D6_PWM11 << GPIO0D6_SHIFT);
		else
			rk_clrsetreg(&grf->gpio0d_iomux, GPIO0D3_MASK,
				     GPIO0D3_PWM1 << GPIO0D3_SHIFT);
		break;
	case PERIPH_ID_PWM2:
		if (mux_con & CON_IOMUX_PWM2SEL_MASK)
			rk_clrsetreg(&grf->gpio1b_iomux, GPIO1B4_MASK,
				     GPIO1B4_PWM12 << GPIO1B4_SHIFT);
		else
			rk_clrsetreg(&grf->gpio0d_iomux, GPIO0D4_MASK,
				     GPIO0D4_PWM2 << GPIO0D4_SHIFT);
		break;
	case PERIPH_ID_PWM3:
		if (mux_con & CON_IOMUX_PWM3SEL_MASK)
			rk_clrsetreg(&grf->gpio1b_iomux, GPIO1B3_MASK,
				     GPIO1B3_PWM13 << GPIO1B3_SHIFT);
		else
			rk_clrsetreg(&grf->gpio3d_iomux, GPIO3D2_MASK,
				     GPIO3D2_PWM3 << GPIO3D2_SHIFT);
		break;
	default:
		debug("pwm id = %d iomux error!\n", pwm_id);
		break;
	}
}

static void pinctrl_rk322x_i2c_config(struct rk322x_grf *grf, int i2c_id)
{
	switch (i2c_id) {
	case PERIPH_ID_I2C0:
		rk_clrsetreg(&grf->gpio0a_iomux,
			     GPIO0A1_MASK | GPIO0A0_MASK,
			     GPIO0A1_I2C0_SDA << GPIO0A1_SHIFT |
			     GPIO0A0_I2C0_SCL << GPIO0A0_SHIFT);

		break;
	case PERIPH_ID_I2C1:
		rk_clrsetreg(&grf->gpio0a_iomux,
			     GPIO0A3_MASK | GPIO0A2_MASK,
			     GPIO0A3_I2C1_SDA << GPIO0A3_SHIFT |
			     GPIO0A2_I2C1_SCL << GPIO0A2_SHIFT);
		break;
	case PERIPH_ID_I2C2:
		rk_clrsetreg(&grf->gpio2c_iomux,
			     GPIO2C5_MASK | GPIO2C4_MASK,
			     GPIO2C5_I2C2_SCL << GPIO2C5_SHIFT |
			     GPIO2C4_I2C2_SDA << GPIO2C4_SHIFT);
		break;
	case PERIPH_ID_I2C3:
		rk_clrsetreg(&grf->gpio0a_iomux,
			     GPIO0A7_MASK | GPIO0A6_MASK,
			     GPIO0A7_I2C3_SDA << GPIO0A7_SHIFT |
			     GPIO0A6_I2C3_SCL << GPIO0A6_SHIFT);

		break;
	}
}

static void pinctrl_rk322x_spi_config(struct rk322x_grf *grf, int cs)
{
	switch (cs) {
	case 0:
		rk_clrsetreg(&grf->gpio0b_iomux, GPIO0B6_MASK,
			     GPIO0B6_SPI_CSN0 << GPIO0B6_SHIFT);
		break;
	case 1:
		rk_clrsetreg(&grf->gpio1b_iomux, GPIO1B4_MASK,
			     GPIO1B4_SPI_CSN1 << GPIO1B4_SHIFT);
		break;
	}
	rk_clrsetreg(&grf->gpio0b_iomux,
		     GPIO0B1_MASK | GPIO0B3_MASK | GPIO0B5_MASK,
		     GPIO0B5_SPI_RXD << GPIO0B5_SHIFT |
		     GPIO0B3_SPI_TXD << GPIO0B3_SHIFT |
		     GPIO0B1_SPI_CLK << GPIO0B1_SHIFT);
}

static void pinctrl_rk322x_uart_config(struct rk322x_grf *grf, int uart_id)
{
	u32 mux_con = readl(&grf->con_iomux);

	switch (uart_id) {
	case PERIPH_ID_UART1:
		if (!(mux_con & CON_IOMUX_UART1SEL_MASK))
			rk_clrsetreg(&grf->gpio1b_iomux,
				     GPIO1B1_MASK | GPIO1B2_MASK,
				     GPIO1B1_UART1_SOUT << GPIO1B1_SHIFT |
				     GPIO1B2_UART1_SIN << GPIO1B2_SHIFT);
		break;
	case PERIPH_ID_UART2:
		if (mux_con & CON_IOMUX_UART2SEL_MASK)
			rk_clrsetreg(&grf->gpio1b_iomux,
				     GPIO1B1_MASK | GPIO1B2_MASK,
				     GPIO1B1_UART21_SOUT << GPIO1B1_SHIFT |
				     GPIO1B2_UART21_SIN << GPIO1B2_SHIFT);
		else
			rk_clrsetreg(&grf->gpio1c_iomux,
				     GPIO1C3_MASK | GPIO1C2_MASK,
				     GPIO1C3_UART2_SIN << GPIO1C3_SHIFT |
				     GPIO1C2_UART2_SOUT << GPIO1C2_SHIFT);
		break;
	}
}

static void pinctrl_rk322x_sdmmc_config(struct rk322x_grf *grf, int mmc_id)
{
	switch (mmc_id) {
	case PERIPH_ID_EMMC:
		rk_clrsetreg(&grf->gpio1d_iomux, 0xffff,
			     GPIO1D7_EMMC_D7 << GPIO1D7_SHIFT |
			     GPIO1D6_EMMC_D6 << GPIO1D6_SHIFT |
			     GPIO1D5_EMMC_D5 << GPIO1D5_SHIFT |
			     GPIO1D4_EMMC_D4 << GPIO1D4_SHIFT |
			     GPIO1D3_EMMC_D3 << GPIO1D3_SHIFT |
			     GPIO1D2_EMMC_D2 << GPIO1D2_SHIFT |
			     GPIO1D1_EMMC_D1 << GPIO1D1_SHIFT |
			     GPIO1D0_EMMC_D0 << GPIO1D0_SHIFT);
		rk_clrsetreg(&grf->gpio2a_iomux,
			     GPIO2A5_MASK | GPIO2A7_MASK,
			     GPIO2A5_EMMC_PWREN << GPIO2A5_SHIFT |
			     GPIO2A7_EMMC_CLKOUT << GPIO2A7_SHIFT);
		rk_clrsetreg(&grf->gpio1c_iomux,
			     GPIO1C6_MASK | GPIO1C7_MASK,
			     GPIO1C6_EMMC_CMD << GPIO1C6_SHIFT |
			     GPIO1C7_EMMC_RSTNOUT << GPIO1C6_SHIFT);
		break;
	case PERIPH_ID_SDCARD:
		rk_clrsetreg(&grf->gpio1b_iomux,
			     GPIO1B6_MASK | GPIO1B7_MASK,
			     GPIO1B6_SDMMC_PWREN << GPIO1B6_SHIFT |
			     GPIO1B7_SDMMC_CMD << GPIO1B6_SHIFT);
		rk_clrsetreg(&grf->gpio1c_iomux, 0xfff,
			     GPIO1C5_SDMMC_D3 << GPIO1C5_SHIFT |
			     GPIO1C4_SDMMC_D2 << GPIO1C4_SHIFT |
			     GPIO1C3_SDMMC_D1 << GPIO1C3_SHIFT |
			     GPIO1C2_SDMMC_D0 << GPIO1C2_SHIFT |
			     GPIO1C1_SDMMC_DETN << GPIO1C1_SHIFT |
			     GPIO1C0_SDMMC_CLKOUT << GPIO1C0_SHIFT);
		break;
	}
}

static int rk322x_pinctrl_request(struct udevice *dev, int func, int flags)
{
	struct rk322x_pinctrl_priv *priv = dev_get_priv(dev);

	debug("%s: func=%x, flags=%x\n", __func__, func, flags);
	switch (func) {
	case PERIPH_ID_PWM0:
	case PERIPH_ID_PWM1:
	case PERIPH_ID_PWM2:
	case PERIPH_ID_PWM3:
		pinctrl_rk322x_pwm_config(priv->grf, func);
		break;
	case PERIPH_ID_I2C0:
	case PERIPH_ID_I2C1:
	case PERIPH_ID_I2C2:
		pinctrl_rk322x_i2c_config(priv->grf, func);
		break;
	case PERIPH_ID_SPI0:
		pinctrl_rk322x_spi_config(priv->grf, flags);
		break;
	case PERIPH_ID_UART0:
	case PERIPH_ID_UART1:
	case PERIPH_ID_UART2:
		pinctrl_rk322x_uart_config(priv->grf, func);
		break;
	case PERIPH_ID_SDMMC0:
	case PERIPH_ID_SDMMC1:
		pinctrl_rk322x_sdmmc_config(priv->grf, func);
		break;
	default:
		return -EINVAL;
	}

	return 0;
}

static int rk322x_pinctrl_get_periph_id(struct udevice *dev,
					struct udevice *periph)
{
	u32 cell[3];
	int ret;

	ret = fdtdec_get_int_array(gd->fdt_blob, dev_of_offset(periph),
				   "interrupts", cell, ARRAY_SIZE(cell));
	if (ret < 0)
		return -EINVAL;

	switch (cell[1]) {
	case 12:
		return PERIPH_ID_SDCARD;
	case 14:
		return PERIPH_ID_EMMC;
	case 36:
		return PERIPH_ID_I2C0;
	case 37:
		return PERIPH_ID_I2C1;
	case 38:
		return PERIPH_ID_I2C2;
	case 49:
		return PERIPH_ID_SPI0;
	case 50:
		return PERIPH_ID_PWM0;
	case 55:
		return PERIPH_ID_UART0;
	case 56:
		return PERIPH_ID_UART1;
	case 57:
		return PERIPH_ID_UART2;
	}
	return -ENOENT;
}

static int rk322x_pinctrl_set_state_simple(struct udevice *dev,
					   struct udevice *periph)
{
	int func;

	func = rk322x_pinctrl_get_periph_id(dev, periph);
	if (func < 0)
		return func;
	return rk322x_pinctrl_request(dev, func, 0);
}

static struct pinctrl_ops rk322x_pinctrl_ops = {
	.set_state_simple	= rk322x_pinctrl_set_state_simple,
	.request	= rk322x_pinctrl_request,
	.get_periph_id	= rk322x_pinctrl_get_periph_id,
};

static int rk322x_pinctrl_probe(struct udevice *dev)
{
	struct rk322x_pinctrl_priv *priv = dev_get_priv(dev);

	priv->grf = syscon_get_first_range(ROCKCHIP_SYSCON_GRF);
	debug("%s: grf=%p\n", __func__, priv->grf);
	return 0;
}

static const struct udevice_id rk322x_pinctrl_ids[] = {
	{ .compatible = "rockchip,rk3228-pinctrl" },
	{ }
};

U_BOOT_DRIVER(pinctrl_rk3228) = {
	.name		= "pinctrl_rk3228",
	.id		= UCLASS_PINCTRL,
	.of_match	= rk322x_pinctrl_ids,
	.priv_auto_alloc_size = sizeof(struct rk322x_pinctrl_priv),
	.ops		= &rk322x_pinctrl_ops,
	.bind		= dm_scan_fdt_dev,
	.probe		= rk322x_pinctrl_probe,
};
Commit	Line	Data
5cc9d31a KY	1	/*
	2	* (C) Copyright 2017 Rockchip Electronics Co., Ltd.
	3	*
	4	* SPDX-License-Identifier: GPL-2.0+
	5	*/
	6
	7	#include <common.h>
	8	#include <dm.h>
	9	#include <errno.h>
	10	#include <syscon.h>
	11	#include <asm/io.h>
	12	#include <asm/arch/clock.h>
	13	#include <asm/arch/grf_rk322x.h>
	14	#include <asm/arch/hardware.h>
	15	#include <asm/arch/periph.h>
	16	#include <dm/pinctrl.h>
	17
	18	DECLARE_GLOBAL_DATA_PTR;
	19
	20	struct rk322x_pinctrl_priv {
	21	struct rk322x_grf *grf;
	22	};
	23
	24	static void pinctrl_rk322x_pwm_config(struct rk322x_grf *grf, int pwm_id)
	25	{
	26	u32 mux_con = readl(&grf->con_iomux);
	27
	28	switch (pwm_id) {
	29	case PERIPH_ID_PWM0:
	30	if (mux_con & CON_IOMUX_PWM0SEL_MASK)
	31	rk_clrsetreg(&grf->gpio3c_iomux, GPIO3C5_MASK,
	32	GPIO3C5_PWM10 << GPIO3C5_SHIFT);
	33	else
	34	rk_clrsetreg(&grf->gpio0d_iomux, GPIO0D2_MASK,
	35	GPIO0D2_PWM0 << GPIO0D2_SHIFT);
	36	break;
	37	case PERIPH_ID_PWM1:
	38	if (mux_con & CON_IOMUX_PWM1SEL_MASK)
	39	rk_clrsetreg(&grf->gpio0d_iomux, GPIO0D6_MASK,
	40	GPIO0D6_PWM11 << GPIO0D6_SHIFT);
	41	else
	42	rk_clrsetreg(&grf->gpio0d_iomux, GPIO0D3_MASK,
	43	GPIO0D3_PWM1 << GPIO0D3_SHIFT);
	44	break;
	45	case PERIPH_ID_PWM2:
	46	if (mux_con & CON_IOMUX_PWM2SEL_MASK)
	47	rk_clrsetreg(&grf->gpio1b_iomux, GPIO1B4_MASK,
	48	GPIO1B4_PWM12 << GPIO1B4_SHIFT);
	49	else
	50	rk_clrsetreg(&grf->gpio0d_iomux, GPIO0D4_MASK,
	51	GPIO0D4_PWM2 << GPIO0D4_SHIFT);
	52	break;
	53	case PERIPH_ID_PWM3:
	54	if (mux_con & CON_IOMUX_PWM3SEL_MASK)
	55	rk_clrsetreg(&grf->gpio1b_iomux, GPIO1B3_MASK,
	56	GPIO1B3_PWM13 << GPIO1B3_SHIFT);
	57	else
	58	rk_clrsetreg(&grf->gpio3d_iomux, GPIO3D2_MASK,
	59	GPIO3D2_PWM3 << GPIO3D2_SHIFT);
	60	break;
	61	default:
	62	debug("pwm id = %d iomux error!\n", pwm_id);
	63	break;
	64	}
65	}
66
67	static void pinctrl_rk322x_i2c_config(struct rk322x_grf *grf, int i2c_id)
68	{
69	switch (i2c_id) {
70	case PERIPH_ID_I2C0:
71	rk_clrsetreg(&grf->gpio0a_iomux,
72	GPIO0A1_MASK \| GPIO0A0_MASK,
73	GPIO0A1_I2C0_SDA << GPIO0A1_SHIFT \|
74	GPIO0A0_I2C0_SCL << GPIO0A0_SHIFT);
75
76	break;
77	case PERIPH_ID_I2C1:
78	rk_clrsetreg(&grf->gpio0a_iomux,
79	GPIO0A3_MASK \| GPIO0A2_MASK,
80	GPIO0A3_I2C1_SDA << GPIO0A3_SHIFT \|
81	GPIO0A2_I2C1_SCL << GPIO0A2_SHIFT);
82	break;
83	case PERIPH_ID_I2C2:
84	rk_clrsetreg(&grf->gpio2c_iomux,
85	GPIO2C5_MASK \| GPIO2C4_MASK,
86	GPIO2C5_I2C2_SCL << GPIO2C5_SHIFT \|
87	GPIO2C4_I2C2_SDA << GPIO2C4_SHIFT);
88	break;
89	case PERIPH_ID_I2C3:
90	rk_clrsetreg(&grf->gpio0a_iomux,
91	GPIO0A7_MASK \| GPIO0A6_MASK,
92	GPIO0A7_I2C3_SDA << GPIO0A7_SHIFT \|
93	GPIO0A6_I2C3_SCL << GPIO0A6_SHIFT);
94
95	break;
96	}
97	}
98
99	static void pinctrl_rk322x_spi_config(struct rk322x_grf *grf, int cs)
100	{
101	switch (cs) {
102	case 0:
103	rk_clrsetreg(&grf->gpio0b_iomux, GPIO0B6_MASK,
104	GPIO0B6_SPI_CSN0 << GPIO0B6_SHIFT);
105	break;
106	case 1:
107	rk_clrsetreg(&grf->gpio1b_iomux, GPIO1B4_MASK,
108	GPIO1B4_SPI_CSN1 << GPIO1B4_SHIFT);
109	break;
110	}
111	rk_clrsetreg(&grf->gpio0b_iomux,
112	GPIO0B1_MASK \| GPIO0B3_MASK \| GPIO0B5_MASK,
113	GPIO0B5_SPI_RXD << GPIO0B5_SHIFT \|
114	GPIO0B3_SPI_TXD << GPIO0B3_SHIFT \|
115	GPIO0B1_SPI_CLK << GPIO0B1_SHIFT);
116	}
117
118	static void pinctrl_rk322x_uart_config(struct rk322x_grf *grf, int uart_id)
119	{
120	u32 mux_con = readl(&grf->con_iomux);
121
122	switch (uart_id) {
123	case PERIPH_ID_UART1:
124	if (!(mux_con & CON_IOMUX_UART1SEL_MASK))
125	rk_clrsetreg(&grf->gpio1b_iomux,
126	GPIO1B1_MASK \| GPIO1B2_MASK,
127	GPIO1B1_UART1_SOUT << GPIO1B1_SHIFT \|
128	GPIO1B2_UART1_SIN << GPIO1B2_SHIFT);
129	break;
130	case PERIPH_ID_UART2:
131	if (mux_con & CON_IOMUX_UART2SEL_MASK)
132	rk_clrsetreg(&grf->gpio1b_iomux,
133	GPIO1B1_MASK \| GPIO1B2_MASK,
134	GPIO1B1_UART21_SOUT << GPIO1B1_SHIFT \|
135	GPIO1B2_UART21_SIN << GPIO1B2_SHIFT);
136	else
137	rk_clrsetreg(&grf->gpio1c_iomux,
138	GPIO1C3_MASK \| GPIO1C2_MASK,
139	GPIO1C3_UART2_SIN << GPIO1C3_SHIFT \|
140	GPIO1C2_UART2_SOUT << GPIO1C2_SHIFT);
141	break;
142	}
143	}
144
145	static void pinctrl_rk322x_sdmmc_config(struct rk322x_grf *grf, int mmc_id)
146	{
147	switch (mmc_id) {
148	case PERIPH_ID_EMMC:
149	rk_clrsetreg(&grf->gpio1d_iomux, 0xffff,
150	GPIO1D7_EMMC_D7 << GPIO1D7_SHIFT \|
151	GPIO1D6_EMMC_D6 << GPIO1D6_SHIFT \|
152	GPIO1D5_EMMC_D5 << GPIO1D5_SHIFT \|
153	GPIO1D4_EMMC_D4 << GPIO1D4_SHIFT \|
154	GPIO1D3_EMMC_D3 << GPIO1D3_SHIFT \|
155	GPIO1D2_EMMC_D2 << GPIO1D2_SHIFT \|
156	GPIO1D1_EMMC_D1 << GPIO1D1_SHIFT \|
157	GPIO1D0_EMMC_D0 << GPIO1D0_SHIFT);
158	rk_clrsetreg(&grf->gpio2a_iomux,
159	GPIO2A5_MASK \| GPIO2A7_MASK,
160	GPIO2A5_EMMC_PWREN << GPIO2A5_SHIFT \|
161	GPIO2A7_EMMC_CLKOUT << GPIO2A7_SHIFT);
162	rk_clrsetreg(&grf->gpio1c_iomux,
163	GPIO1C6_MASK \| GPIO1C7_MASK,
164	GPIO1C6_EMMC_CMD << GPIO1C6_SHIFT \|
165	GPIO1C7_EMMC_RSTNOUT << GPIO1C6_SHIFT);
166	break;
167	case PERIPH_ID_SDCARD:
168	rk_clrsetreg(&grf->gpio1b_iomux,
169	GPIO1B6_MASK \| GPIO1B7_MASK,
170	GPIO1B6_SDMMC_PWREN << GPIO1B6_SHIFT \|
171	GPIO1B7_SDMMC_CMD << GPIO1B6_SHIFT);
172	rk_clrsetreg(&grf->gpio1c_iomux, 0xfff,
173	GPIO1C5_SDMMC_D3 << GPIO1C5_SHIFT \|
174	GPIO1C4_SDMMC_D2 << GPIO1C4_SHIFT \|
175	GPIO1C3_SDMMC_D1 << GPIO1C3_SHIFT \|
176	GPIO1C2_SDMMC_D0 << GPIO1C2_SHIFT \|
177	GPIO1C1_SDMMC_DETN << GPIO1C1_SHIFT \|
178	GPIO1C0_SDMMC_CLKOUT << GPIO1C0_SHIFT);
179	break;
180	}
181	}
182
183	static int rk322x_pinctrl_request(struct udevice *dev, int func, int flags)
184	{
185	struct rk322x_pinctrl_priv *priv = dev_get_priv(dev);
186
187	debug("%s: func=%x, flags=%x\n", __func__, func, flags);
188	switch (func) {
189	case PERIPH_ID_PWM0:
190	case PERIPH_ID_PWM1:
191	case PERIPH_ID_PWM2:
192	case PERIPH_ID_PWM3:
193	pinctrl_rk322x_pwm_config(priv->grf, func);
194	break;
195	case PERIPH_ID_I2C0:
196	case PERIPH_ID_I2C1:
197	case PERIPH_ID_I2C2:
198	pinctrl_rk322x_i2c_config(priv->grf, func);
199	break;
200	case PERIPH_ID_SPI0:
201	pinctrl_rk322x_spi_config(priv->grf, flags);
202	break;
203	case PERIPH_ID_UART0:
204	case PERIPH_ID_UART1:
205	case PERIPH_ID_UART2:
206	pinctrl_rk322x_uart_config(priv->grf, func);
207	break;
208	case PERIPH_ID_SDMMC0:
209	case PERIPH_ID_SDMMC1:
210	pinctrl_rk322x_sdmmc_config(priv->grf, func);
211	break;
212	default:
213	return -EINVAL;
214	}
215
216	return 0;
217	}
218
219	static int rk322x_pinctrl_get_periph_id(struct udevice *dev,
220	struct udevice *periph)
221	{
222	u32 cell[3];
223	int ret;
224
225	ret = fdtdec_get_int_array(gd->fdt_blob, dev_of_offset(periph),
226	"interrupts", cell, ARRAY_SIZE(cell));
227	if (ret < 0)
228	return -EINVAL;
229
230	switch (cell[1]) {
231	case 12:
232	return PERIPH_ID_SDCARD;
233	case 14:
234	return PERIPH_ID_EMMC;
235	case 36:
236	return PERIPH_ID_I2C0;
237	case 37:
238	return PERIPH_ID_I2C1;
239	case 38:
240	return PERIPH_ID_I2C2;
241	case 49:
242	return PERIPH_ID_SPI0;
243	case 50:
244	return PERIPH_ID_PWM0;
245	case 55:
246	return PERIPH_ID_UART0;
247	case 56:
248	return PERIPH_ID_UART1;
249	case 57:
250	return PERIPH_ID_UART2;
251	}
252	return -ENOENT;
253	}
254
255	static int rk322x_pinctrl_set_state_simple(struct udevice *dev,
256	struct udevice *periph)
257	{
258	int func;
259
260	func = rk322x_pinctrl_get_periph_id(dev, periph);
261	if (func < 0)
262	return func;
263	return rk322x_pinctrl_request(dev, func, 0);
264	}
265
266	static struct pinctrl_ops rk322x_pinctrl_ops = {
267	.set_state_simple = rk322x_pinctrl_set_state_simple,
268	.request = rk322x_pinctrl_request,
269	.get_periph_id = rk322x_pinctrl_get_periph_id,
270	};
271
272	static int rk322x_pinctrl_probe(struct udevice *dev)
273	{
274	struct rk322x_pinctrl_priv *priv = dev_get_priv(dev);
275
276	priv->grf = syscon_get_first_range(ROCKCHIP_SYSCON_GRF);
277	debug("%s: grf=%p\n", __func__, priv->grf);
278	return 0;
279	}
280
281	static const struct udevice_id rk322x_pinctrl_ids[] = {
a634236b	282	{ .compatible = "rockchip,rk3228-pinctrl" },
5cc9d31a KY	283	{ }
	284	};
	285
a634236b KY	286	U_BOOT_DRIVER(pinctrl_rk3228) = {
a634236b KY	287	.name = "pinctrl_rk3228",
5cc9d31a KY	288	.id = UCLASS_PINCTRL,
	289	.of_match = rk322x_pinctrl_ids,
	290	.priv_auto_alloc_size = sizeof(struct rk322x_pinctrl_priv),
	291	.ops = &rk322x_pinctrl_ops,
	292	.bind = dm_scan_fdt_dev,
	293	.probe = rk322x_pinctrl_probe,
	294	};