[J-u-boot.git] / board / denx / m28evk / spl_boot.c

/*
 * DENX M28 Boot setup
 *
 * Copyright (C) 2011 Marek Vasut <[email protected]>
 * on behalf of DENX Software Engineering GmbH
 *
 * SPDX-License-Identifier:	GPL-2.0+
 */

#include <common.h>
#include <config.h>
#include <asm/io.h>
#include <asm/arch/iomux-mx28.h>
#include <asm/arch/imx-regs.h>
#include <asm/arch/sys_proto.h>

#define	MUX_CONFIG_LED	(MXS_PAD_3V3 | MXS_PAD_4MA | MXS_PAD_NOPULL)
#define	MUX_CONFIG_LCD	(MXS_PAD_3V3 | MXS_PAD_4MA | MXS_PAD_NOPULL)
#define	MUX_CONFIG_TSC	(MXS_PAD_3V3 | MXS_PAD_8MA | MXS_PAD_PULLUP)
#define	MUX_CONFIG_SSP0	(MXS_PAD_3V3 | MXS_PAD_12MA | MXS_PAD_PULLUP)
#define	MUX_CONFIG_SSP2	(MXS_PAD_3V3 | MXS_PAD_4MA | MXS_PAD_PULLUP)
#define	MUX_CONFIG_GPMI	(MXS_PAD_1V8 | MXS_PAD_4MA | MXS_PAD_NOPULL)
#define	MUX_CONFIG_ENET	(MXS_PAD_3V3 | MXS_PAD_4MA | MXS_PAD_PULLUP)
#define	MUX_CONFIG_EMI	(MXS_PAD_3V3 | MXS_PAD_12MA | MXS_PAD_NOPULL)

const iomux_cfg_t iomux_setup[] = {
	/* LED */
	MX28_PAD_ENET0_RXD3__GPIO_4_10 | MUX_CONFIG_LED,

	/* framebuffer */
	MX28_PAD_LCD_D00__LCD_D0 | MUX_CONFIG_LCD,
	MX28_PAD_LCD_D01__LCD_D1 | MUX_CONFIG_LCD,
	MX28_PAD_LCD_D02__LCD_D2 | MUX_CONFIG_LCD,
	MX28_PAD_LCD_D03__LCD_D3 | MUX_CONFIG_LCD,
	MX28_PAD_LCD_D04__LCD_D4 | MUX_CONFIG_LCD,
	MX28_PAD_LCD_D05__LCD_D5 | MUX_CONFIG_LCD,
	MX28_PAD_LCD_D06__LCD_D6 | MUX_CONFIG_LCD,
	MX28_PAD_LCD_D07__LCD_D7 | MUX_CONFIG_LCD,
	MX28_PAD_LCD_D08__LCD_D8 | MUX_CONFIG_LCD,
	MX28_PAD_LCD_D09__LCD_D9 | MUX_CONFIG_LCD,
	MX28_PAD_LCD_D10__LCD_D10 | MUX_CONFIG_LCD,
	MX28_PAD_LCD_D11__LCD_D11 | MUX_CONFIG_LCD,
	MX28_PAD_LCD_D12__LCD_D12 | MUX_CONFIG_LCD,
	MX28_PAD_LCD_D13__LCD_D13 | MUX_CONFIG_LCD,
	MX28_PAD_LCD_D14__LCD_D14 | MUX_CONFIG_LCD,
	MX28_PAD_LCD_D15__LCD_D15 | MUX_CONFIG_LCD,
	MX28_PAD_LCD_D16__LCD_D16 | MUX_CONFIG_LCD,
	MX28_PAD_LCD_D17__LCD_D17 | MUX_CONFIG_LCD,
	MX28_PAD_LCD_D18__LCD_D18 | MUX_CONFIG_LCD,
	MX28_PAD_LCD_D19__LCD_D19 | MUX_CONFIG_LCD,
	MX28_PAD_LCD_D20__LCD_D20 | MUX_CONFIG_LCD,
	MX28_PAD_LCD_D21__LCD_D21 | MUX_CONFIG_LCD,
	MX28_PAD_LCD_D22__LCD_D22 | MUX_CONFIG_LCD,
	MX28_PAD_LCD_D23__LCD_D23 | MUX_CONFIG_LCD,
	MX28_PAD_LCD_DOTCLK__LCD_DOTCLK | MUX_CONFIG_LCD,
	MX28_PAD_LCD_ENABLE__LCD_ENABLE | MUX_CONFIG_LCD,

	/* UART1 */
#ifdef	CONFIG_DENX_M28_V10
	MX28_PAD_AUART0_CTS__DUART_RX,
	MX28_PAD_AUART0_RTS__DUART_TX,
#else
	MX28_PAD_PWM0__DUART_RX,
	MX28_PAD_PWM1__DUART_TX,
#endif
	MX28_PAD_AUART0_TX__DUART_RTS,
	MX28_PAD_AUART0_RX__DUART_CTS,

	/* UART2 */
	MX28_PAD_AUART1_RX__AUART1_RX,
	MX28_PAD_AUART1_TX__AUART1_TX,
	MX28_PAD_AUART1_RTS__AUART1_RTS,
	MX28_PAD_AUART1_CTS__AUART1_CTS,

	/* CAN */
	MX28_PAD_GPMI_RDY2__CAN0_TX,
	MX28_PAD_GPMI_RDY3__CAN0_RX,

	/* TSC2007 */
	MX28_PAD_SAIF0_MCLK__GPIO_3_20 | MUX_CONFIG_TSC,

	/* MMC0 */
	MX28_PAD_SSP0_DATA0__SSP0_D0 | MUX_CONFIG_SSP0,
	MX28_PAD_SSP0_DATA1__SSP0_D1 | MUX_CONFIG_SSP0,
	MX28_PAD_SSP0_DATA2__SSP0_D2 | MUX_CONFIG_SSP0,
	MX28_PAD_SSP0_DATA3__SSP0_D3 | MUX_CONFIG_SSP0,
	MX28_PAD_SSP0_DATA4__SSP0_D4 | MUX_CONFIG_SSP0,
	MX28_PAD_SSP0_DATA5__SSP0_D5 | MUX_CONFIG_SSP0,
	MX28_PAD_SSP0_DATA6__SSP0_D6 | MUX_CONFIG_SSP0,
	MX28_PAD_SSP0_DATA7__SSP0_D7 | MUX_CONFIG_SSP0,
	MX28_PAD_SSP0_CMD__SSP0_CMD | MUX_CONFIG_SSP0,
	MX28_PAD_SSP0_DETECT__SSP0_CARD_DETECT |
		(MXS_PAD_3V3 | MXS_PAD_12MA | MXS_PAD_NOPULL),
	MX28_PAD_SSP0_SCK__SSP0_SCK |
		(MXS_PAD_3V3 | MXS_PAD_12MA | MXS_PAD_NOPULL),
	MX28_PAD_PWM3__GPIO_3_28 | MUX_CONFIG_SSP0 |
		(MXS_PAD_3V3 | MXS_PAD_12MA | MXS_PAD_NOPULL),	/* Power */
	MX28_PAD_AUART2_CTS__GPIO_3_10,	/* WP */

	/* GPMI NAND */
	MX28_PAD_GPMI_D00__GPMI_D0 | MUX_CONFIG_GPMI,
	MX28_PAD_GPMI_D01__GPMI_D1 | MUX_CONFIG_GPMI,
	MX28_PAD_GPMI_D02__GPMI_D2 | MUX_CONFIG_GPMI,
	MX28_PAD_GPMI_D03__GPMI_D3 | MUX_CONFIG_GPMI,
	MX28_PAD_GPMI_D04__GPMI_D4 | MUX_CONFIG_GPMI,
	MX28_PAD_GPMI_D05__GPMI_D5 | MUX_CONFIG_GPMI,
	MX28_PAD_GPMI_D06__GPMI_D6 | MUX_CONFIG_GPMI,
	MX28_PAD_GPMI_D07__GPMI_D7 | MUX_CONFIG_GPMI,
	MX28_PAD_GPMI_CE0N__GPMI_CE0N | MUX_CONFIG_GPMI,
	MX28_PAD_GPMI_RDY0__GPMI_READY0 | MUX_CONFIG_GPMI,
	MX28_PAD_GPMI_RDN__GPMI_RDN |
		(MXS_PAD_1V8 | MXS_PAD_8MA | MXS_PAD_PULLUP),
	MX28_PAD_GPMI_WRN__GPMI_WRN | MUX_CONFIG_GPMI,
	MX28_PAD_GPMI_ALE__GPMI_ALE | MUX_CONFIG_GPMI,
	MX28_PAD_GPMI_CLE__GPMI_CLE | MUX_CONFIG_GPMI,
	MX28_PAD_GPMI_RESETN__GPMI_RESETN | MUX_CONFIG_GPMI,

	/* FEC Ethernet */
	MX28_PAD_ENET0_MDC__ENET0_MDC | MUX_CONFIG_ENET,
	MX28_PAD_ENET0_MDIO__ENET0_MDIO | MUX_CONFIG_ENET,
	MX28_PAD_ENET0_RX_EN__ENET0_RX_EN | MUX_CONFIG_ENET,
	MX28_PAD_ENET0_TX_EN__ENET0_TX_EN | MUX_CONFIG_ENET,
	MX28_PAD_ENET0_RXD0__ENET0_RXD0 | MUX_CONFIG_ENET,
	MX28_PAD_ENET0_RXD1__ENET0_RXD1 | MUX_CONFIG_ENET,
	MX28_PAD_ENET0_TXD0__ENET0_TXD0 | MUX_CONFIG_ENET,
	MX28_PAD_ENET0_TXD1__ENET0_TXD1 | MUX_CONFIG_ENET,
	MX28_PAD_ENET_CLK__CLKCTRL_ENET | MUX_CONFIG_ENET,

	MX28_PAD_ENET0_COL__ENET1_TX_EN | MUX_CONFIG_ENET,
	MX28_PAD_ENET0_CRS__ENET1_RX_EN | MUX_CONFIG_ENET,
	MX28_PAD_ENET0_RXD2__ENET1_RXD0 | MUX_CONFIG_ENET,
	MX28_PAD_ENET0_RXD3__ENET1_RXD1 | MUX_CONFIG_ENET,
	MX28_PAD_ENET0_TXD2__ENET1_TXD0 | MUX_CONFIG_ENET,
	MX28_PAD_ENET0_TXD3__ENET1_TXD1 | MUX_CONFIG_ENET,
#if !defined(CONFIG_DENX_M28_V11) && !defined(CONFIG_DENX_M28_V10)
	MX28_PAD_AUART2_RTS__GPIO_3_11,	/* PHY reset */
#endif

	/* I2C */
	MX28_PAD_I2C0_SCL__I2C0_SCL,
	MX28_PAD_I2C0_SDA__I2C0_SDA,

	/* EMI */
	MX28_PAD_EMI_D00__EMI_DATA0 | MUX_CONFIG_EMI,
	MX28_PAD_EMI_D01__EMI_DATA1 | MUX_CONFIG_EMI,
	MX28_PAD_EMI_D02__EMI_DATA2 | MUX_CONFIG_EMI,
	MX28_PAD_EMI_D03__EMI_DATA3 | MUX_CONFIG_EMI,
	MX28_PAD_EMI_D04__EMI_DATA4 | MUX_CONFIG_EMI,
	MX28_PAD_EMI_D05__EMI_DATA5 | MUX_CONFIG_EMI,
	MX28_PAD_EMI_D06__EMI_DATA6 | MUX_CONFIG_EMI,
	MX28_PAD_EMI_D07__EMI_DATA7 | MUX_CONFIG_EMI,
	MX28_PAD_EMI_D08__EMI_DATA8 | MUX_CONFIG_EMI,
	MX28_PAD_EMI_D09__EMI_DATA9 | MUX_CONFIG_EMI,
	MX28_PAD_EMI_D10__EMI_DATA10 | MUX_CONFIG_EMI,
	MX28_PAD_EMI_D11__EMI_DATA11 | MUX_CONFIG_EMI,
	MX28_PAD_EMI_D12__EMI_DATA12 | MUX_CONFIG_EMI,
	MX28_PAD_EMI_D13__EMI_DATA13 | MUX_CONFIG_EMI,
	MX28_PAD_EMI_D14__EMI_DATA14 | MUX_CONFIG_EMI,
	MX28_PAD_EMI_D15__EMI_DATA15 | MUX_CONFIG_EMI,
	MX28_PAD_EMI_ODT0__EMI_ODT0 | MUX_CONFIG_EMI,
	MX28_PAD_EMI_DQM0__EMI_DQM0 | MUX_CONFIG_EMI,
	MX28_PAD_EMI_ODT1__EMI_ODT1 | MUX_CONFIG_EMI,
	MX28_PAD_EMI_DQM1__EMI_DQM1 | MUX_CONFIG_EMI,
	MX28_PAD_EMI_DDR_OPEN_FB__EMI_DDR_OPEN_FEEDBACK | MUX_CONFIG_EMI,
	MX28_PAD_EMI_CLK__EMI_CLK | MUX_CONFIG_EMI,
	MX28_PAD_EMI_DQS0__EMI_DQS0 | MUX_CONFIG_EMI,
	MX28_PAD_EMI_DQS1__EMI_DQS1 | MUX_CONFIG_EMI,
	MX28_PAD_EMI_DDR_OPEN__EMI_DDR_OPEN | MUX_CONFIG_EMI,

	MX28_PAD_EMI_A00__EMI_ADDR0 | MUX_CONFIG_EMI,
	MX28_PAD_EMI_A01__EMI_ADDR1 | MUX_CONFIG_EMI,
	MX28_PAD_EMI_A02__EMI_ADDR2 | MUX_CONFIG_EMI,
	MX28_PAD_EMI_A03__EMI_ADDR3 | MUX_CONFIG_EMI,
	MX28_PAD_EMI_A04__EMI_ADDR4 | MUX_CONFIG_EMI,
	MX28_PAD_EMI_A05__EMI_ADDR5 | MUX_CONFIG_EMI,
	MX28_PAD_EMI_A06__EMI_ADDR6 | MUX_CONFIG_EMI,
	MX28_PAD_EMI_A07__EMI_ADDR7 | MUX_CONFIG_EMI,
	MX28_PAD_EMI_A08__EMI_ADDR8 | MUX_CONFIG_EMI,
	MX28_PAD_EMI_A09__EMI_ADDR9 | MUX_CONFIG_EMI,
	MX28_PAD_EMI_A10__EMI_ADDR10 | MUX_CONFIG_EMI,
	MX28_PAD_EMI_A11__EMI_ADDR11 | MUX_CONFIG_EMI,
	MX28_PAD_EMI_A12__EMI_ADDR12 | MUX_CONFIG_EMI,
	MX28_PAD_EMI_A13__EMI_ADDR13 | MUX_CONFIG_EMI,
	MX28_PAD_EMI_A14__EMI_ADDR14 | MUX_CONFIG_EMI,
	MX28_PAD_EMI_BA0__EMI_BA0 | MUX_CONFIG_EMI,
	MX28_PAD_EMI_BA1__EMI_BA1 | MUX_CONFIG_EMI,
	MX28_PAD_EMI_BA2__EMI_BA2 | MUX_CONFIG_EMI,
	MX28_PAD_EMI_CASN__EMI_CASN | MUX_CONFIG_EMI,
	MX28_PAD_EMI_RASN__EMI_RASN | MUX_CONFIG_EMI,
	MX28_PAD_EMI_WEN__EMI_WEN | MUX_CONFIG_EMI,
	MX28_PAD_EMI_CE0N__EMI_CE0N | MUX_CONFIG_EMI,
	MX28_PAD_EMI_CE1N__EMI_CE1N | MUX_CONFIG_EMI,
	MX28_PAD_EMI_CKE__EMI_CKE | MUX_CONFIG_EMI,

	/* SPI2 (for flash) */
	MX28_PAD_SSP2_SCK__SSP2_SCK | MUX_CONFIG_SSP2,
	MX28_PAD_SSP2_MOSI__SSP2_CMD | MUX_CONFIG_SSP2,
	MX28_PAD_SSP2_MISO__SSP2_D0 | MUX_CONFIG_SSP2,
	MX28_PAD_SSP2_SS0__SSP2_D3 |
		(MXS_PAD_3V3 | MXS_PAD_8MA | MXS_PAD_PULLUP),
};

void board_init_ll(const uint32_t arg, const uint32_t *resptr)
{
	mxs_common_spl_init(arg, resptr, iomux_setup, ARRAY_SIZE(iomux_setup));
}
Commit	Line	Data
04fe4273	1	/*
c944a3ef	2	* DENX M28 Boot setup
04fe4273 MV	3	*
	4	* Copyright (C) 2011 Marek Vasut <[email protected]>
	5	* on behalf of DENX Software Engineering GmbH
	6	*
1a459660	7	* SPDX-License-Identifier: GPL-2.0+
04fe4273 MV	8	*/
	9
	10	#include <common.h>
	11	#include <config.h>
	12	#include <asm/io.h>
	13	#include <asm/arch/iomux-mx28.h>
c944a3ef MV	14	#include <asm/arch/imx-regs.h>
c944a3ef MV	15	#include <asm/arch/sys_proto.h>
04fe4273 MV	16
04fe4273 MV	17	#define MUX_CONFIG_LED (MXS_PAD_3V3 \| MXS_PAD_4MA \| MXS_PAD_NOPULL)
f5861ccc	18	#define MUX_CONFIG_LCD (MXS_PAD_3V3 \| MXS_PAD_4MA \| MXS_PAD_NOPULL)
04fe4273 MV	19	#define MUX_CONFIG_TSC (MXS_PAD_3V3 \| MXS_PAD_8MA \| MXS_PAD_PULLUP)
	20	#define MUX_CONFIG_SSP0 (MXS_PAD_3V3 \| MXS_PAD_12MA \| MXS_PAD_PULLUP)
	21	#define MUX_CONFIG_SSP2 (MXS_PAD_3V3 \| MXS_PAD_4MA \| MXS_PAD_PULLUP)
	22	#define MUX_CONFIG_GPMI (MXS_PAD_1V8 \| MXS_PAD_4MA \| MXS_PAD_NOPULL)
	23	#define MUX_CONFIG_ENET (MXS_PAD_3V3 \| MXS_PAD_4MA \| MXS_PAD_PULLUP)
	24	#define MUX_CONFIG_EMI (MXS_PAD_3V3 \| MXS_PAD_12MA \| MXS_PAD_NOPULL)
	25
	26	const iomux_cfg_t iomux_setup[] = {
	27	/* LED */
	28	MX28_PAD_ENET0_RXD3__GPIO_4_10 \| MUX_CONFIG_LED,
	29
	30	/* framebuffer */
	31	MX28_PAD_LCD_D00__LCD_D0 \| MUX_CONFIG_LCD,
	32	MX28_PAD_LCD_D01__LCD_D1 \| MUX_CONFIG_LCD,
	33	MX28_PAD_LCD_D02__LCD_D2 \| MUX_CONFIG_LCD,
	34	MX28_PAD_LCD_D03__LCD_D3 \| MUX_CONFIG_LCD,
	35	MX28_PAD_LCD_D04__LCD_D4 \| MUX_CONFIG_LCD,
	36	MX28_PAD_LCD_D05__LCD_D5 \| MUX_CONFIG_LCD,
	37	MX28_PAD_LCD_D06__LCD_D6 \| MUX_CONFIG_LCD,
	38	MX28_PAD_LCD_D07__LCD_D7 \| MUX_CONFIG_LCD,
	39	MX28_PAD_LCD_D08__LCD_D8 \| MUX_CONFIG_LCD,
	40	MX28_PAD_LCD_D09__LCD_D9 \| MUX_CONFIG_LCD,
	41	MX28_PAD_LCD_D10__LCD_D10 \| MUX_CONFIG_LCD,
	42	MX28_PAD_LCD_D11__LCD_D11 \| MUX_CONFIG_LCD,
	43	MX28_PAD_LCD_D12__LCD_D12 \| MUX_CONFIG_LCD,
	44	MX28_PAD_LCD_D13__LCD_D13 \| MUX_CONFIG_LCD,
	45	MX28_PAD_LCD_D14__LCD_D14 \| MUX_CONFIG_LCD,
	46	MX28_PAD_LCD_D15__LCD_D15 \| MUX_CONFIG_LCD,
	47	MX28_PAD_LCD_D16__LCD_D16 \| MUX_CONFIG_LCD,
	48	MX28_PAD_LCD_D17__LCD_D17 \| MUX_CONFIG_LCD,
	49	MX28_PAD_LCD_D18__LCD_D18 \| MUX_CONFIG_LCD,
	50	MX28_PAD_LCD_D19__LCD_D19 \| MUX_CONFIG_LCD,
	51	MX28_PAD_LCD_D20__LCD_D20 \| MUX_CONFIG_LCD,
	52	MX28_PAD_LCD_D21__LCD_D21 \| MUX_CONFIG_LCD,
	53	MX28_PAD_LCD_D22__LCD_D22 \| MUX_CONFIG_LCD,
	54	MX28_PAD_LCD_D23__LCD_D23 \| MUX_CONFIG_LCD,
04fe4273	55	MX28_PAD_LCD_DOTCLK__LCD_DOTCLK \| MUX_CONFIG_LCD,
f5861ccc	56	MX28_PAD_LCD_ENABLE__LCD_ENABLE \| MUX_CONFIG_LCD,
04fe4273 MV	57
04fe4273 MV	58	/* UART1 */
af335c57 MV	59	#ifdef CONFIG_DENX_M28_V10
	60	MX28_PAD_AUART0_CTS__DUART_RX,
	61	MX28_PAD_AUART0_RTS__DUART_TX,
	62	#else
04fe4273 MV	63	MX28_PAD_PWM0__DUART_RX,
04fe4273 MV	64	MX28_PAD_PWM1__DUART_TX,
af335c57	65	#endif
04fe4273 MV	66	MX28_PAD_AUART0_TX__DUART_RTS,
	67	MX28_PAD_AUART0_RX__DUART_CTS,
	68
	69	/* UART2 */
	70	MX28_PAD_AUART1_RX__AUART1_RX,
	71	MX28_PAD_AUART1_TX__AUART1_TX,
	72	MX28_PAD_AUART1_RTS__AUART1_RTS,
	73	MX28_PAD_AUART1_CTS__AUART1_CTS,
	74
	75	/* CAN */
	76	MX28_PAD_GPMI_RDY2__CAN0_TX,
	77	MX28_PAD_GPMI_RDY3__CAN0_RX,
	78
04fe4273 MV	79	/* TSC2007 */
	80	MX28_PAD_SAIF0_MCLK__GPIO_3_20 \| MUX_CONFIG_TSC,
	81
	82	/* MMC0 */
	83	MX28_PAD_SSP0_DATA0__SSP0_D0 \| MUX_CONFIG_SSP0,
	84	MX28_PAD_SSP0_DATA1__SSP0_D1 \| MUX_CONFIG_SSP0,
	85	MX28_PAD_SSP0_DATA2__SSP0_D2 \| MUX_CONFIG_SSP0,
	86	MX28_PAD_SSP0_DATA3__SSP0_D3 \| MUX_CONFIG_SSP0,
	87	MX28_PAD_SSP0_DATA4__SSP0_D4 \| MUX_CONFIG_SSP0,
	88	MX28_PAD_SSP0_DATA5__SSP0_D5 \| MUX_CONFIG_SSP0,
	89	MX28_PAD_SSP0_DATA6__SSP0_D6 \| MUX_CONFIG_SSP0,
	90	MX28_PAD_SSP0_DATA7__SSP0_D7 \| MUX_CONFIG_SSP0,
	91	MX28_PAD_SSP0_CMD__SSP0_CMD \| MUX_CONFIG_SSP0,
	92	MX28_PAD_SSP0_DETECT__SSP0_CARD_DETECT \|
	93	(MXS_PAD_3V3 \| MXS_PAD_12MA \| MXS_PAD_NOPULL),
	94	MX28_PAD_SSP0_SCK__SSP0_SCK \|
	95	(MXS_PAD_3V3 \| MXS_PAD_12MA \| MXS_PAD_NOPULL),
b7154ec2 MV	96	MX28_PAD_PWM3__GPIO_3_28 \| MUX_CONFIG_SSP0 \|
	97	(MXS_PAD_3V3 \| MXS_PAD_12MA \| MXS_PAD_NOPULL), /* Power */
	98	MX28_PAD_AUART2_CTS__GPIO_3_10, /* WP */
04fe4273 MV	99
	100	/* GPMI NAND */
	101	MX28_PAD_GPMI_D00__GPMI_D0 \| MUX_CONFIG_GPMI,
	102	MX28_PAD_GPMI_D01__GPMI_D1 \| MUX_CONFIG_GPMI,
	103	MX28_PAD_GPMI_D02__GPMI_D2 \| MUX_CONFIG_GPMI,
	104	MX28_PAD_GPMI_D03__GPMI_D3 \| MUX_CONFIG_GPMI,
	105	MX28_PAD_GPMI_D04__GPMI_D4 \| MUX_CONFIG_GPMI,
	106	MX28_PAD_GPMI_D05__GPMI_D5 \| MUX_CONFIG_GPMI,
	107	MX28_PAD_GPMI_D06__GPMI_D6 \| MUX_CONFIG_GPMI,
	108	MX28_PAD_GPMI_D07__GPMI_D7 \| MUX_CONFIG_GPMI,
	109	MX28_PAD_GPMI_CE0N__GPMI_CE0N \| MUX_CONFIG_GPMI,
	110	MX28_PAD_GPMI_RDY0__GPMI_READY0 \| MUX_CONFIG_GPMI,
	111	MX28_PAD_GPMI_RDN__GPMI_RDN \|
	112	(MXS_PAD_1V8 \| MXS_PAD_8MA \| MXS_PAD_PULLUP),
	113	MX28_PAD_GPMI_WRN__GPMI_WRN \| MUX_CONFIG_GPMI,
	114	MX28_PAD_GPMI_ALE__GPMI_ALE \| MUX_CONFIG_GPMI,
	115	MX28_PAD_GPMI_CLE__GPMI_CLE \| MUX_CONFIG_GPMI,
	116	MX28_PAD_GPMI_RESETN__GPMI_RESETN \| MUX_CONFIG_GPMI,
	117
	118	/* FEC Ethernet */
	119	MX28_PAD_ENET0_MDC__ENET0_MDC \| MUX_CONFIG_ENET,
	120	MX28_PAD_ENET0_MDIO__ENET0_MDIO \| MUX_CONFIG_ENET,
	121	MX28_PAD_ENET0_RX_EN__ENET0_RX_EN \| MUX_CONFIG_ENET,
	122	MX28_PAD_ENET0_TX_EN__ENET0_TX_EN \| MUX_CONFIG_ENET,
	123	MX28_PAD_ENET0_RXD0__ENET0_RXD0 \| MUX_CONFIG_ENET,
	124	MX28_PAD_ENET0_RXD1__ENET0_RXD1 \| MUX_CONFIG_ENET,
	125	MX28_PAD_ENET0_TXD0__ENET0_TXD0 \| MUX_CONFIG_ENET,
	126	MX28_PAD_ENET0_TXD1__ENET0_TXD1 \| MUX_CONFIG_ENET,
	127	MX28_PAD_ENET_CLK__CLKCTRL_ENET \| MUX_CONFIG_ENET,
	128
	129	MX28_PAD_ENET0_COL__ENET1_TX_EN \| MUX_CONFIG_ENET,
	130	MX28_PAD_ENET0_CRS__ENET1_RX_EN \| MUX_CONFIG_ENET,
	131	MX28_PAD_ENET0_RXD2__ENET1_RXD0 \| MUX_CONFIG_ENET,
	132	MX28_PAD_ENET0_RXD3__ENET1_RXD1 \| MUX_CONFIG_ENET,
	133	MX28_PAD_ENET0_TXD2__ENET1_TXD0 \| MUX_CONFIG_ENET,
	134	MX28_PAD_ENET0_TXD3__ENET1_TXD1 \| MUX_CONFIG_ENET,
b7154ec2 MV	135	#if !defined(CONFIG_DENX_M28_V11) && !defined(CONFIG_DENX_M28_V10)
	136	MX28_PAD_AUART2_RTS__GPIO_3_11, /* PHY reset */
	137	#endif
04fe4273 MV	138
	139	/* I2C */
	140	MX28_PAD_I2C0_SCL__I2C0_SCL,
	141	MX28_PAD_I2C0_SDA__I2C0_SDA,
	142
	143	/* EMI */
	144	MX28_PAD_EMI_D00__EMI_DATA0 \| MUX_CONFIG_EMI,
	145	MX28_PAD_EMI_D01__EMI_DATA1 \| MUX_CONFIG_EMI,
	146	MX28_PAD_EMI_D02__EMI_DATA2 \| MUX_CONFIG_EMI,
	147	MX28_PAD_EMI_D03__EMI_DATA3 \| MUX_CONFIG_EMI,
	148	MX28_PAD_EMI_D04__EMI_DATA4 \| MUX_CONFIG_EMI,
	149	MX28_PAD_EMI_D05__EMI_DATA5 \| MUX_CONFIG_EMI,
	150	MX28_PAD_EMI_D06__EMI_DATA6 \| MUX_CONFIG_EMI,
	151	MX28_PAD_EMI_D07__EMI_DATA7 \| MUX_CONFIG_EMI,
	152	MX28_PAD_EMI_D08__EMI_DATA8 \| MUX_CONFIG_EMI,
	153	MX28_PAD_EMI_D09__EMI_DATA9 \| MUX_CONFIG_EMI,
	154	MX28_PAD_EMI_D10__EMI_DATA10 \| MUX_CONFIG_EMI,
	155	MX28_PAD_EMI_D11__EMI_DATA11 \| MUX_CONFIG_EMI,
	156	MX28_PAD_EMI_D12__EMI_DATA12 \| MUX_CONFIG_EMI,
	157	MX28_PAD_EMI_D13__EMI_DATA13 \| MUX_CONFIG_EMI,
	158	MX28_PAD_EMI_D14__EMI_DATA14 \| MUX_CONFIG_EMI,
	159	MX28_PAD_EMI_D15__EMI_DATA15 \| MUX_CONFIG_EMI,
	160	MX28_PAD_EMI_ODT0__EMI_ODT0 \| MUX_CONFIG_EMI,
	161	MX28_PAD_EMI_DQM0__EMI_DQM0 \| MUX_CONFIG_EMI,
	162	MX28_PAD_EMI_ODT1__EMI_ODT1 \| MUX_CONFIG_EMI,
	163	MX28_PAD_EMI_DQM1__EMI_DQM1 \| MUX_CONFIG_EMI,
	164	MX28_PAD_EMI_DDR_OPEN_FB__EMI_DDR_OPEN_FEEDBACK \| MUX_CONFIG_EMI,
	165	MX28_PAD_EMI_CLK__EMI_CLK \| MUX_CONFIG_EMI,
	166	MX28_PAD_EMI_DQS0__EMI_DQS0 \| MUX_CONFIG_EMI,
	167	MX28_PAD_EMI_DQS1__EMI_DQS1 \| MUX_CONFIG_EMI,
	168	MX28_PAD_EMI_DDR_OPEN__EMI_DDR_OPEN \| MUX_CONFIG_EMI,
	169
	170	MX28_PAD_EMI_A00__EMI_ADDR0 \| MUX_CONFIG_EMI,
	171	MX28_PAD_EMI_A01__EMI_ADDR1 \| MUX_CONFIG_EMI,
	172	MX28_PAD_EMI_A02__EMI_ADDR2 \| MUX_CONFIG_EMI,
	173	MX28_PAD_EMI_A03__EMI_ADDR3 \| MUX_CONFIG_EMI,
	174	MX28_PAD_EMI_A04__EMI_ADDR4 \| MUX_CONFIG_EMI,
	175	MX28_PAD_EMI_A05__EMI_ADDR5 \| MUX_CONFIG_EMI,
	176	MX28_PAD_EMI_A06__EMI_ADDR6 \| MUX_CONFIG_EMI,
	177	MX28_PAD_EMI_A07__EMI_ADDR7 \| MUX_CONFIG_EMI,
	178	MX28_PAD_EMI_A08__EMI_ADDR8 \| MUX_CONFIG_EMI,
	179	MX28_PAD_EMI_A09__EMI_ADDR9 \| MUX_CONFIG_EMI,
	180	MX28_PAD_EMI_A10__EMI_ADDR10 \| MUX_CONFIG_EMI,
	181	MX28_PAD_EMI_A11__EMI_ADDR11 \| MUX_CONFIG_EMI,
	182	MX28_PAD_EMI_A12__EMI_ADDR12 \| MUX_CONFIG_EMI,
	183	MX28_PAD_EMI_A13__EMI_ADDR13 \| MUX_CONFIG_EMI,
	184	MX28_PAD_EMI_A14__EMI_ADDR14 \| MUX_CONFIG_EMI,
	185	MX28_PAD_EMI_BA0__EMI_BA0 \| MUX_CONFIG_EMI,
	186	MX28_PAD_EMI_BA1__EMI_BA1 \| MUX_CONFIG_EMI,
	187	MX28_PAD_EMI_BA2__EMI_BA2 \| MUX_CONFIG_EMI,
	188	MX28_PAD_EMI_CASN__EMI_CASN \| MUX_CONFIG_EMI,
	189	MX28_PAD_EMI_RASN__EMI_RASN \| MUX_CONFIG_EMI,
	190	MX28_PAD_EMI_WEN__EMI_WEN \| MUX_CONFIG_EMI,
	191	MX28_PAD_EMI_CE0N__EMI_CE0N \| MUX_CONFIG_EMI,
	192	MX28_PAD_EMI_CE1N__EMI_CE1N \| MUX_CONFIG_EMI,
	193	MX28_PAD_EMI_CKE__EMI_CKE \| MUX_CONFIG_EMI,
	194
	195	/* SPI2 (for flash) */
	196	MX28_PAD_SSP2_SCK__SSP2_SCK \| MUX_CONFIG_SSP2,
	197	MX28_PAD_SSP2_MOSI__SSP2_CMD \| MUX_CONFIG_SSP2,
	198	MX28_PAD_SSP2_MISO__SSP2_D0 \| MUX_CONFIG_SSP2,
	199	MX28_PAD_SSP2_SS0__SSP2_D3 \|
	200	(MXS_PAD_3V3 \| MXS_PAD_8MA \| MXS_PAD_PULLUP),
	201	};
202
7b8657e2	203	void board_init_ll(const uint32_t arg, const uint32_t *resptr)
04fe4273	204	{
7b8657e2	205	mxs_common_spl_init(arg, resptr, iomux_setup, ARRAY_SIZE(iomux_setup));
04fe4273	206	}