]>
Commit | Line | Data |
---|---|---|
757bff49 JC |
1 | /* |
2 | * (C) Copyright 2012 SAMSUNG Electronics | |
3 | * Jaehoon Chung <[email protected]> | |
4 | * | |
5 | * This program is free software; you can redistribute it and/or | |
6 | * modify it under the terms of the GNU General Public License as | |
7 | * published by the Free Software Foundation; either version 2 of | |
8 | * the License, or (at your option) any later version. | |
9 | * | |
10 | * This program is distributed in the hope that it will be useful, | |
11 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
12 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
13 | * GNU General Public License for more details. | |
14 | * | |
15 | * You should have received a copy of the GNU General Public License | |
16 | * along with this program; if not, write to the Free Software | |
17 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA | |
18 | * | |
19 | */ | |
20 | ||
21 | #ifndef __DWMMC_HW_H | |
22 | #define __DWMMC_HW_H | |
23 | ||
24 | #include <asm/io.h> | |
25 | #include <mmc.h> | |
26 | ||
27 | #define DWMCI_CTRL 0x000 | |
28 | #define DWMCI_PWREN 0x004 | |
29 | #define DWMCI_CLKDIV 0x008 | |
30 | #define DWMCI_CLKSRC 0x00C | |
31 | #define DWMCI_CLKENA 0x010 | |
32 | #define DWMCI_TMOUT 0x014 | |
33 | #define DWMCI_CTYPE 0x018 | |
34 | #define DWMCI_BLKSIZ 0x01C | |
35 | #define DWMCI_BYTCNT 0x020 | |
36 | #define DWMCI_INTMASK 0x024 | |
37 | #define DWMCI_CMDARG 0x028 | |
38 | #define DWMCI_CMD 0x02C | |
39 | #define DWMCI_RESP0 0x030 | |
40 | #define DWMCI_RESP1 0x034 | |
41 | #define DWMCI_RESP2 0x038 | |
42 | #define DWMCI_RESP3 0x03C | |
43 | #define DWMCI_MINTSTS 0x040 | |
44 | #define DWMCI_RINTSTS 0x044 | |
45 | #define DWMCI_STATUS 0x048 | |
46 | #define DWMCI_FIFOTH 0x04C | |
47 | #define DWMCI_CDETECT 0x050 | |
48 | #define DWMCI_WRTPRT 0x054 | |
49 | #define DWMCI_GPIO 0x058 | |
50 | #define DWMCI_TCMCNT 0x05C | |
51 | #define DWMCI_TBBCNT 0x060 | |
52 | #define DWMCI_DEBNCE 0x064 | |
53 | #define DWMCI_USRID 0x068 | |
54 | #define DWMCI_VERID 0x06C | |
55 | #define DWMCI_HCON 0x070 | |
56 | #define DWMCI_UHS_REG 0x074 | |
57 | #define DWMCI_BMOD 0x080 | |
58 | #define DWMCI_PLDMND 0x084 | |
59 | #define DWMCI_DBADDR 0x088 | |
60 | #define DWMCI_IDSTS 0x08C | |
61 | #define DWMCI_IDINTEN 0x090 | |
62 | #define DWMCI_DSCADDR 0x094 | |
63 | #define DWMCI_BUFADDR 0x098 | |
64 | #define DWMCI_DATA 0x200 | |
65 | ||
66 | /* Interrupt Mask register */ | |
67 | #define DWMCI_INTMSK_ALL 0xffffffff | |
68 | #define DWMCI_INTMSK_RE (1 << 1) | |
69 | #define DWMCI_INTMSK_CDONE (1 << 2) | |
70 | #define DWMCI_INTMSK_DTO (1 << 3) | |
71 | #define DWMCI_INTMSK_TXDR (1 << 4) | |
72 | #define DWMCI_INTMSK_RXDR (1 << 5) | |
73 | #define DWMCI_INTMSK_DCRC (1 << 7) | |
74 | #define DWMCI_INTMSK_RTO (1 << 8) | |
75 | #define DWMCI_INTMSK_DRTO (1 << 9) | |
76 | #define DWMCI_INTMSK_HTO (1 << 10) | |
77 | #define DWMCI_INTMSK_FRUN (1 << 11) | |
78 | #define DWMCI_INTMSK_HLE (1 << 12) | |
79 | #define DWMCI_INTMSK_SBE (1 << 13) | |
80 | #define DWMCI_INTMSK_ACD (1 << 14) | |
81 | #define DWMCI_INTMSK_EBE (1 << 15) | |
82 | ||
83 | /* Raw interrupt Regsiter */ | |
84 | #define DWMCI_DATA_ERR (DWMCI_INTMSK_EBE | DWMCI_INTMSK_SBE | DWMCI_INTMSK_HLE |\ | |
85 | DWMCI_INTMSK_FRUN | DWMCI_INTMSK_EBE | DWMCI_INTMSK_DCRC) | |
86 | #define DWMCI_DATA_TOUT (DWMCI_INTMSK_HTO | DWMCI_INTMSK_DRTO) | |
87 | /* CTRL register */ | |
88 | #define DWMCI_CTRL_RESET (1 << 0) | |
89 | #define DWMCI_CTRL_FIFO_RESET (1 << 1) | |
90 | #define DWMCI_CTRL_DMA_RESET (1 << 2) | |
91 | #define DWMCI_DMA_EN (1 << 5) | |
92 | #define DWMCI_CTRL_SEND_AS_CCSD (1 << 10) | |
93 | #define DWMCI_IDMAC_EN (1 << 25) | |
94 | #define DWMCI_RESET_ALL (DWMCI_CTRL_RESET | DWMCI_CTRL_FIFO_RESET |\ | |
95 | DWMCI_CTRL_DMA_RESET) | |
96 | ||
97 | /* CMD register */ | |
98 | #define DWMCI_CMD_RESP_EXP (1 << 6) | |
99 | #define DWMCI_CMD_RESP_LENGTH (1 << 7) | |
100 | #define DWMCI_CMD_CHECK_CRC (1 << 8) | |
101 | #define DWMCI_CMD_DATA_EXP (1 << 9) | |
102 | #define DWMCI_CMD_RW (1 << 10) | |
103 | #define DWMCI_CMD_SEND_STOP (1 << 12) | |
104 | #define DWMCI_CMD_ABORT_STOP (1 << 14) | |
105 | #define DWMCI_CMD_PRV_DAT_WAIT (1 << 13) | |
106 | #define DWMCI_CMD_UPD_CLK (1 << 21) | |
107 | #define DWMCI_CMD_USE_HOLD_REG (1 << 29) | |
108 | #define DWMCI_CMD_START (1 << 31) | |
109 | ||
110 | /* CLKENA register */ | |
111 | #define DWMCI_CLKEN_ENABLE (1 << 0) | |
112 | #define DWMCI_CLKEN_LOW_PWR (1 << 16) | |
113 | ||
114 | /* Card-type registe */ | |
115 | #define DWMCI_CTYPE_1BIT 0 | |
116 | #define DWMCI_CTYPE_4BIT (1 << 0) | |
117 | #define DWMCI_CTYPE_8BIT (1 << 16) | |
118 | ||
119 | /* Status Register */ | |
120 | #define DWMCI_BUSY (1 << 9) | |
121 | ||
122 | /* FIFOTH Register */ | |
123 | #define MSIZE(x) ((x) << 28) | |
124 | #define RX_WMARK(x) ((x) << 16) | |
125 | #define TX_WMARK(x) (x) | |
126 | ||
127 | #define DWMCI_IDMAC_OWN (1 << 31) | |
128 | #define DWMCI_IDMAC_CH (1 << 4) | |
129 | #define DWMCI_IDMAC_FS (1 << 3) | |
130 | #define DWMCI_IDMAC_LD (1 << 2) | |
131 | ||
132 | /* Bus Mode Register */ | |
133 | #define DWMCI_BMOD_IDMAC_RESET (1 << 0) | |
134 | #define DWMCI_BMOD_IDMAC_FB (1 << 1) | |
135 | #define DWMCI_BMOD_IDMAC_EN (1 << 7) | |
136 | ||
137 | struct dwmci_host { | |
138 | char *name; | |
139 | void *ioaddr; | |
140 | unsigned int quirks; | |
141 | unsigned int caps; | |
142 | unsigned int version; | |
143 | unsigned int clock; | |
144 | unsigned int bus_hz; | |
145 | int dev_index; | |
146 | int buswidth; | |
147 | u32 fifoth_val; | |
148 | struct mmc *mmc; | |
149 | ||
150 | void (*clksel)(struct dwmci_host *host); | |
151 | unsigned int (*mmc_clk)(int dev_index); | |
152 | }; | |
153 | ||
154 | struct dwmci_idmac { | |
155 | u32 flags; | |
156 | u32 cnt; | |
157 | u32 addr; | |
158 | u32 next_addr; | |
159 | }; | |
160 | ||
161 | static inline void dwmci_writel(struct dwmci_host *host, int reg, u32 val) | |
162 | { | |
163 | writel(val, host->ioaddr + reg); | |
164 | } | |
165 | ||
166 | static inline void dwmci_writew(struct dwmci_host *host, int reg, u16 val) | |
167 | { | |
168 | writew(val, host->ioaddr + reg); | |
169 | } | |
170 | ||
171 | static inline void dwmci_writeb(struct dwmci_host *host, int reg, u8 val) | |
172 | { | |
173 | writeb(val, host->ioaddr + reg); | |
174 | } | |
175 | static inline u32 dwmci_readl(struct dwmci_host *host, int reg) | |
176 | { | |
177 | return readl(host->ioaddr + reg); | |
178 | } | |
179 | ||
180 | static inline u16 dwmci_readw(struct dwmci_host *host, int reg) | |
181 | { | |
182 | return readw(host->ioaddr + reg); | |
183 | } | |
184 | ||
185 | static inline u8 dwmci_readb(struct dwmci_host *host, int reg) | |
186 | { | |
187 | return readb(host->ioaddr + reg); | |
188 | } | |
189 | ||
190 | int add_dwmci(struct dwmci_host *host, u32 max_clk, u32 min_clk); | |
191 | #endif /* __DWMMC_HW_H */ |