[J-u-boot.git] / include / configs / bct-brettl2.h

/*
 * U-Boot - Configuration file for BF536 brettl2 board
 */

#ifndef __CONFIG_BCT_BRETTL2_H__
#define __CONFIG_BCT_BRETTL2_H__

#include <asm/config-pre.h>


/*
 * Processor Settings
 */
#define CONFIG_BFIN_CPU             bf536-0.3
#define CONFIG_BFIN_BOOT_MODE       BFIN_BOOT_BYPASS


/*
 * Clock Settings
 *	CCLK = (CLKIN * VCO_MULT) / CCLK_DIV
 *	SCLK = (CLKIN * VCO_MULT) / SCLK_DIV
 */
/* CONFIG_CLKIN_HZ is any value in Hz					*/
#define CONFIG_CLKIN_HZ			16384000
/* CLKIN_HALF controls the DF bit in PLL_CTL	  0 = CLKIN		*/
/*						  1 = CLKIN / 2		*/
#define CONFIG_CLKIN_HALF		0
/* PLL_BYPASS controls the BYPASS bit in PLL_CTL  0 = do not bypass	*/
/*						  1 = bypass PLL	*/
#define CONFIG_PLL_BYPASS		0
/* VCO_MULT controls the MSEL (multiplier) bits in PLL_CTL		*/
/* Values can range from 0-63 (where 0 means 64)			*/
#define CONFIG_VCO_MULT			24
/* CCLK_DIV controls the core clock divider				*/
/* Values can be 1, 2, 4, or 8 ONLY					*/
#define CONFIG_CCLK_DIV			1
/* SCLK_DIV controls the system clock divider				*/
/* Values can range from 1-15						*/
#define CONFIG_SCLK_DIV			3
#define CONFIG_VR_CTL_VAL	(VLEV_110 | GAIN_20 | FREQ_1000)


/*
 * Memory Settings
 */
#define CONFIG_MEM_ADD_WDTH	9
#define CONFIG_MEM_SIZE		32


/*
 * SDRAM Settings
 */
#define CONFIG_EBIU_SDRRC_VAL	0x07f6
#define CONFIG_EBIU_SDGCTL_VAL	0x9111cd

#define CONFIG_EBIU_AMGCTL_VAL	(AMBEN_ALL)
#define CONFIG_EBIU_AMBCTL0_VAL	(B1WAT_7 | B1RAT_11 | B1HT_2 | B1ST_3 | B0WAT_7 | B0RAT_11 | B0HT_2 | B0ST_3)
#define CONFIG_EBIU_AMBCTL1_VAL	(B3WAT_7 | B3RAT_11 | B3HT_2 | B3ST_3 | B2WAT_7 | B2RAT_11 | B2HT_2 | B2ST_3)

#define CONFIG_SYS_MONITOR_LEN		(256 * 1024)
#define CONFIG_SYS_MALLOC_LEN		(128 * 1024)


/*
 * Network Settings
 */
#ifndef __ADSPBF534__
#define ADI_CMDS_NETWORK	1
#define CONFIG_BFIN_MAC		1
#define CONFIG_NETCONSOLE	1
#define CONFIG_HOSTNAME		brettl2
#define CONFIG_IPADDR		192.168.233.224
#define CONFIG_GATEWAYIP	192.168.233.1
#define CONFIG_SERVERIP		192.168.233.53
#define CONFIG_ROOTPATH		"/romfs/brettl2"
#endif


/*
 * Flash Settings
 */
#define CONFIG_FLASH_CFI_DRIVER
#define CONFIG_SYS_FLASH_CFI
#define CONFIG_CFI_FLASH_USE_WEAK_ACCESSORS
#define CONFIG_SYS_FLASH_PROTECTION
#define CONFIG_SYS_FLASH_BASE			0x20000000
#define CONFIG_SYS_MAX_FLASH_BANKS		1
#define CONFIG_SYS_MAX_FLASH_SECT		135


/*
 * Env Storage Settings
 */
#define CONFIG_ENV_IS_IN_FLASH 1
#define CONFIG_ENV_OFFSET	0x4000
#define CONFIG_ENV_SIZE		0x2000
#define CONFIG_ENV_SECT_SIZE	0x12000

#if (CONFIG_BFIN_BOOT_MODE == BFIN_BOOT_BYPASS)
#define ENV_IS_EMBEDDED
#else
#define CONFIG_ENV_IS_EMBEDDED_IN_LDR
#endif

#ifdef ENV_IS_EMBEDDED
/* WARNING - the following is hand-optimized to fit within
 * the sector before the environment sector. If it throws
 * an error during compilation remove an object here to get
 * it linked after the configuration sector.
 */
# define LDS_BOARD_TEXT \
	arch/blackfin/lib/built-in.o (.text*); \
	arch/blackfin/cpu/built-in.o (.text*); \
	. = DEFINED(env_offset) ? env_offset : .; \
	common/env_embedded.o (.text*);
#endif


/*
 * I2C Settings
 */
#define CONFIG_SYS_I2C
#define CONFIG_SYS_I2C_ADI


/*
 * Misc Settings
 */
#define CONFIG_BOOTDELAY	1
#define CONFIG_LOADADDR		0x800000
#define CONFIG_MISC_INIT_R
#define CONFIG_UART_CONSOLE	0
#define CONFIG_BAUDRATE		115200
#define CONFIG_MTD_DEVICE
#define CONFIG_MTD_PARTITIONS
#define CONFIG_SYS_HUSH_PARSER

/*
 * Pull in common ADI header for remaining command/environment setup
 */
#include <configs/bfin_adi_common.h>

/* disable unnecessary features */
#undef CONFIG_BOOTM_RTEMS
#undef CONFIG_BZIP2
#undef CONFIG_KALLSYMS

#endif
Commit	Line	Data
06399329	1	/*
a187559e	2	* U-Boot - Configuration file for BF536 brettl2 board
06399329 PM	3	*/
	4
	5	#ifndef __CONFIG_BCT_BRETTL2_H__
	6	#define __CONFIG_BCT_BRETTL2_H__
	7
	8	#include <asm/config-pre.h>
	9
	10
	11	/*
	12	* Processor Settings
	13	*/
fbcf8e8c MF	14	#define CONFIG_BFIN_CPU bf536-0.3
fbcf8e8c MF	15	#define CONFIG_BFIN_BOOT_MODE BFIN_BOOT_BYPASS
06399329 PM	16
	17
	18	/*
	19	* Clock Settings
	20	* CCLK = (CLKIN * VCO_MULT) / CCLK_DIV
	21	* SCLK = (CLKIN * VCO_MULT) / SCLK_DIV
	22	*/
	23	/* CONFIG_CLKIN_HZ is any value in Hz */
	24	#define CONFIG_CLKIN_HZ 16384000
071bc923 WD	25	/* CLKIN_HALF controls the DF bit in PLL_CTL 0 = CLKIN */
071bc923 WD	26	/* 1 = CLKIN / 2 */
06399329 PM	27	#define CONFIG_CLKIN_HALF 0
06399329 PM	28	/* PLL_BYPASS controls the BYPASS bit in PLL_CTL 0 = do not bypass */
071bc923	29	/* 1 = bypass PLL */
06399329 PM	30	#define CONFIG_PLL_BYPASS 0
	31	/* VCO_MULT controls the MSEL (multiplier) bits in PLL_CTL */
	32	/* Values can range from 0-63 (where 0 means 64) */
	33	#define CONFIG_VCO_MULT 24
	34	/* CCLK_DIV controls the core clock divider */
	35	/* Values can be 1, 2, 4, or 8 ONLY */
	36	#define CONFIG_CCLK_DIV 1
	37	/* SCLK_DIV controls the system clock divider */
	38	/* Values can range from 1-15 */
	39	#define CONFIG_SCLK_DIV 3
071bc923	40	#define CONFIG_VR_CTL_VAL (VLEV_110 \| GAIN_20 \| FREQ_1000)
06399329 PM	41
	42
	43	/*
	44	* Memory Settings
	45	*/
	46	#define CONFIG_MEM_ADD_WDTH 9
	47	#define CONFIG_MEM_SIZE 32
	48
	49
	50	/*
	51	* SDRAM Settings
	52	*/
	53	#define CONFIG_EBIU_SDRRC_VAL 0x07f6
	54	#define CONFIG_EBIU_SDGCTL_VAL 0x9111cd
	55
	56	#define CONFIG_EBIU_AMGCTL_VAL (AMBEN_ALL)
	57	#define CONFIG_EBIU_AMBCTL0_VAL (B1WAT_7 \| B1RAT_11 \| B1HT_2 \| B1ST_3 \| B0WAT_7 \| B0RAT_11 \| B0HT_2 \| B0ST_3)
	58	#define CONFIG_EBIU_AMBCTL1_VAL (B3WAT_7 \| B3RAT_11 \| B3HT_2 \| B3ST_3 \| B2WAT_7 \| B2RAT_11 \| B2HT_2 \| B2ST_3)
	59
	60	#define CONFIG_SYS_MONITOR_LEN (256 * 1024)
	61	#define CONFIG_SYS_MALLOC_LEN (128 * 1024)
	62
	63
	64	/*
	65	* Network Settings
	66	*/
	67	#ifndef __ADSPBF534__
	68	#define ADI_CMDS_NETWORK 1
	69	#define CONFIG_BFIN_MAC 1
	70	#define CONFIG_NETCONSOLE 1
06399329 PM	71	#define CONFIG_HOSTNAME brettl2
	72	#define CONFIG_IPADDR 192.168.233.224
	73	#define CONFIG_GATEWAYIP 192.168.233.1
	74	#define CONFIG_SERVERIP 192.168.233.53
8b3637c6	75	#define CONFIG_ROOTPATH "/romfs/brettl2"
06399329 PM	76	#endif
	77
	78
	79	/*
	80	* Flash Settings
	81	*/
	82	#define CONFIG_FLASH_CFI_DRIVER
	83	#define CONFIG_SYS_FLASH_CFI
	84	#define CONFIG_CFI_FLASH_USE_WEAK_ACCESSORS
	85	#define CONFIG_SYS_FLASH_PROTECTION
	86	#define CONFIG_SYS_FLASH_BASE 0x20000000
	87	#define CONFIG_SYS_MAX_FLASH_BANKS 1
	88	#define CONFIG_SYS_MAX_FLASH_SECT 135
	89
	90
	91	/*
	92	* Env Storage Settings
	93	*/
	94	#define CONFIG_ENV_IS_IN_FLASH 1
	95	#define CONFIG_ENV_OFFSET 0x4000
	96	#define CONFIG_ENV_SIZE 0x2000
0d3fd562	97	#define CONFIG_ENV_SECT_SIZE 0x12000
06399329 PM	98
	99	#if (CONFIG_BFIN_BOOT_MODE == BFIN_BOOT_BYPASS)
	100	#define ENV_IS_EMBEDDED
	101	#else
	102	#define CONFIG_ENV_IS_EMBEDDED_IN_LDR
	103	#endif
	104
	105	#ifdef ENV_IS_EMBEDDED
	106	/* WARNING - the following is hand-optimized to fit within
	107	* the sector before the environment sector. If it throws
	108	* an error during compilation remove an object here to get
	109	* it linked after the configuration sector.
	110	*/
	111	# define LDS_BOARD_TEXT \
e2906a59 MY	112	arch/blackfin/lib/built-in.o (.text*); \
e2906a59 MY	113	arch/blackfin/cpu/built-in.o (.text*); \
071bc923	114	. = DEFINED(env_offset) ? env_offset : .; \
c70e7ddb	115	common/env_embedded.o (.text*);
06399329 PM	116	#endif
	117
	118
	119	/*
	120	* I2C Settings
	121	*/
c469703b	122	#define CONFIG_SYS_I2C
fea9b69a	123	#define CONFIG_SYS_I2C_ADI
06399329 PM	124
	125
	126	/*
	127	* Misc Settings
	128	*/
	129	#define CONFIG_BOOTDELAY 1
	130	#define CONFIG_LOADADDR 0x800000
	131	#define CONFIG_MISC_INIT_R
	132	#define CONFIG_UART_CONSOLE 0
	133	#define CONFIG_BAUDRATE 115200
	134	#define CONFIG_MTD_DEVICE
	135	#define CONFIG_MTD_PARTITIONS
	136	#define CONFIG_SYS_HUSH_PARSER
06399329 PM	137
	138	/*
	139	* Pull in common ADI header for remaining command/environment setup
	140	*/
	141	#include <configs/bfin_adi_common.h>
	142
	143	/* disable unnecessary features */
	144	#undef CONFIG_BOOTM_RTEMS
	145	#undef CONFIG_BZIP2
	146	#undef CONFIG_KALLSYMS
	147
	148	#endif