[J-u-boot.git] / include / configs / grpeach.h

/* SPDX-License-Identifier: GPL-2.0+ */
/*
 * Configuration settings for the Renesas GRPEACH board
 *
 * Copyright (C) 2017-2019 Renesas Electronics
 */

#ifndef __GRPEACH_H
#define __GRPEACH_H

/* Board Clock , P1 clock frequency (XTAL=13.33MHz) */
#define CONFIG_SYS_CLK_FREQ	66666666

/* Serial Console */
#define CONFIG_BAUDRATE		115200

/* Miscellaneous */
#define CONFIG_SYS_PBSIZE	256
#define CONFIG_SYS_ARM_CACHE_WRITETHROUGH
#define CONFIG_CMDLINE_TAG

/* Internal RAM Size (RZ/A1=3M, RZ/A1M=5M, RZ/A1H=10M) */
#define CONFIG_SYS_SDRAM_BASE		0x20000000
#define CONFIG_SYS_SDRAM_SIZE		(10 * 1024 * 1024)
#define CONFIG_SYS_INIT_SP_ADDR		\
	(CONFIG_SYS_SDRAM_BASE + CONFIG_SYS_SDRAM_SIZE - 1024 * 1024)
#define CONFIG_SYS_LOAD_ADDR		\
	(CONFIG_SYS_SDRAM_BASE + 4 * 1024 * 1024)

#define CONFIG_ENV_OVERWRITE		1

/* Malloc */
#define CONFIG_SYS_MALLOC_LEN		(1024 * 1024)
#define CONFIG_SYS_MONITOR_LEN		(512 * 1024)

/* Kernel Boot */
#define CONFIG_BOOTARGS			"ignore_loglevel"

/* Network interface */
#define CONFIG_SH_ETHER_USE_PORT	0
#define CONFIG_SH_ETHER_PHY_ADDR	0
#define CONFIG_SH_ETHER_PHY_MODE PHY_INTERFACE_MODE_MII
#define CONFIG_SH_ETHER_CACHE_WRITEBACK
#define CONFIG_SH_ETHER_CACHE_INVALIDATE
#define CONFIG_SH_ETHER_ALIGNE_SIZE	64
#define CONFIG_BITBANGMII
#define CONFIG_BITBANGMII_MULTI

#endif	/* __GRPEACH_H */
Commit	Line	Data
ba932bc8 CB	1	/* SPDX-License-Identifier: GPL-2.0+ */
	2	/*
	3	* Configuration settings for the Renesas GRPEACH board
	4	*
	5	* Copyright (C) 2017-2019 Renesas Electronics
	6	*/
	7
	8	#ifndef __GRPEACH_H
	9	#define __GRPEACH_H
	10
	11	/* Board Clock , P1 clock frequency (XTAL=13.33MHz) */
	12	#define CONFIG_SYS_CLK_FREQ 66666666
	13
	14	/* Serial Console */
	15	#define CONFIG_BAUDRATE 115200
	16
	17	/* Miscellaneous */
	18	#define CONFIG_SYS_PBSIZE 256
	19	#define CONFIG_SYS_ARM_CACHE_WRITETHROUGH
	20	#define CONFIG_CMDLINE_TAG
ba932bc8 CB	21
	22	/* Internal RAM Size (RZ/A1=3M, RZ/A1M=5M, RZ/A1H=10M) */
	23	#define CONFIG_SYS_SDRAM_BASE 0x20000000
	24	#define CONFIG_SYS_SDRAM_SIZE (10 * 1024 * 1024)
	25	#define CONFIG_SYS_INIT_SP_ADDR \
	26	(CONFIG_SYS_SDRAM_BASE + CONFIG_SYS_SDRAM_SIZE - 1024 * 1024)
	27	#define CONFIG_SYS_LOAD_ADDR \
	28	(CONFIG_SYS_SDRAM_BASE + 4 * 1024 * 1024)
	29
	30	#define CONFIG_ENV_OVERWRITE 1
ba932bc8 CB	31
	32	/* Malloc */
	33	#define CONFIG_SYS_MALLOC_LEN (1024 * 1024)
	34	#define CONFIG_SYS_MONITOR_LEN (512 * 1024)
	35
	36	/* Kernel Boot */
	37	#define CONFIG_BOOTARGS "ignore_loglevel"
	38
	39	/* Network interface */
	40	#define CONFIG_SH_ETHER_USE_PORT 0
	41	#define CONFIG_SH_ETHER_PHY_ADDR 0
	42	#define CONFIG_SH_ETHER_PHY_MODE PHY_INTERFACE_MODE_MII
	43	#define CONFIG_SH_ETHER_CACHE_WRITEBACK
	44	#define CONFIG_SH_ETHER_CACHE_INVALIDATE
	45	#define CONFIG_SH_ETHER_ALIGNE_SIZE 64
	46	#define CONFIG_BITBANGMII
	47	#define CONFIG_BITBANGMII_MULTI
	48
	49	#endif /* __GRPEACH_H */