[J-u-boot.git] / drivers / serial / serial_stm32.c

// SPDX-License-Identifier: GPL-2.0+
/*
 * Copyright (C) 2016, STMicroelectronics - All Rights Reserved
 * Author(s): Vikas Manocha, <[email protected]> for STMicroelectronics.
 */

#define LOG_CATEGORY UCLASS_SERIAL

#include <clk.h>
#include <dm.h>
#include <log.h>
#include <reset.h>
#include <serial.h>
#include <watchdog.h>
#include <asm/io.h>
#include <asm/arch/stm32.h>
#include <dm/device_compat.h>
#include <linux/bitops.h>
#include <linux/delay.h>
#include <linux/iopoll.h>
#include "serial_stm32.h"
#include <dm/device_compat.h>

/*
 * At 115200 bits/s
 * 1 bit = 1 / 115200 = 8,68 us
 * 8 bits = 69,444 us
 * 10 bits are needed for worst case (8 bits + 1 start + 1 stop) = 86.806 us
 */
#define ONE_BYTE_B115200_US		87

static void _stm32_serial_setbrg(void __iomem *base,
				 struct stm32_uart_info *uart_info,
				 u32 clock_rate,
				 int baudrate)
{
	bool stm32f4 = uart_info->stm32f4;
	u32 int_div, mantissa, fraction, oversampling;
	u8 uart_enable_bit = uart_info->uart_enable_bit;

	/* BRR register must be set when uart is disabled */
	clrbits_le32(base + CR1_OFFSET(stm32f4), BIT(uart_enable_bit));

	int_div = DIV_ROUND_CLOSEST(clock_rate, baudrate);

	if (int_div < 16) {
		oversampling = 8;
		setbits_le32(base + CR1_OFFSET(stm32f4), USART_CR1_OVER8);
	} else {
		oversampling = 16;
		clrbits_le32(base + CR1_OFFSET(stm32f4), USART_CR1_OVER8);
	}

	mantissa = (int_div / oversampling) << USART_BRR_M_SHIFT;
	fraction = int_div % oversampling;

	writel(mantissa | fraction, base + BRR_OFFSET(stm32f4));

	setbits_le32(base + CR1_OFFSET(stm32f4), BIT(uart_enable_bit));
}

static int stm32_serial_setbrg(struct udevice *dev, int baudrate)
{
	struct stm32x7_serial_plat *plat = dev_get_plat(dev);

	_stm32_serial_setbrg(plat->base, plat->uart_info,
			     plat->clock_rate, baudrate);

	return 0;
}

static int stm32_serial_setconfig(struct udevice *dev, uint serial_config)
{
	struct stm32x7_serial_plat *plat = dev_get_plat(dev);
	bool stm32f4 = plat->uart_info->stm32f4;
	u8 uart_enable_bit = plat->uart_info->uart_enable_bit;
	void __iomem *cr1 = plat->base + CR1_OFFSET(stm32f4);
	u32 config = 0;
	uint parity = SERIAL_GET_PARITY(serial_config);
	uint bits = SERIAL_GET_BITS(serial_config);
	uint stop = SERIAL_GET_STOP(serial_config);

	/*
	 * only parity config is implemented, check if other serial settings
	 * are the default one.
	 * (STM32F4 serial IP didn't support parity setting)
	 */
	if (bits != SERIAL_8_BITS || stop != SERIAL_ONE_STOP || stm32f4)
		return -ENOTSUPP; /* not supported in driver*/

	clrbits_le32(cr1, USART_CR1_RE | USART_CR1_TE | BIT(uart_enable_bit));
	/* update usart configuration (uart need to be disable)
	 * PCE: parity check enable
	 * PS : '0' : Even / '1' : Odd
	 * M[1:0] = '00' : 8 Data bits
	 * M[1:0] = '01' : 9 Data bits with parity
	 */
	switch (parity) {
	default:
	case SERIAL_PAR_NONE:
		config = 0;
		break;
	case SERIAL_PAR_ODD:
		config = USART_CR1_PCE | USART_CR1_PS | USART_CR1_M0;
		break;
	case SERIAL_PAR_EVEN:
		config = USART_CR1_PCE | USART_CR1_M0;
		break;
	}

	clrsetbits_le32(cr1,
			USART_CR1_PCE | USART_CR1_PS | USART_CR1_M1 |
			USART_CR1_M0,
			config);
	setbits_le32(cr1, USART_CR1_RE | USART_CR1_TE | BIT(uart_enable_bit));

	return 0;
}

static int stm32_serial_getc(struct udevice *dev)
{
	struct stm32x7_serial_plat *plat = dev_get_plat(dev);
	bool stm32f4 = plat->uart_info->stm32f4;
	void __iomem *base = plat->base;
	u32 isr = readl(base + ISR_OFFSET(stm32f4));

	if ((isr & USART_ISR_RXNE) == 0)
		return -EAGAIN;

	if (isr & (USART_ISR_PE | USART_ISR_ORE | USART_ISR_FE)) {
		if (!stm32f4)
			setbits_le32(base + ICR_OFFSET,
				     USART_ICR_PCECF | USART_ICR_ORECF |
				     USART_ICR_FECF);
		else
			readl(base + RDR_OFFSET(stm32f4));
		return -EIO;
	}

	return readl(base + RDR_OFFSET(stm32f4));
}

static int _stm32_serial_putc(void __iomem *base,
			      struct stm32_uart_info *uart_info,
			      const char c)
{
	bool stm32f4 = uart_info->stm32f4;

	if ((readl(base + ISR_OFFSET(stm32f4)) & USART_ISR_TXE) == 0)
		return -EAGAIN;

	writel(c, base + TDR_OFFSET(stm32f4));

	return 0;
}

static int stm32_serial_putc(struct udevice *dev, const char c)
{
	struct stm32x7_serial_plat *plat = dev_get_plat(dev);

	return _stm32_serial_putc(plat->base, plat->uart_info, c);
}

static int stm32_serial_pending(struct udevice *dev, bool input)
{
	struct stm32x7_serial_plat *plat = dev_get_plat(dev);
	bool stm32f4 = plat->uart_info->stm32f4;
	void __iomem *base = plat->base;

	if (input)
		return readl(base + ISR_OFFSET(stm32f4)) &
			USART_ISR_RXNE ? 1 : 0;
	else
		return readl(base + ISR_OFFSET(stm32f4)) &
			USART_ISR_TXE ? 0 : 1;
}

static void _stm32_serial_init(void __iomem *base,
			       struct stm32_uart_info *uart_info)
{
	bool stm32f4 = uart_info->stm32f4;
	u8 uart_enable_bit = uart_info->uart_enable_bit;

	/* Disable uart-> enable fifo -> enable uart */
	clrbits_le32(base + CR1_OFFSET(stm32f4), USART_CR1_RE | USART_CR1_TE |
		     BIT(uart_enable_bit));
	if (uart_info->has_fifo)
		setbits_le32(base + CR1_OFFSET(stm32f4), USART_CR1_FIFOEN);
	setbits_le32(base + CR1_OFFSET(stm32f4), USART_CR1_RE | USART_CR1_TE |
		     BIT(uart_enable_bit));
}

static int stm32_serial_probe(struct udevice *dev)
{
	struct stm32x7_serial_plat *plat = dev_get_plat(dev);
	struct clk clk;
	struct reset_ctl reset;
	u32 isr;
	int ret;
	bool stm32f4;

	plat->uart_info = (struct stm32_uart_info *)dev_get_driver_data(dev);
	stm32f4 = plat->uart_info->stm32f4;

	ret = clk_get_by_index(dev, 0, &clk);
	if (ret < 0)
		return ret;

	ret = clk_enable(&clk);
	if (ret) {
		dev_err(dev, "failed to enable clock\n");
		return ret;
	}

	/*
	 * before uart initialization, wait for TC bit (Transmission Complete)
	 * in case there is still chars from previous bootstage to transmit
	 */
	ret = read_poll_timeout(readl, isr, isr & USART_ISR_TC, 50,
				16 * ONE_BYTE_B115200_US, plat->base + ISR_OFFSET(stm32f4));
	if (ret)
		dev_dbg(dev, "FIFO not empty, some character can be lost (%d)\n", ret);

	ret = reset_get_by_index(dev, 0, &reset);
	if (!ret) {
		reset_assert(&reset);
		udelay(2);
		reset_deassert(&reset);
	}

	plat->clock_rate = clk_get_rate(&clk);
	if (!plat->clock_rate) {
		clk_disable(&clk);
		return -EINVAL;
	};

	_stm32_serial_init(plat->base, plat->uart_info);

	return 0;
}

static const struct udevice_id stm32_serial_id[] = {
	{ .compatible = "st,stm32-uart", .data = (ulong)&stm32f4_info},
	{ .compatible = "st,stm32f7-uart", .data = (ulong)&stm32f7_info},
	{ .compatible = "st,stm32h7-uart", .data = (ulong)&stm32h7_info},
	{}
};

static int stm32_serial_of_to_plat(struct udevice *dev)
{
	struct stm32x7_serial_plat *plat = dev_get_plat(dev);
	fdt_addr_t addr;

	addr = dev_read_addr(dev);
	if (addr == FDT_ADDR_T_NONE)
		return -EINVAL;

	plat->base = (void __iomem *)addr;

	return 0;
}

static const struct dm_serial_ops stm32_serial_ops = {
	.putc = stm32_serial_putc,
	.pending = stm32_serial_pending,
	.getc = stm32_serial_getc,
	.setbrg = stm32_serial_setbrg,
	.setconfig = stm32_serial_setconfig
};

U_BOOT_DRIVER(serial_stm32) = {
	.name = "serial_stm32",
	.id = UCLASS_SERIAL,
	.of_match = of_match_ptr(stm32_serial_id),
	.of_to_plat = of_match_ptr(stm32_serial_of_to_plat),
	.plat_auto	= sizeof(struct stm32x7_serial_plat),
	.ops = &stm32_serial_ops,
	.probe = stm32_serial_probe,
#if !CONFIG_IS_ENABLED(OF_CONTROL)
	.flags = DM_FLAG_PRE_RELOC,
#endif
};

#ifdef CONFIG_DEBUG_UART_STM32
#include <debug_uart.h>
static inline struct stm32_uart_info *_debug_uart_info(void)
{
	struct stm32_uart_info *uart_info;

#if defined(CONFIG_STM32F4)
	uart_info = &stm32f4_info;
#elif defined(CONFIG_STM32F7)
	uart_info = &stm32f7_info;
#else
	uart_info = &stm32h7_info;
#endif
	return uart_info;
}

static inline void _debug_uart_init(void)
{
	void __iomem *base = (void __iomem *)CONFIG_VAL(DEBUG_UART_BASE);
	struct stm32_uart_info *uart_info = _debug_uart_info();

	_stm32_serial_init(base, uart_info);
	_stm32_serial_setbrg(base, uart_info,
			     CONFIG_DEBUG_UART_CLOCK,
			     CONFIG_BAUDRATE);
}

static inline void _debug_uart_putc(int c)
{
	void __iomem *base = (void __iomem *)CONFIG_VAL(DEBUG_UART_BASE);
	struct stm32_uart_info *uart_info = _debug_uart_info();

	while (_stm32_serial_putc(base, uart_info, c) == -EAGAIN)
		;
}

DEBUG_UART_FUNCS
#endif
Commit	Line	Data
83d290c5	1	// SPDX-License-Identifier: GPL-2.0+
6a12cebd	2	/*
3bc599c9 PC	3	* Copyright (C) 2016, STMicroelectronics - All Rights Reserved
3bc599c9 PC	4	* Author(s): Vikas Manocha, <[email protected]> for STMicroelectronics.
6a12cebd VM	5	*/
6a12cebd VM	6
a3ce8d60 PD	7	#define LOG_CATEGORY UCLASS_SERIAL
a3ce8d60 PD	8
fd03b83a	9	#include <clk.h>
6a12cebd	10	#include <dm.h>
f7ae49fc	11	#include <log.h>
f828fa4d	12	#include <reset.h>
6a12cebd	13	#include <serial.h>
215c8bed PD	14	#include <watchdog.h>
215c8bed PD	15	#include <asm/io.h>
ba0a3c16	16	#include <asm/arch/stm32.h>
a3ce8d60	17	#include <dm/device_compat.h>
cd93d625	18	#include <linux/bitops.h>
c05ed00a	19	#include <linux/delay.h>
b4dbc5d6	20	#include <linux/iopoll.h>
ae74de0d	21	#include "serial_stm32.h"
336d4615	22	#include <dm/device_compat.h>
6a12cebd	23
9e8cbea1 VC	24	/*
	25	* At 115200 bits/s
	26	* 1 bit = 1 / 115200 = 8,68 us
	27	* 8 bits = 69,444 us
	28	* 10 bits are needed for worst case (8 bits + 1 start + 1 stop) = 86.806 us
	29	*/
	30	#define ONE_BYTE_B115200_US 87
	31
6261cf6a	32	static void _stm32_serial_setbrg(void __iomem *base,
215c8bed PD	33	struct stm32_uart_info *uart_info,
	34	u32 clock_rate,
	35	int baudrate)
6a12cebd	36	{
215c8bed	37	bool stm32f4 = uart_info->stm32f4;
27265cee	38	u32 int_div, mantissa, fraction, oversampling;
8ab9e8ff PC	39	u8 uart_enable_bit = uart_info->uart_enable_bit;
	40
	41	/* BRR register must be set when uart is disabled */
	42	clrbits_le32(base + CR1_OFFSET(stm32f4), BIT(uart_enable_bit));
ba0a3c16	43
215c8bed	44	int_div = DIV_ROUND_CLOSEST(clock_rate, baudrate);
1afcf9cb PC	45
	46	if (int_div < 16) {
	47	oversampling = 8;
60a996ba	48	setbits_le32(base + CR1_OFFSET(stm32f4), USART_CR1_OVER8);
1afcf9cb PC	49	} else {
1afcf9cb PC	50	oversampling = 16;
60a996ba	51	clrbits_le32(base + CR1_OFFSET(stm32f4), USART_CR1_OVER8);
1afcf9cb PC	52	}
	53
	54	mantissa = (int_div / oversampling) << USART_BRR_M_SHIFT;
	55	fraction = int_div % oversampling;
	56
60a996ba	57	writel(mantissa \| fraction, base + BRR_OFFSET(stm32f4));
8ab9e8ff PC	58
8ab9e8ff PC	59	setbits_le32(base + CR1_OFFSET(stm32f4), BIT(uart_enable_bit));
215c8bed PD	60	}
	61
	62	static int stm32_serial_setbrg(struct udevice *dev, int baudrate)
	63	{
8a8d24bd	64	struct stm32x7_serial_plat *plat = dev_get_plat(dev);
215c8bed PD	65
	66	_stm32_serial_setbrg(plat->base, plat->uart_info,
	67	plat->clock_rate, baudrate);
6a12cebd VM	68
	69	return 0;
	70	}
	71
fbd5c72d	72	static int stm32_serial_setconfig(struct udevice *dev, uint serial_config)
bc709a41	73	{
8a8d24bd	74	struct stm32x7_serial_plat *plat = dev_get_plat(dev);
bc709a41 PD	75	bool stm32f4 = plat->uart_info->stm32f4;
bc709a41 PD	76	u8 uart_enable_bit = plat->uart_info->uart_enable_bit;
6261cf6a	77	void __iomem *cr1 = plat->base + CR1_OFFSET(stm32f4);
bc709a41	78	u32 config = 0;
fbd5c72d PC	79	uint parity = SERIAL_GET_PARITY(serial_config);
	80	uint bits = SERIAL_GET_BITS(serial_config);
	81	uint stop = SERIAL_GET_STOP(serial_config);
	82
	83	/*
	84	* only parity config is implemented, check if other serial settings
	85	* are the default one.
	86	* (STM32F4 serial IP didn't support parity setting)
	87	*/
	88	if (bits != SERIAL_8_BITS \|\| stop != SERIAL_ONE_STOP \|\| stm32f4)
	89	return -ENOTSUPP; /* not supported in driver*/
bc709a41 PD	90
	91	clrbits_le32(cr1, USART_CR1_RE \| USART_CR1_TE \| BIT(uart_enable_bit));
	92	/* update usart configuration (uart need to be disable)
fbd5c72d	93	* PCE: parity check enable
bc709a41 PD	94	* PS : '0' : Even / '1' : Odd
	95	* M[1:0] = '00' : 8 Data bits
	96	* M[1:0] = '01' : 9 Data bits with parity
	97	*/
	98	switch (parity) {
	99	default:
	100	case SERIAL_PAR_NONE:
	101	config = 0;
	102	break;
	103	case SERIAL_PAR_ODD:
	104	config = USART_CR1_PCE \| USART_CR1_PS \| USART_CR1_M0;
	105	break;
	106	case SERIAL_PAR_EVEN:
	107	config = USART_CR1_PCE \| USART_CR1_M0;
	108	break;
	109	}
fbd5c72d	110
bc709a41 PD	111	clrsetbits_le32(cr1,
	112	USART_CR1_PCE \| USART_CR1_PS \| USART_CR1_M1 \|
	113	USART_CR1_M0,
	114	config);
	115	setbits_le32(cr1, USART_CR1_RE \| USART_CR1_TE \| BIT(uart_enable_bit));
	116
	117	return 0;
	118	}
	119
6a12cebd VM	120	static int stm32_serial_getc(struct udevice *dev)
6a12cebd VM	121	{
8a8d24bd	122	struct stm32x7_serial_plat *plat = dev_get_plat(dev);
60a996ba	123	bool stm32f4 = plat->uart_info->stm32f4;
6261cf6a	124	void __iomem *base = plat->base;
7b3b74d3	125	u32 isr = readl(base + ISR_OFFSET(stm32f4));
6a12cebd	126
be1a6f77	127	if ((isr & USART_ISR_RXNE) == 0)
6a12cebd VM	128	return -EAGAIN;
6a12cebd VM	129
132518f3	130	if (isr & (USART_ISR_PE \| USART_ISR_ORE \| USART_ISR_FE)) {
7b3b74d3	131	if (!stm32f4)
bc709a41	132	setbits_le32(base + ICR_OFFSET,
132518f3 PD	133	USART_ICR_PCECF \| USART_ICR_ORECF \|
132518f3 PD	134	USART_ICR_FECF);
7b3b74d3 PC	135	else
	136	readl(base + RDR_OFFSET(stm32f4));
	137	return -EIO;
	138	}
	139
60a996ba	140	return readl(base + RDR_OFFSET(stm32f4));
6a12cebd VM	141	}
6a12cebd VM	142
6261cf6a	143	static int _stm32_serial_putc(void __iomem *base,
215c8bed PD	144	struct stm32_uart_info *uart_info,
215c8bed PD	145	const char c)
6a12cebd	146	{
215c8bed	147	bool stm32f4 = uart_info->stm32f4;
6a12cebd	148
be1a6f77	149	if ((readl(base + ISR_OFFSET(stm32f4)) & USART_ISR_TXE) == 0)
6a12cebd VM	150	return -EAGAIN;
6a12cebd VM	151
60a996ba	152	writel(c, base + TDR_OFFSET(stm32f4));
6a12cebd VM	153
	154	return 0;
	155	}
	156
215c8bed PD	157	static int stm32_serial_putc(struct udevice *dev, const char c)
215c8bed PD	158	{
8a8d24bd	159	struct stm32x7_serial_plat *plat = dev_get_plat(dev);
215c8bed PD	160
	161	return _stm32_serial_putc(plat->base, plat->uart_info, c);
	162	}
	163
6a12cebd VM	164	static int stm32_serial_pending(struct udevice *dev, bool input)
6a12cebd VM	165	{
8a8d24bd	166	struct stm32x7_serial_plat *plat = dev_get_plat(dev);
60a996ba	167	bool stm32f4 = plat->uart_info->stm32f4;
6261cf6a	168	void __iomem *base = plat->base;
6a12cebd VM	169
6a12cebd VM	170	if (input)
60a996ba	171	return readl(base + ISR_OFFSET(stm32f4)) &
be1a6f77	172	USART_ISR_RXNE ? 1 : 0;
6a12cebd	173	else
60a996ba	174	return readl(base + ISR_OFFSET(stm32f4)) &
be1a6f77	175	USART_ISR_TXE ? 0 : 1;
6a12cebd VM	176	}
6a12cebd VM	177
6261cf6a	178	static void _stm32_serial_init(void __iomem *base,
215c8bed PD	179	struct stm32_uart_info *uart_info)
	180	{
	181	bool stm32f4 = uart_info->stm32f4;
	182	u8 uart_enable_bit = uart_info->uart_enable_bit;
	183
	184	/* Disable uart-> enable fifo -> enable uart */
	185	clrbits_le32(base + CR1_OFFSET(stm32f4), USART_CR1_RE \| USART_CR1_TE \|
	186	BIT(uart_enable_bit));
	187	if (uart_info->has_fifo)
	188	setbits_le32(base + CR1_OFFSET(stm32f4), USART_CR1_FIFOEN);
	189	setbits_le32(base + CR1_OFFSET(stm32f4), USART_CR1_RE \| USART_CR1_TE \|
	190	BIT(uart_enable_bit));
	191	}
	192
6a12cebd VM	193	static int stm32_serial_probe(struct udevice *dev)
6a12cebd VM	194	{
8a8d24bd	195	struct stm32x7_serial_plat *plat = dev_get_plat(dev);
9a212d7f	196	struct clk clk;
f828fa4d	197	struct reset_ctl reset;
b4dbc5d6	198	u32 isr;
9a212d7f	199	int ret;
b4dbc5d6	200	bool stm32f4;
60a996ba PC	201
60a996ba PC	202	plat->uart_info = (struct stm32_uart_info *)dev_get_driver_data(dev);
b4dbc5d6	203	stm32f4 = plat->uart_info->stm32f4;
fd03b83a	204
fd03b83a VM	205	ret = clk_get_by_index(dev, 0, &clk);
	206	if (ret < 0)
	207	return ret;
	208
	209	ret = clk_enable(&clk);
	210	if (ret) {
	211	dev_err(dev, "failed to enable clock\n");
	212	return ret;
	213	}
fd03b83a	214
b4dbc5d6 PC	215	/*
	216	* before uart initialization, wait for TC bit (Transmission Complete)
	217	* in case there is still chars from previous bootstage to transmit
	218	*/
9e8cbea1 VC	219	ret = read_poll_timeout(readl, isr, isr & USART_ISR_TC, 50,
	220	16 * ONE_BYTE_B115200_US, plat->base + ISR_OFFSET(stm32f4));
	221	if (ret)
	222	dev_dbg(dev, "FIFO not empty, some character can be lost (%d)\n", ret);
b4dbc5d6	223
f828fa4d PC	224	ret = reset_get_by_index(dev, 0, &reset);
	225	if (!ret) {
	226	reset_assert(&reset);
	227	udelay(2);
	228	reset_deassert(&reset);
	229	}
	230
27265cee	231	plat->clock_rate = clk_get_rate(&clk);
585289b4	232	if (!plat->clock_rate) {
27265cee	233	clk_disable(&clk);
585289b4	234	return -EINVAL;
27265cee PC	235	};
27265cee PC	236
215c8bed	237	_stm32_serial_init(plat->base, plat->uart_info);
6a12cebd VM	238
	239	return 0;
	240	}
	241
42bf5e7c	242	static const struct udevice_id stm32_serial_id[] = {
6c30f15b	243	{ .compatible = "st,stm32-uart", .data = (ulong)&stm32f4_info},
2a7ecc53 PC	244	{ .compatible = "st,stm32f7-uart", .data = (ulong)&stm32f7_info},
2a7ecc53 PC	245	{ .compatible = "st,stm32h7-uart", .data = (ulong)&stm32h7_info},
42bf5e7c VM	246	{}
	247	};
	248
d1998a9f	249	static int stm32_serial_of_to_plat(struct udevice *dev)
42bf5e7c	250	{
8a8d24bd	251	struct stm32x7_serial_plat *plat = dev_get_plat(dev);
6261cf6a	252	fdt_addr_t addr;
42bf5e7c	253
6261cf6a PC	254	addr = dev_read_addr(dev);
6261cf6a PC	255	if (addr == FDT_ADDR_T_NONE)
42bf5e7c VM	256	return -EINVAL;
42bf5e7c VM	257
6261cf6a PC	258	plat->base = (void __iomem *)addr;
6261cf6a PC	259
42bf5e7c VM	260	return 0;
42bf5e7c VM	261	}
42bf5e7c	262
6a12cebd VM	263	static const struct dm_serial_ops stm32_serial_ops = {
	264	.putc = stm32_serial_putc,
	265	.pending = stm32_serial_pending,
	266	.getc = stm32_serial_getc,
	267	.setbrg = stm32_serial_setbrg,
fbd5c72d	268	.setconfig = stm32_serial_setconfig
6a12cebd VM	269	};
	270
	271	U_BOOT_DRIVER(serial_stm32) = {
ae74de0d	272	.name = "serial_stm32",
6a12cebd	273	.id = UCLASS_SERIAL,
42bf5e7c	274	.of_match = of_match_ptr(stm32_serial_id),
d1998a9f	275	.of_to_plat = of_match_ptr(stm32_serial_of_to_plat),
8a8d24bd	276	.plat_auto = sizeof(struct stm32x7_serial_plat),
6a12cebd VM	277	.ops = &stm32_serial_ops,
6a12cebd VM	278	.probe = stm32_serial_probe,
46879196	279	#if !CONFIG_IS_ENABLED(OF_CONTROL)
6a12cebd	280	.flags = DM_FLAG_PRE_RELOC,
46879196	281	#endif
6a12cebd	282	};
215c8bed PD	283
	284	#ifdef CONFIG_DEBUG_UART_STM32
	285	#include <debug_uart.h>
	286	static inline struct stm32_uart_info *_debug_uart_info(void)
	287	{
	288	struct stm32_uart_info *uart_info;
	289
	290	#if defined(CONFIG_STM32F4)
	291	uart_info = &stm32f4_info;
	292	#elif defined(CONFIG_STM32F7)
	293	uart_info = &stm32f7_info;
	294	#else
	295	uart_info = &stm32h7_info;
	296	#endif
	297	return uart_info;
	298	}
	299
	300	static inline void _debug_uart_init(void)
	301	{
6261cf6a	302	void __iomem base = (void __iomem )CONFIG_VAL(DEBUG_UART_BASE);
215c8bed PD	303	struct stm32_uart_info *uart_info = _debug_uart_info();
	304
	305	_stm32_serial_init(base, uart_info);
	306	_stm32_serial_setbrg(base, uart_info,
	307	CONFIG_DEBUG_UART_CLOCK,
	308	CONFIG_BAUDRATE);
215c8bed PD	309	}
	310
	311	static inline void _debug_uart_putc(int c)
	312	{
6261cf6a	313	void __iomem base = (void __iomem )CONFIG_VAL(DEBUG_UART_BASE);
215c8bed PD	314	struct stm32_uart_info *uart_info = _debug_uart_info();
	315
	316	while (_stm32_serial_putc(base, uart_info, c) == -EAGAIN)
66dba9a1	317	;
215c8bed PD	318	}
	319
	320	DEBUG_UART_FUNCS
	321	#endif