[J-u-boot.git] / drivers / misc / mpc83xx_serdes.c

// SPDX-License-Identifier: GPL-2.0+
/*
 * (C) Copyright 2018
 * Mario Six, Guntermann & Drunck GmbH, [email protected]
 *
 * base on the MPC83xx serdes initialization, which is
 *
 * Copyright 2007,2011 Freescale Semiconductor, Inc.
 * Copyright (C) 2008 MontaVista Software, Inc.
 */

#include <dm.h>
#include <log.h>
#include <mapmem.h>
#include <misc.h>
#include <linux/delay.h>

#include "mpc83xx_serdes.h"

/**
 * struct mpc83xx_serdes_priv - Private structure for MPC83xx serdes
 * @regs:  The device's register map
 * @rfcks: Variable to keep the serdes reference clock selection set during
 *	   initialization in (is or'd to every value written to SRDSCR4)
 */
struct mpc83xx_serdes_priv {
	struct mpc83xx_serdes_regs *regs;
	u32 rfcks;
};

/**
 * setup_sata() - Configure the SerDes device to SATA mode
 * @dev: The device to configure
 */
static void setup_sata(struct udevice *dev)
{
	struct mpc83xx_serdes_priv *priv = dev_get_priv(dev);

	/* Set and clear reset bits */
	setbits_be32(&priv->regs->srdsrstctl, SRDSRSTCTL_SATA_RESET);
	udelay(1000);
	clrbits_be32(&priv->regs->srdsrstctl, SRDSRSTCTL_SATA_RESET);

	/* Configure SRDSCR0 */
	clrsetbits_be32(&priv->regs->srdscr0,
			SRDSCR0_TXEQA_MASK | SRDSCR0_TXEQE_MASK,
			SRDSCR0_TXEQA_SATA | SRDSCR0_TXEQE_SATA);

	/* Configure SRDSCR1 */
	clrbits_be32(&priv->regs->srdscr1, SRDSCR1_PLLBW);

	/* Configure SRDSCR2 */
	clrsetbits_be32(&priv->regs->srdscr2,
			SRDSCR2_SEIC_MASK,
			SRDSCR2_SEIC_SATA);

	/* Configure SRDSCR3 */
	out_be32(&priv->regs->srdscr3,
		 SRDSCR3_KFR_SATA | SRDSCR3_KPH_SATA |
		 SRDSCR3_SDFM_SATA_PEX | SRDSCR3_SDTXL_SATA);

	/* Configure SRDSCR4 */
	out_be32(&priv->regs->srdscr4, priv->rfcks | SRDSCR4_PROT_SATA);
}

/**
 * setup_pex() - Configure the SerDes device to PCI Express mode
 * @dev:  The device to configure
 * @type: The PCI Express type to configure for (x1 or x2)
 */
static void setup_pex(struct udevice *dev, enum pex_type type)
{
	struct mpc83xx_serdes_priv *priv = dev_get_priv(dev);

	/* Configure SRDSCR1 */
	setbits_be32(&priv->regs->srdscr1, SRDSCR1_PLLBW);

	/* Configure SRDSCR2 */
	clrsetbits_be32(&priv->regs->srdscr2,
			SRDSCR2_SEIC_MASK,
			SRDSCR2_SEIC_PEX);

	/* Configure SRDSCR3 */
	out_be32(&priv->regs->srdscr3, SRDSCR3_SDFM_SATA_PEX);

	/* Configure SRDSCR4 */
	if (type == PEX_X2)
		out_be32(&priv->regs->srdscr4,
			 priv->rfcks | SRDSCR4_PROT_PEX | SRDSCR4_PLANE_X2);
	else
		out_be32(&priv->regs->srdscr4,
			 priv->rfcks | SRDSCR4_PROT_PEX);
}

/**
 * setup_sgmii() - Configure the SerDes device to SGMII mode
 * @dev: The device to configure
 */
static void setup_sgmii(struct udevice *dev)
{
	struct mpc83xx_serdes_priv *priv = dev_get_priv(dev);

	/* Configure SRDSCR1 */
	clrbits_be32(&priv->regs->srdscr1, SRDSCR1_PLLBW);

	/* Configure SRDSCR2 */
	clrsetbits_be32(&priv->regs->srdscr2,
			SRDSCR2_SEIC_MASK,
			SRDSCR2_SEIC_SGMII);

	/* Configure SRDSCR3 */
	out_be32(&priv->regs->srdscr3, 0);

	/* Configure SRDSCR4 */
	out_be32(&priv->regs->srdscr4, priv->rfcks | SRDSCR4_PROT_SGMII);
}

static int mpc83xx_serdes_probe(struct udevice *dev)
{
	struct mpc83xx_serdes_priv *priv = dev_get_priv(dev);
	bool vdd;
	const char *proto;

	priv->regs = map_sysmem(dev_read_addr(dev),
				sizeof(struct mpc83xx_serdes_regs));

	switch (dev_read_u32_default(dev, "serdes-clk", -1)) {
	case 100:
		priv->rfcks = SRDSCR4_RFCKS_100;
		break;
	case 125:
		priv->rfcks = SRDSCR4_RFCKS_125;
		break;
	case 150:
		priv->rfcks = SRDSCR4_RFCKS_150;
		break;
	default:
		debug("%s: Could not read serdes clock value\n", dev->name);
		return -EINVAL;
	}

	vdd = dev_read_bool(dev, "vdd");

	/* 1.0V corevdd */
	if (vdd) {
		/* DPPE/DPPA = 0 */
		clrbits_be32(&priv->regs->srdscr0, SRDSCR0_DPP_1V2);

		/* VDD = 0 */
		clrbits_be32(&priv->regs->srdscr0, SRDSCR2_VDD_1V2);
	}

	proto = dev_read_string(dev, "proto");

	/* protocol specific configuration */
	if (!strcmp(proto, "sata")) {
		setup_sata(dev);
	} else if (!strcmp(proto, "pex")) {
		setup_pex(dev, PEX_X1);
	} else if (!strcmp(proto, "pex-x2")) {
		setup_pex(dev, PEX_X2);
	} else if (!strcmp(proto, "sgmii")) {
		setup_sgmii(dev);
	} else {
		debug("%s: Invalid protocol value %s\n", dev->name, proto);
		return -EINVAL;
	}

	/* Do a software reset */
	setbits_be32(&priv->regs->srdsrstctl, SRDSRSTCTL_RST);

	return 0;
}

static const struct udevice_id mpc83xx_serdes_ids[] = {
	{ .compatible = "fsl,mpc83xx-serdes" },
	{ }
};

U_BOOT_DRIVER(mpc83xx_serdes) = {
	.name           = "mpc83xx_serdes",
	.id             = UCLASS_MISC,
	.of_match       = mpc83xx_serdes_ids,
	.probe          = mpc83xx_serdes_probe,
	.priv_auto	= sizeof(struct mpc83xx_serdes_priv),
};
Commit	Line	Data
d2166319 MS	1	// SPDX-License-Identifier: GPL-2.0+
	2	/*
	3	* (C) Copyright 2018
	4	* Mario Six, Guntermann & Drunck GmbH, [email protected]
	5	*
	6	* base on the MPC83xx serdes initialization, which is
	7	*
	8	* Copyright 2007,2011 Freescale Semiconductor, Inc.
	9	* Copyright (C) 2008 MontaVista Software, Inc.
	10	*/
	11
d2166319	12	#include <dm.h>
f7ae49fc	13	#include <log.h>
d2166319 MS	14	#include <mapmem.h>
d2166319 MS	15	#include <misc.h>
c05ed00a	16	#include <linux/delay.h>
d2166319 MS	17
	18	#include "mpc83xx_serdes.h"
	19
	20	/**
	21	* struct mpc83xx_serdes_priv - Private structure for MPC83xx serdes
	22	* @regs: The device's register map
	23	* @rfcks: Variable to keep the serdes reference clock selection set during
	24	* initialization in (is or'd to every value written to SRDSCR4)
	25	*/
	26	struct mpc83xx_serdes_priv {
	27	struct mpc83xx_serdes_regs *regs;
	28	u32 rfcks;
	29	};
	30
	31	/**
	32	* setup_sata() - Configure the SerDes device to SATA mode
	33	* @dev: The device to configure
	34	*/
	35	static void setup_sata(struct udevice *dev)
	36	{
	37	struct mpc83xx_serdes_priv *priv = dev_get_priv(dev);
	38
	39	/* Set and clear reset bits */
	40	setbits_be32(&priv->regs->srdsrstctl, SRDSRSTCTL_SATA_RESET);
	41	udelay(1000);
	42	clrbits_be32(&priv->regs->srdsrstctl, SRDSRSTCTL_SATA_RESET);
	43
	44	/* Configure SRDSCR0 */
	45	clrsetbits_be32(&priv->regs->srdscr0,
	46	SRDSCR0_TXEQA_MASK \| SRDSCR0_TXEQE_MASK,
	47	SRDSCR0_TXEQA_SATA \| SRDSCR0_TXEQE_SATA);
	48
	49	/* Configure SRDSCR1 */
	50	clrbits_be32(&priv->regs->srdscr1, SRDSCR1_PLLBW);
	51
	52	/* Configure SRDSCR2 */
	53	clrsetbits_be32(&priv->regs->srdscr2,
	54	SRDSCR2_SEIC_MASK,
	55	SRDSCR2_SEIC_SATA);
	56
	57	/* Configure SRDSCR3 */
	58	out_be32(&priv->regs->srdscr3,
	59	SRDSCR3_KFR_SATA \| SRDSCR3_KPH_SATA \|
	60	SRDSCR3_SDFM_SATA_PEX \| SRDSCR3_SDTXL_SATA);
	61
	62	/* Configure SRDSCR4 */
	63	out_be32(&priv->regs->srdscr4, priv->rfcks \| SRDSCR4_PROT_SATA);
	64	}
	65
	66	/**
	67	* setup_pex() - Configure the SerDes device to PCI Express mode
	68	* @dev: The device to configure
	69	* @type: The PCI Express type to configure for (x1 or x2)
	70	*/
	71	static void setup_pex(struct udevice *dev, enum pex_type type)
	72	{
	73	struct mpc83xx_serdes_priv *priv = dev_get_priv(dev);
	74
	75	/* Configure SRDSCR1 */
	76	setbits_be32(&priv->regs->srdscr1, SRDSCR1_PLLBW);
	77
	78	/* Configure SRDSCR2 */
	79	clrsetbits_be32(&priv->regs->srdscr2,
	80	SRDSCR2_SEIC_MASK,
81	SRDSCR2_SEIC_PEX);
82
83	/* Configure SRDSCR3 */
84	out_be32(&priv->regs->srdscr3, SRDSCR3_SDFM_SATA_PEX);
85
86	/* Configure SRDSCR4 */
87	if (type == PEX_X2)
88	out_be32(&priv->regs->srdscr4,
89	priv->rfcks \| SRDSCR4_PROT_PEX \| SRDSCR4_PLANE_X2);
90	else
91	out_be32(&priv->regs->srdscr4,
92	priv->rfcks \| SRDSCR4_PROT_PEX);
93	}
94
95	/**
96	* setup_sgmii() - Configure the SerDes device to SGMII mode
97	* @dev: The device to configure
98	*/
99	static void setup_sgmii(struct udevice *dev)
100	{
101	struct mpc83xx_serdes_priv *priv = dev_get_priv(dev);
102
103	/* Configure SRDSCR1 */
104	clrbits_be32(&priv->regs->srdscr1, SRDSCR1_PLLBW);
105
106	/* Configure SRDSCR2 */
107	clrsetbits_be32(&priv->regs->srdscr2,
108	SRDSCR2_SEIC_MASK,
109	SRDSCR2_SEIC_SGMII);
110
111	/* Configure SRDSCR3 */
112	out_be32(&priv->regs->srdscr3, 0);
113
114	/* Configure SRDSCR4 */
115	out_be32(&priv->regs->srdscr4, priv->rfcks \| SRDSCR4_PROT_SGMII);
116	}
117
118	static int mpc83xx_serdes_probe(struct udevice *dev)
119	{
120	struct mpc83xx_serdes_priv *priv = dev_get_priv(dev);
121	bool vdd;
122	const char *proto;
123
124	priv->regs = map_sysmem(dev_read_addr(dev),
125	sizeof(struct mpc83xx_serdes_regs));
126
127	switch (dev_read_u32_default(dev, "serdes-clk", -1)) {
128	case 100:
129	priv->rfcks = SRDSCR4_RFCKS_100;
130	break;
131	case 125:
132	priv->rfcks = SRDSCR4_RFCKS_125;
133	break;
134	case 150:
135	priv->rfcks = SRDSCR4_RFCKS_150;
136	break;
137	default:
138	debug("%s: Could not read serdes clock value\n", dev->name);
139	return -EINVAL;
140	}
141
142	vdd = dev_read_bool(dev, "vdd");
143
144	/* 1.0V corevdd */
145	if (vdd) {
146	/* DPPE/DPPA = 0 */
147	clrbits_be32(&priv->regs->srdscr0, SRDSCR0_DPP_1V2);
148
149	/* VDD = 0 */
150	clrbits_be32(&priv->regs->srdscr0, SRDSCR2_VDD_1V2);
151	}
152
153	proto = dev_read_string(dev, "proto");
154
155	/* protocol specific configuration */
156	if (!strcmp(proto, "sata")) {
157	setup_sata(dev);
158	} else if (!strcmp(proto, "pex")) {
159	setup_pex(dev, PEX_X1);
160	} else if (!strcmp(proto, "pex-x2")) {
161	setup_pex(dev, PEX_X2);
162	} else if (!strcmp(proto, "sgmii")) {
163	setup_sgmii(dev);
164	} else {
165	debug("%s: Invalid protocol value %s\n", dev->name, proto);
166	return -EINVAL;
167	}
168
169	/* Do a software reset */
170	setbits_be32(&priv->regs->srdsrstctl, SRDSRSTCTL_RST);
171
172	return 0;
173	}
174
175	static const struct udevice_id mpc83xx_serdes_ids[] = {
176	{ .compatible = "fsl,mpc83xx-serdes" },
177	{ }
178	};
179
180	U_BOOT_DRIVER(mpc83xx_serdes) = {
181	.name = "mpc83xx_serdes",
182	.id = UCLASS_MISC,
183	.of_match = mpc83xx_serdes_ids,
184	.probe = mpc83xx_serdes_probe,
41575d8e	185	.priv_auto = sizeof(struct mpc83xx_serdes_priv),
d2166319	186	};