[J-u-boot.git] / drivers / misc / fsl_portals.c

// SPDX-License-Identifier: GPL-2.0+
/*
 * Copyright 2008-2011 Freescale Semiconductor, Inc.
 * Copyright 2017 NXP
 */

#include <config.h>
#include <log.h>
#include <linux/libfdt.h>
#include <fdt_support.h>

#include <asm/processor.h>
#include <asm/io.h>
#ifdef CONFIG_PPC
#include <asm/fsl_portals.h>
#include <asm/fsl_liodn.h>
#else
#include <asm/arch-fsl-layerscape/fsl_portals.h>
#include <asm/arch-fsl-layerscape/fsl_icid.h>
#endif
#include <fsl_qbman.h>

#define MAX_BPORTALS (CFG_SYS_BMAN_CINH_SIZE / CFG_SYS_BMAN_SP_CINH_SIZE)
#define MAX_QPORTALS (CFG_SYS_QMAN_CINH_SIZE / CFG_SYS_QMAN_SP_CINH_SIZE)
void setup_qbman_portals(void)
{
	void __iomem *bpaddr = (void *)CFG_SYS_BMAN_CINH_BASE +
				CFG_SYS_BMAN_SWP_ISDR_REG;
	void __iomem *qpaddr = (void *)CFG_SYS_QMAN_CINH_BASE +
				CFG_SYS_QMAN_SWP_ISDR_REG;
	struct ccsr_qman *qman = (void *)CFG_SYS_FSL_QMAN_ADDR;

	/* Set the Qman initiator BAR to match the LAW (for DQRR stashing) */
#ifdef CONFIG_PHYS_64BIT
	out_be32(&qman->qcsp_bare, (u32)(CFG_SYS_QMAN_MEM_PHYS >> 32));
#endif
	out_be32(&qman->qcsp_bar, (u32)CFG_SYS_QMAN_MEM_PHYS);
#ifdef CONFIG_FSL_CORENET
	int i;

	for (i = 0; i < CFG_SYS_QMAN_NUM_PORTALS; i++) {
		u8 sdest = qp_info[i].sdest;
		u16 fliodn = qp_info[i].fliodn;
		u16 dliodn = qp_info[i].dliodn;
		u16 liodn_off = qp_info[i].liodn_offset;

		out_be32(&qman->qcsp[i].qcsp_lio_cfg, (liodn_off << 16) |
					dliodn);
		/* set frame liodn */
		out_be32(&qman->qcsp[i].qcsp_io_cfg, (sdest << 16) | fliodn);
	}
#else
#if defined(CONFIG_ARCH_LS1043A) || defined(CONFIG_ARCH_LS1046A)
	int i;

	for (i = 0; i < CFG_SYS_QMAN_NUM_PORTALS; i++) {
		u8 sdest = qp_info[i].sdest;
		u16 ficid = qp_info[i].ficid;
		u16 dicid = qp_info[i].dicid;
		u16 icid = qp_info[i].icid;

		out_be32(&qman->qcsp[i].qcsp_lio_cfg, (icid << 16) |
					dicid);
		/* set frame icid */
		out_be32(&qman->qcsp[i].qcsp_io_cfg, (sdest << 16) | ficid);
	}
#endif
#endif

	/* Change default state of BMan ISDR portals to all 1s */
	inhibit_portals(bpaddr, CFG_SYS_BMAN_NUM_PORTALS, MAX_BPORTALS,
			CFG_SYS_BMAN_SP_CINH_SIZE);
	inhibit_portals(qpaddr, CFG_SYS_QMAN_NUM_PORTALS, MAX_QPORTALS,
			CFG_SYS_QMAN_SP_CINH_SIZE);
}

void inhibit_portals(void __iomem *addr, int max_portals,
		     int arch_max_portals, int portal_cinh_size)
{
	u32 val;
	int i;

	/* arch_max_portals is the maximum based on memory size. This includes
	 * the reserved memory in the SoC.  max_portals the number of physical
	 * portals in the SoC
	 */
	if (max_portals > arch_max_portals) {
		printf("ERROR: portal config error\n");
		max_portals = arch_max_portals;
	}

	for (i = 0; i < max_portals; i++) {
		out_be32(addr, -1);
		val = in_be32(addr);
		if (!val) {
			printf("ERROR: Stopped after %d portals\n", i);
			return;
		}
		addr += portal_cinh_size;
	}
	debug("Cleared %d portals\n", i);
}

#ifdef CONFIG_PPC
static int fdt_qportal(void *blob, int off, int id, char *name,
		       enum fsl_dpaa_dev dev, int create)
{
	int childoff, dev_off, ret = 0;
	unsigned int dev_handle;
#ifdef CONFIG_FSL_CORENET
	int num;
	u32 liodns[2];
#endif

	childoff = fdt_subnode_offset(blob, off, name);
	if (create) {
		char handle[64], *p;

		strncpy(handle, name, sizeof(handle));
		p = strchr(handle, '@');
		if (!strncmp(name, "fman", 4)) {
			*p = *(p + 1);
			p++;
		}
		*p = '\0';

		dev_off = fdt_path_offset(blob, handle);
		/* skip this node if alias is not found */
		if (dev_off == -FDT_ERR_BADPATH)
			return 0;
		if (dev_off < 0)
			return dev_off;

		if (childoff <= 0)
			childoff = fdt_add_subnode(blob, off, name);

		/* need to update the dev_off after adding a subnode */
		dev_off = fdt_path_offset(blob, handle);
		if (dev_off < 0)
			return dev_off;

		if (childoff > 0) {
			dev_handle = fdt_get_phandle(blob, dev_off);
			if (dev_handle <= 0) {
				dev_handle = fdt_create_phandle(blob, dev_off);
				if (!dev_handle)
					return -FDT_ERR_NOPHANDLES;
			}

			ret = fdt_setprop(blob, childoff, "dev-handle",
					  &dev_handle, sizeof(dev_handle));
			if (ret < 0)
				return ret;

#ifdef CONFIG_FSL_CORENET
			num = get_dpaa_liodn(dev, &liodns[0], id);
			ret = fdt_setprop(blob, childoff, "fsl,liodn",
					  &liodns[0], sizeof(u32) * num);
			if (!strncmp(name, "pme", 3)) {
				u32 pme_rev1, pme_rev2;
				ccsr_pme_t *pme_regs =
					(void *)CFG_SYS_FSL_CORENET_PME_ADDR;

				pme_rev1 = in_be32(&pme_regs->pm_ip_rev_1);
				pme_rev2 = in_be32(&pme_regs->pm_ip_rev_2);
				ret = fdt_setprop(blob, childoff,
						  "fsl,pme-rev1", &pme_rev1,
						  sizeof(u32));
				if (ret < 0)
					return ret;
				ret = fdt_setprop(blob, childoff,
						  "fsl,pme-rev2", &pme_rev2,
						  sizeof(u32));
			}
#endif
		} else {
			return childoff;
		}
	} else {
		if (childoff > 0)
			ret = fdt_del_node(blob, childoff);
	}

	return ret;
}
#endif /* CONFIG_PPC */

void fdt_fixup_qportals(void *blob)
{
	int off, err;
	unsigned int maj, min;
	unsigned int ip_cfg;
	struct ccsr_qman *qman = (void *)CFG_SYS_FSL_QMAN_ADDR;
	u32 rev_1 = in_be32(&qman->ip_rev_1);
	u32 rev_2 = in_be32(&qman->ip_rev_2);
	char compat[64];
	int compat_len;

#if defined(CONFIG_ARCH_LS1043A) || defined(CONFIG_ARCH_LS1046A)
	int smmu_ph = fdt_get_smmu_phandle(blob);
#endif

	maj = (rev_1 >> 8) & 0xff;
	min = rev_1 & 0xff;
	ip_cfg = rev_2 & 0xff;

	compat_len = sprintf(compat, "fsl,qman-portal-%u.%u.%u",
			     maj, min, ip_cfg) + 1;
	compat_len += sprintf(compat + compat_len, "fsl,qman-portal") + 1;

	fdt_for_each_node_by_compatible(off, blob, -1, "fsl,qman-portal") {
#if defined(CONFIG_PPC) || defined(CONFIG_ARCH_LS1043A) || \
defined(CONFIG_ARCH_LS1046A)
#ifdef CONFIG_FSL_CORENET
		u32 liodns[2];
#endif
		const int *ci = fdt_getprop(blob, off, "cell-index", &err);
		int i;

		if (!ci)
			goto err;

		i = fdt32_to_cpu(*ci);
#if defined(CONFIG_SYS_DPAA_FMAN) && defined(CONFIG_PPC)
		int j;
#endif

#endif /* CONFIG_PPC || CONFIG_ARCH_LS1043A || CONFIG_ARCH_LS1046A */
		err = fdt_setprop(blob, off, "compatible", compat, compat_len);
		if (err < 0)
			goto err;
#ifdef CONFIG_PPC
#ifdef CONFIG_FSL_CORENET
		liodns[0] = qp_info[i].dliodn;
		liodns[1] = qp_info[i].fliodn;
		err = fdt_setprop(blob, off, "fsl,liodn",
				  &liodns, sizeof(u32) * 2);
		if (err < 0)
			goto err;
#endif

		i++;

		err = fdt_qportal(blob, off, i, "crypto@0", FSL_HW_PORTAL_SEC,
				  IS_E_PROCESSOR(get_svr()));
		if (err < 0)
			goto err;

#ifdef CONFIG_FSL_CORENET
#ifdef CONFIG_SYS_DPAA_PME
		err = fdt_qportal(blob, off, i, "pme@0", FSL_HW_PORTAL_PME, 1);
		if (err < 0)
			goto err;
#else
		fdt_qportal(blob, off, i, "pme@0", FSL_HW_PORTAL_PME, 0);
#endif
#endif

#ifdef CONFIG_SYS_DPAA_FMAN
		for (j = 0; j < CFG_SYS_NUM_FMAN; j++) {
			char name[] = "fman@0";

			name[sizeof(name) - 2] = '0' + j;
			err = fdt_qportal(blob, off, i, name,
					  FSL_HW_PORTAL_FMAN1 + j, 1);
			if (err < 0)
				goto err;
		}
#endif
#ifdef CONFIG_SYS_DPAA_RMAN
		err = fdt_qportal(blob, off, i, "rman@0",
				  FSL_HW_PORTAL_RMAN, 1);
		if (err < 0)
			goto err;
#endif
#else
#if defined(CONFIG_ARCH_LS1043A) || defined(CONFIG_ARCH_LS1046A)
		if (smmu_ph >= 0) {
			u32 icids[3];

			icids[0] = qp_info[i].icid;
			icids[1] = qp_info[i].dicid;
			icids[2] = qp_info[i].ficid;

			fdt_set_iommu_prop(blob, off, smmu_ph, icids, 3);
		}
#endif
#endif /* CONFIG_PPC */

err:
		if (err < 0) {
			printf("ERROR: unable to create props for %s: %s\n",
			       fdt_get_name(blob, off, NULL),
			       fdt_strerror(err));
			return;
		}
	}
}

void fdt_fixup_bportals(void *blob)
{
	int off, err;
	unsigned int maj, min;
	unsigned int ip_cfg;
	struct ccsr_bman *bman = (void *)CFG_SYS_FSL_BMAN_ADDR;
	u32 rev_1 = in_be32(&bman->ip_rev_1);
	u32 rev_2 = in_be32(&bman->ip_rev_2);
	char compat[64];
	int compat_len;

	maj = (rev_1 >> 8) & 0xff;
	min = rev_1 & 0xff;

	ip_cfg = rev_2 & 0xff;

	compat_len = sprintf(compat, "fsl,bman-portal-%u.%u.%u",
			     maj, min, ip_cfg) + 1;
	compat_len += sprintf(compat + compat_len, "fsl,bman-portal") + 1;

	off = fdt_node_offset_by_compatible(blob, -1, "fsl,bman-portal");
	while (off != -FDT_ERR_NOTFOUND) {
		err = fdt_setprop(blob, off, "compatible", compat, compat_len);
		if (err < 0) {
			printf("ERROR: unable to create props for %s: %s\n",
			       fdt_get_name(blob, off, NULL),
			       fdt_strerror(err));
			return;
		}

		off = fdt_node_offset_by_compatible(blob, off,
						    "fsl,bman-portal");
	}
}
Commit	Line	Data
83d290c5	1	// SPDX-License-Identifier: GPL-2.0+
44262327 AM	2	/*
	3	* Copyright 2008-2011 Freescale Semiconductor, Inc.
	4	* Copyright 2017 NXP
44262327 AM	5	*/
44262327 AM	6
03de305e	7	#include <config.h>
f7ae49fc	8	#include <log.h>
b08c8c48	9	#include <linux/libfdt.h>
44262327 AM	10	#include <fdt_support.h>
	11
	12	#include <asm/processor.h>
	13	#include <asm/io.h>
	14	#ifdef CONFIG_PPC
	15	#include <asm/fsl_portals.h>
	16	#include <asm/fsl_liodn.h>
599a97d4 LT	17	#else
	18	#include <asm/arch-fsl-layerscape/fsl_portals.h>
	19	#include <asm/arch-fsl-layerscape/fsl_icid.h>
44262327 AM	20	#endif
	21	#include <fsl_qbman.h>
	22
65cc0e2a TR	23	#define MAX_BPORTALS (CFG_SYS_BMAN_CINH_SIZE / CFG_SYS_BMAN_SP_CINH_SIZE)
65cc0e2a TR	24	#define MAX_QPORTALS (CFG_SYS_QMAN_CINH_SIZE / CFG_SYS_QMAN_SP_CINH_SIZE)
44262327 AM	25	void setup_qbman_portals(void)
44262327 AM	26	{
65cc0e2a TR	27	void __iomem bpaddr = (void )CFG_SYS_BMAN_CINH_BASE +
	28	CFG_SYS_BMAN_SWP_ISDR_REG;
	29	void __iomem qpaddr = (void )CFG_SYS_QMAN_CINH_BASE +
	30	CFG_SYS_QMAN_SWP_ISDR_REG;
6cc04547	31	struct ccsr_qman qman = (void )CFG_SYS_FSL_QMAN_ADDR;
44262327 AM	32
	33	/* Set the Qman initiator BAR to match the LAW (for DQRR stashing) */
	34	#ifdef CONFIG_PHYS_64BIT
65cc0e2a	35	out_be32(&qman->qcsp_bare, (u32)(CFG_SYS_QMAN_MEM_PHYS >> 32));
44262327	36	#endif
65cc0e2a	37	out_be32(&qman->qcsp_bar, (u32)CFG_SYS_QMAN_MEM_PHYS);
44262327 AM	38	#ifdef CONFIG_FSL_CORENET
	39	int i;
	40
65cc0e2a	41	for (i = 0; i < CFG_SYS_QMAN_NUM_PORTALS; i++) {
44262327 AM	42	u8 sdest = qp_info[i].sdest;
	43	u16 fliodn = qp_info[i].fliodn;
	44	u16 dliodn = qp_info[i].dliodn;
	45	u16 liodn_off = qp_info[i].liodn_offset;
	46
	47	out_be32(&qman->qcsp[i].qcsp_lio_cfg, (liodn_off << 16) \|
	48	dliodn);
	49	/* set frame liodn */
	50	out_be32(&qman->qcsp[i].qcsp_io_cfg, (sdest << 16) \| fliodn);
	51	}
599a97d4	52	#else
0c2255b5	53	#if defined(CONFIG_ARCH_LS1043A) \|\| defined(CONFIG_ARCH_LS1046A)
599a97d4 LT	54	int i;
599a97d4 LT	55
65cc0e2a	56	for (i = 0; i < CFG_SYS_QMAN_NUM_PORTALS; i++) {
599a97d4 LT	57	u8 sdest = qp_info[i].sdest;
	58	u16 ficid = qp_info[i].ficid;
	59	u16 dicid = qp_info[i].dicid;
	60	u16 icid = qp_info[i].icid;
	61
	62	out_be32(&qman->qcsp[i].qcsp_lio_cfg, (icid << 16) \|
	63	dicid);
	64	/* set frame icid */
	65	out_be32(&qman->qcsp[i].qcsp_io_cfg, (sdest << 16) \| ficid);
	66	}
	67	#endif
44262327 AM	68	#endif
	69
	70	/* Change default state of BMan ISDR portals to all 1s */
65cc0e2a TR	71	inhibit_portals(bpaddr, CFG_SYS_BMAN_NUM_PORTALS, MAX_BPORTALS,
	72	CFG_SYS_BMAN_SP_CINH_SIZE);
	73	inhibit_portals(qpaddr, CFG_SYS_QMAN_NUM_PORTALS, MAX_QPORTALS,
	74	CFG_SYS_QMAN_SP_CINH_SIZE);
44262327 AM	75	}
	76
	77	void inhibit_portals(void __iomem *addr, int max_portals,
	78	int arch_max_portals, int portal_cinh_size)
	79	{
	80	u32 val;
	81	int i;
	82
	83	/* arch_max_portals is the maximum based on memory size. This includes
	84	* the reserved memory in the SoC. max_portals the number of physical
	85	* portals in the SoC
	86	*/
	87	if (max_portals > arch_max_portals) {
	88	printf("ERROR: portal config error\n");
	89	max_portals = arch_max_portals;
	90	}
	91
	92	for (i = 0; i < max_portals; i++) {
	93	out_be32(addr, -1);
	94	val = in_be32(addr);
	95	if (!val) {
	96	printf("ERROR: Stopped after %d portals\n", i);
	97	return;
	98	}
	99	addr += portal_cinh_size;
	100	}
	101	debug("Cleared %d portals\n", i);
	102	}
	103
	104	#ifdef CONFIG_PPC
	105	static int fdt_qportal(void blob, int off, int id, char name,
	106	enum fsl_dpaa_dev dev, int create)
	107	{
	108	int childoff, dev_off, ret = 0;
68a2faa9	109	unsigned int dev_handle;
44262327 AM	110	#ifdef CONFIG_FSL_CORENET
	111	int num;
	112	u32 liodns[2];
	113	#endif
	114
	115	childoff = fdt_subnode_offset(blob, off, name);
	116	if (create) {
	117	char handle[64], *p;
	118
	119	strncpy(handle, name, sizeof(handle));
	120	p = strchr(handle, '@');
	121	if (!strncmp(name, "fman", 4)) {
	122	p = (p + 1);
	123	p++;
	124	}
	125	*p = '\0';
	126
	127	dev_off = fdt_path_offset(blob, handle);
	128	/* skip this node if alias is not found */
	129	if (dev_off == -FDT_ERR_BADPATH)
	130	return 0;
	131	if (dev_off < 0)
	132	return dev_off;
	133
	134	if (childoff <= 0)
	135	childoff = fdt_add_subnode(blob, off, name);
	136
	137	/* need to update the dev_off after adding a subnode */
	138	dev_off = fdt_path_offset(blob, handle);
	139	if (dev_off < 0)
	140	return dev_off;
	141
	142	if (childoff > 0) {
	143	dev_handle = fdt_get_phandle(blob, dev_off);
	144	if (dev_handle <= 0) {
68a2faa9 MB	145	dev_handle = fdt_create_phandle(blob, dev_off);
	146	if (!dev_handle)
	147	return -FDT_ERR_NOPHANDLES;
44262327 AM	148	}
	149
	150	ret = fdt_setprop(blob, childoff, "dev-handle",
	151	&dev_handle, sizeof(dev_handle));
	152	if (ret < 0)
	153	return ret;
	154
	155	#ifdef CONFIG_FSL_CORENET
	156	num = get_dpaa_liodn(dev, &liodns[0], id);
	157	ret = fdt_setprop(blob, childoff, "fsl,liodn",
	158	&liodns[0], sizeof(u32) * num);
	159	if (!strncmp(name, "pme", 3)) {
	160	u32 pme_rev1, pme_rev2;
	161	ccsr_pme_t *pme_regs =
6cc04547	162	(void *)CFG_SYS_FSL_CORENET_PME_ADDR;
44262327 AM	163
	164	pme_rev1 = in_be32(&pme_regs->pm_ip_rev_1);
	165	pme_rev2 = in_be32(&pme_regs->pm_ip_rev_2);
	166	ret = fdt_setprop(blob, childoff,
	167	"fsl,pme-rev1", &pme_rev1,
	168	sizeof(u32));
	169	if (ret < 0)
	170	return ret;
	171	ret = fdt_setprop(blob, childoff,
	172	"fsl,pme-rev2", &pme_rev2,
	173	sizeof(u32));
	174	}
	175	#endif
	176	} else {
	177	return childoff;
	178	}
	179	} else {
	180	if (childoff > 0)
	181	ret = fdt_del_node(blob, childoff);
	182	}
	183
	184	return ret;
	185	}
	186	#endif /* CONFIG_PPC */
	187
	188	void fdt_fixup_qportals(void *blob)
	189	{
	190	int off, err;
	191	unsigned int maj, min;
	192	unsigned int ip_cfg;
6cc04547	193	struct ccsr_qman qman = (void )CFG_SYS_FSL_QMAN_ADDR;
44262327 AM	194	u32 rev_1 = in_be32(&qman->ip_rev_1);
	195	u32 rev_2 = in_be32(&qman->ip_rev_2);
	196	char compat[64];
	197	int compat_len;
	198
0c2255b5	199	#if defined(CONFIG_ARCH_LS1043A) \|\| defined(CONFIG_ARCH_LS1046A)
599a97d4 LT	200	int smmu_ph = fdt_get_smmu_phandle(blob);
	201	#endif
	202
44262327 AM	203	maj = (rev_1 >> 8) & 0xff;
	204	min = rev_1 & 0xff;
	205	ip_cfg = rev_2 & 0xff;
	206
	207	compat_len = sprintf(compat, "fsl,qman-portal-%u.%u.%u",
	208	maj, min, ip_cfg) + 1;
	209	compat_len += sprintf(compat + compat_len, "fsl,qman-portal") + 1;
	210
3058e283	211	fdt_for_each_node_by_compatible(off, blob, -1, "fsl,qman-portal") {
0c2255b5 LT	212	#if defined(CONFIG_PPC) \|\| defined(CONFIG_ARCH_LS1043A) \|\| \
0c2255b5 LT	213	defined(CONFIG_ARCH_LS1046A)
44262327 AM	214	#ifdef CONFIG_FSL_CORENET
	215	u32 liodns[2];
	216	#endif
	217	const int *ci = fdt_getprop(blob, off, "cell-index", &err);
	218	int i;
	219
	220	if (!ci)
	221	goto err;
	222
599a97d4 LT	223	i = fdt32_to_cpu(*ci);
599a97d4 LT	224	#if defined(CONFIG_SYS_DPAA_FMAN) && defined(CONFIG_PPC)
44262327 AM	225	int j;
	226	#endif
	227
0c2255b5	228	#endif /* CONFIG_PPC \|\| CONFIG_ARCH_LS1043A \|\| CONFIG_ARCH_LS1046A */
44262327 AM	229	err = fdt_setprop(blob, off, "compatible", compat, compat_len);
	230	if (err < 0)
	231	goto err;
	232	#ifdef CONFIG_PPC
	233	#ifdef CONFIG_FSL_CORENET
	234	liodns[0] = qp_info[i].dliodn;
	235	liodns[1] = qp_info[i].fliodn;
	236	err = fdt_setprop(blob, off, "fsl,liodn",
	237	&liodns, sizeof(u32) * 2);
	238	if (err < 0)
	239	goto err;
	240	#endif
	241
	242	i++;
	243
	244	err = fdt_qportal(blob, off, i, "crypto@0", FSL_HW_PORTAL_SEC,
	245	IS_E_PROCESSOR(get_svr()));
	246	if (err < 0)
	247	goto err;
	248
	249	#ifdef CONFIG_FSL_CORENET
	250	#ifdef CONFIG_SYS_DPAA_PME
	251	err = fdt_qportal(blob, off, i, "pme@0", FSL_HW_PORTAL_PME, 1);
	252	if (err < 0)
	253	goto err;
	254	#else
	255	fdt_qportal(blob, off, i, "pme@0", FSL_HW_PORTAL_PME, 0);
	256	#endif
	257	#endif
	258
	259	#ifdef CONFIG_SYS_DPAA_FMAN
cdc5ed8f	260	for (j = 0; j < CFG_SYS_NUM_FMAN; j++) {
44262327 AM	261	char name[] = "fman@0";
	262
	263	name[sizeof(name) - 2] = '0' + j;
	264	err = fdt_qportal(blob, off, i, name,
	265	FSL_HW_PORTAL_FMAN1 + j, 1);
	266	if (err < 0)
	267	goto err;
	268	}
	269	#endif
	270	#ifdef CONFIG_SYS_DPAA_RMAN
	271	err = fdt_qportal(blob, off, i, "rman@0",
	272	FSL_HW_PORTAL_RMAN, 1);
	273	if (err < 0)
	274	goto err;
	275	#endif
599a97d4	276	#else
0c2255b5	277	#if defined(CONFIG_ARCH_LS1043A) \|\| defined(CONFIG_ARCH_LS1046A)
599a97d4 LT	278	if (smmu_ph >= 0) {
	279	u32 icids[3];
	280
	281	icids[0] = qp_info[i].icid;
	282	icids[1] = qp_info[i].dicid;
	283	icids[2] = qp_info[i].ficid;
	284
	285	fdt_set_iommu_prop(blob, off, smmu_ph, icids, 3);
	286	}
	287	#endif
44262327 AM	288	#endif /* CONFIG_PPC */
	289
	290	err:
	291	if (err < 0) {
	292	printf("ERROR: unable to create props for %s: %s\n",
	293	fdt_get_name(blob, off, NULL),
	294	fdt_strerror(err));
	295	return;
	296	}
44262327 AM	297	}
	298	}
	299
	300	void fdt_fixup_bportals(void *blob)
	301	{
	302	int off, err;
	303	unsigned int maj, min;
	304	unsigned int ip_cfg;
6cc04547	305	struct ccsr_bman bman = (void )CFG_SYS_FSL_BMAN_ADDR;
44262327 AM	306	u32 rev_1 = in_be32(&bman->ip_rev_1);
	307	u32 rev_2 = in_be32(&bman->ip_rev_2);
	308	char compat[64];
	309	int compat_len;
	310
	311	maj = (rev_1 >> 8) & 0xff;
	312	min = rev_1 & 0xff;
	313
	314	ip_cfg = rev_2 & 0xff;
	315
	316	compat_len = sprintf(compat, "fsl,bman-portal-%u.%u.%u",
	317	maj, min, ip_cfg) + 1;
	318	compat_len += sprintf(compat + compat_len, "fsl,bman-portal") + 1;
	319
	320	off = fdt_node_offset_by_compatible(blob, -1, "fsl,bman-portal");
	321	while (off != -FDT_ERR_NOTFOUND) {
	322	err = fdt_setprop(blob, off, "compatible", compat, compat_len);
	323	if (err < 0) {
	324	printf("ERROR: unable to create props for %s: %s\n",
	325	fdt_get_name(blob, off, NULL),
	326	fdt_strerror(err));
	327	return;
	328	}
	329
	330	off = fdt_node_offset_by_compatible(blob, off,
	331	"fsl,bman-portal");
	332	}
	333	}