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83d290c5 | 1 | // SPDX-License-Identifier: GPL-2.0+ |
ff9c4c53 SR |
2 | /* |
3 | * Copyright (C) 2016 Stefan Roese <[email protected]> | |
ff9c4c53 SR |
4 | */ |
5 | ||
ff9c4c53 | 6 | #include <altera.h> |
f7ae49fc | 7 | #include <log.h> |
ff9c4c53 SR |
8 | #include <spi.h> |
9 | #include <asm/io.h> | |
c05ed00a | 10 | #include <linux/delay.h> |
1221ce45 | 11 | #include <linux/errno.h> |
ff9c4c53 SR |
12 | |
13 | /* Write the RBF data to FPGA via SPI */ | |
14 | static int program_write(int spi_bus, int spi_dev, const void *rbf_data, | |
15 | unsigned long rbf_size) | |
16 | { | |
17 | struct spi_slave *slave; | |
18 | int ret; | |
19 | ||
20 | debug("%s (%d): data=%p size=%ld\n", | |
21 | __func__, __LINE__, rbf_data, rbf_size); | |
22 | ||
23 | /* FIXME: How to get the max. SPI clock and SPI mode? */ | |
24 | slave = spi_setup_slave(spi_bus, spi_dev, 27777777, SPI_MODE_3); | |
25 | if (!slave) | |
26 | return -1; | |
27 | ||
28 | if (spi_claim_bus(slave)) | |
29 | return -1; | |
30 | ||
31 | ret = spi_xfer(slave, rbf_size * 8, rbf_data, (void *)rbf_data, | |
32 | SPI_XFER_BEGIN | SPI_XFER_END); | |
33 | ||
34 | spi_release_bus(slave); | |
35 | ||
36 | return ret; | |
37 | } | |
38 | ||
39 | /* | |
40 | * This is the interface used by FPGA driver. | |
41 | * Return 0 for sucess, non-zero for error. | |
42 | */ | |
43 | int stratixv_load(Altera_desc *desc, const void *rbf_data, size_t rbf_size) | |
44 | { | |
45 | altera_board_specific_func *pfns = desc->iface_fns; | |
46 | int cookie = desc->cookie; | |
47 | int spi_bus; | |
48 | int spi_dev; | |
49 | int ret = 0; | |
50 | ||
51 | if ((u32)rbf_data & 0x3) { | |
52 | puts("FPGA: Unaligned data, realign to 32bit boundary.\n"); | |
53 | return -EINVAL; | |
54 | } | |
55 | ||
56 | /* Run the pre configuration function if there is one */ | |
57 | if (pfns->pre) | |
58 | (pfns->pre)(cookie); | |
59 | ||
60 | /* Establish the initial state */ | |
61 | if (pfns->config) { | |
62 | /* De-assert nCONFIG */ | |
63 | (pfns->config)(false, true, cookie); | |
64 | ||
65 | /* nConfig minimum low pulse width is 2us */ | |
66 | udelay(200); | |
67 | ||
68 | /* Assert nCONFIG */ | |
69 | (pfns->config)(true, true, cookie); | |
70 | ||
71 | /* nCONFIG high to first rising clock on DCLK min 1506 us */ | |
72 | udelay(1600); | |
73 | } | |
74 | ||
75 | /* Write the RBF data to FPGA */ | |
76 | if (pfns->write) { | |
77 | /* | |
78 | * Use board specific data function to write bitstream | |
79 | * into the FPGA | |
80 | */ | |
81 | ret = (pfns->write)(rbf_data, rbf_size, true, cookie); | |
82 | } else { | |
83 | /* | |
84 | * Use common SPI functions to write bitstream into the | |
85 | * FPGA | |
86 | */ | |
87 | spi_bus = COOKIE2SPI_BUS(cookie); | |
88 | spi_dev = COOKIE2SPI_DEV(cookie); | |
89 | ret = program_write(spi_bus, spi_dev, rbf_data, rbf_size); | |
90 | } | |
91 | if (ret) | |
92 | return ret; | |
93 | ||
94 | /* Check done pin */ | |
95 | if (pfns->done) { | |
96 | ret = (pfns->done)(cookie); | |
97 | ||
98 | if (ret) | |
99 | printf("Error: DONE not set (ret=%d)!\n", ret); | |
100 | } | |
101 | ||
102 | return ret; | |
103 | } |