[J-u-boot.git] / drivers / fpga / stratixII.c

// SPDX-License-Identifier: GPL-2.0+
/*
 * (C) Copyright 2007
 * Eran Liberty, Extricom , [email protected]
 */

#include <altera.h>
#include <linux/delay.h>

int StratixII_ps_fpp_load (Altera_desc * desc, void *buf, size_t bsize,
			   int isSerial, int isSecure);
int StratixII_ps_fpp_dump (Altera_desc * desc, void *buf, size_t bsize);

/****************************************************************/
/* Stratix II Generic Implementation                            */
int StratixII_load (Altera_desc * desc, void *buf, size_t bsize)
{
	int ret_val = FPGA_FAIL;

	switch (desc->iface) {
	case passive_serial:
		ret_val = StratixII_ps_fpp_load (desc, buf, bsize, 1, 0);
		break;
	case fast_passive_parallel:
		ret_val = StratixII_ps_fpp_load (desc, buf, bsize, 0, 0);
		break;
	case fast_passive_parallel_security:
		ret_val = StratixII_ps_fpp_load (desc, buf, bsize, 0, 1);
		break;

		/* Add new interface types here */
	default:
		printf ("%s: Unsupported interface type, %d\n", __FUNCTION__,
			desc->iface);
	}
	return ret_val;
}

int StratixII_dump (Altera_desc * desc, void *buf, size_t bsize)
{
	int ret_val = FPGA_FAIL;

	switch (desc->iface) {
	case passive_serial:
	case fast_passive_parallel:
	case fast_passive_parallel_security:
		ret_val = StratixII_ps_fpp_dump (desc, buf, bsize);
		break;
		/* Add new interface types here */
	default:
		printf ("%s: Unsupported interface type, %d\n", __FUNCTION__,
			desc->iface);
	}
	return ret_val;
}

int StratixII_info (Altera_desc * desc)
{
	return FPGA_SUCCESS;
}

int StratixII_ps_fpp_dump (Altera_desc * desc, void *buf, size_t bsize)
{
	printf ("Stratix II Fast Passive Parallel dump is not implemented\n");
	return FPGA_FAIL;
}

int StratixII_ps_fpp_load (Altera_desc * desc, void *buf, size_t bsize,
			   int isSerial, int isSecure)
{
	altera_board_specific_func *fns;
	int cookie;
	int ret_val = FPGA_FAIL;
	int bytecount;
	char *buff = buf;
	int i;

	if (!desc) {
		printf ("%s(%d) Altera_desc missing\n", __FUNCTION__, __LINE__);
		return FPGA_FAIL;
	}
	if (!buff) {
		printf ("%s(%d) buffer is missing\n", __FUNCTION__, __LINE__);
		return FPGA_FAIL;
	}
	if (!bsize) {
		printf ("%s(%d) size is zero\n", __FUNCTION__, __LINE__);
		return FPGA_FAIL;
	}
	if (!desc->iface_fns) {
		printf
		    ("%s(%d) Altera_desc function interface table is missing\n",
		     __FUNCTION__, __LINE__);
		return FPGA_FAIL;
	}
	fns = (altera_board_specific_func *) (desc->iface_fns);
	cookie = desc->cookie;

	if (!
	    (fns->config && fns->status && fns->done && fns->data
	     && fns->abort)) {
		printf
		    ("%s(%d) Missing some function in the function interface table\n",
		     __FUNCTION__, __LINE__);
		return FPGA_FAIL;
	}

	/* 1. give board specific a chance to do anything before we start */
	if (fns->pre) {
		if ((ret_val = fns->pre (cookie)) < 0) {
			return ret_val;
		}
	}

	/* from this point on we must fail gracfully by calling lower layer abort */

	/* 2. Strat burn cycle by deasserting config for t_CFG and waiting t_CF2CK after reaserted */
	fns->config (0, 1, cookie);
	udelay(5);		/* nCONFIG low pulse width 2usec */
	fns->config (1, 1, cookie);
	udelay(100);		/* nCONFIG high to first rising edge on DCLK */

	/* 3. Start the Data cycle with clk deasserted */
	bytecount = 0;
	fns->clk (0, 1, cookie);

	printf ("loading to fpga    ");
	while (bytecount < bsize) {
		/* 3.1 check stratix has not signaled us an error */
		if (fns->status (cookie) != 1) {
			printf
			    ("\n%s(%d) Stratix failed (byte transferred till failure 0x%x)\n",
			     __FUNCTION__, __LINE__, bytecount);
			fns->abort (cookie);
			return FPGA_FAIL;
		}
		if (isSerial) {
			int i;
			uint8_t data = buff[bytecount++];
			for (i = 0; i < 8; i++) {
				/* 3.2(ps) put data on the bus */
				fns->data ((data >> i) & 1, 1, cookie);

				/* 3.3(ps) clock once */
				fns->clk (1, 1, cookie);
				fns->clk (0, 1, cookie);
			}
		} else {
			/* 3.2(fpp) put data on the bus */
			fns->data (buff[bytecount++], 1, cookie);

			/* 3.3(fpp) clock once */
			fns->clk (1, 1, cookie);
			fns->clk (0, 1, cookie);

			/* 3.4(fpp) for secure cycle push 3 more  clocks */
			for (i = 0; isSecure && i < 3; i++) {
				fns->clk (1, 1, cookie);
				fns->clk (0, 1, cookie);
			}
		}

		/* 3.5 while clk is deasserted it is safe to print some progress indication */
		if ((bytecount % (bsize / 100)) == 0) {
			printf ("\b\b\b%02d\%", bytecount * 100 / bsize);
		}
	}

	/* 4. Set one last clock and check conf done signal */
	fns->clk (1, 1, cookie);
	udelay(100);
	if (!fns->done (cookie)) {
		printf (" error!.\n");
		fns->abort (cookie);
		return FPGA_FAIL;
	} else {
		printf ("\b\b\b done.\n");
	}

	/* 5. call lower layer post configuration */
	if (fns->post) {
		if ((ret_val = fns->post (cookie)) < 0) {
			fns->abort (cookie);
			return ret_val;
		}
	}

	return FPGA_SUCCESS;
}
Commit	Line	Data
83d290c5	1	// SPDX-License-Identifier: GPL-2.0+
3c735e74	2	/*
	3	* (C) Copyright 2007
	4	* Eran Liberty, Extricom , [email protected]
3c735e74	5	*/
3c735e74	6
3c735e74	7	#include <altera.h>
c05ed00a	8	#include <linux/delay.h>
3c735e74	9
3c735e74	10	int StratixII_ps_fpp_load (Altera_desc * desc, void *buf, size_t bsize,
	11	int isSerial, int isSecure);
	12	int StratixII_ps_fpp_dump (Altera_desc * desc, void *buf, size_t bsize);
	13
	14	/****************************************************************/
	15	/* Stratix II Generic Implementation */
	16	int StratixII_load (Altera_desc * desc, void *buf, size_t bsize)
	17	{
	18	int ret_val = FPGA_FAIL;
	19
	20	switch (desc->iface) {
	21	case passive_serial:
	22	ret_val = StratixII_ps_fpp_load (desc, buf, bsize, 1, 0);
	23	break;
	24	case fast_passive_parallel:
	25	ret_val = StratixII_ps_fpp_load (desc, buf, bsize, 0, 0);
	26	break;
	27	case fast_passive_parallel_security:
	28	ret_val = StratixII_ps_fpp_load (desc, buf, bsize, 0, 1);
	29	break;
	30
	31	/* Add new interface types here */
	32	default:
	33	printf ("%s: Unsupported interface type, %d\n", __FUNCTION__,
	34	desc->iface);
	35	}
	36	return ret_val;
	37	}
	38
	39	int StratixII_dump (Altera_desc * desc, void *buf, size_t bsize)
	40	{
	41	int ret_val = FPGA_FAIL;
	42
	43	switch (desc->iface) {
	44	case passive_serial:
	45	case fast_passive_parallel:
	46	case fast_passive_parallel_security:
	47	ret_val = StratixII_ps_fpp_dump (desc, buf, bsize);
	48	break;
	49	/* Add new interface types here */
	50	default:
	51	printf ("%s: Unsupported interface type, %d\n", __FUNCTION__,
	52	desc->iface);
	53	}
	54	return ret_val;
	55	}
	56
	57	int StratixII_info (Altera_desc * desc)
	58	{
	59	return FPGA_SUCCESS;
	60	}
	61
3c735e74	62	int StratixII_ps_fpp_dump (Altera_desc * desc, void *buf, size_t bsize)
	63	{
	64	printf ("Stratix II Fast Passive Parallel dump is not implemented\n");
	65	return FPGA_FAIL;
	66	}
	67
	68	int StratixII_ps_fpp_load (Altera_desc * desc, void *buf, size_t bsize,
	69	int isSerial, int isSecure)
	70	{
	71	altera_board_specific_func *fns;
	72	int cookie;
	73	int ret_val = FPGA_FAIL;
	74	int bytecount;
	75	char *buff = buf;
	76	int i;
	77
	78	if (!desc) {
	79	printf ("%s(%d) Altera_desc missing\n", __FUNCTION__, __LINE__);
	80	return FPGA_FAIL;
	81	}
	82	if (!buff) {
	83	printf ("%s(%d) buffer is missing\n", __FUNCTION__, __LINE__);
	84	return FPGA_FAIL;
	85	}
	86	if (!bsize) {
	87	printf ("%s(%d) size is zero\n", __FUNCTION__, __LINE__);
	88	return FPGA_FAIL;
	89	}
	90	if (!desc->iface_fns) {
	91	printf
	92	("%s(%d) Altera_desc function interface table is missing\n",
	93	__FUNCTION__, __LINE__);
	94	return FPGA_FAIL;
	95	}
	96	fns = (altera_board_specific_func *) (desc->iface_fns);
	97	cookie = desc->cookie;
	98
	99	if (!
	100	(fns->config && fns->status && fns->done && fns->data
	101	&& fns->abort)) {
	102	printf
	103	("%s(%d) Missing some function in the function interface table\n",
	104	__FUNCTION__, __LINE__);
	105	return FPGA_FAIL;
	106	}
	107
	108	/* 1. give board specific a chance to do anything before we start */
	109	if (fns->pre) {
	110	if ((ret_val = fns->pre (cookie)) < 0) {
	111	return ret_val;
	112	}
	113	}
	114
	115	/* from this point on we must fail gracfully by calling lower layer abort */
	116
	117	/* 2. Strat burn cycle by deasserting config for t_CFG and waiting t_CF2CK after reaserted */
	118	fns->config (0, 1, cookie);
07e11146	119	udelay(5); /* nCONFIG low pulse width 2usec */
3c735e74	120	fns->config (1, 1, cookie);
07e11146	121	udelay(100); /* nCONFIG high to first rising edge on DCLK */
3c735e74	122
	123	/* 3. Start the Data cycle with clk deasserted */
	124	bytecount = 0;
	125	fns->clk (0, 1, cookie);
	126
	127	printf ("loading to fpga ");
	128	while (bytecount < bsize) {
	129	/* 3.1 check stratix has not signaled us an error */
	130	if (fns->status (cookie) != 1) {
	131	printf
a6f70a3d	132	("\n%s(%d) Stratix failed (byte transferred till failure 0x%x)\n",
3c735e74	133	__FUNCTION__, __LINE__, bytecount);
	134	fns->abort (cookie);
	135	return FPGA_FAIL;
	136	}
	137	if (isSerial) {
	138	int i;
	139	uint8_t data = buff[bytecount++];
	140	for (i = 0; i < 8; i++) {
	141	/* 3.2(ps) put data on the bus */
	142	fns->data ((data >> i) & 1, 1, cookie);
	143
	144	/* 3.3(ps) clock once */
	145	fns->clk (1, 1, cookie);
	146	fns->clk (0, 1, cookie);
	147	}
	148	} else {
	149	/* 3.2(fpp) put data on the bus */
	150	fns->data (buff[bytecount++], 1, cookie);
	151
	152	/* 3.3(fpp) clock once */
	153	fns->clk (1, 1, cookie);
	154	fns->clk (0, 1, cookie);
	155
	156	/* 3.4(fpp) for secure cycle push 3 more clocks */
	157	for (i = 0; isSecure && i < 3; i++) {
	158	fns->clk (1, 1, cookie);
	159	fns->clk (0, 1, cookie);
	160	}
	161	}
	162
	163	/* 3.5 while clk is deasserted it is safe to print some progress indication */
	164	if ((bytecount % (bsize / 100)) == 0) {
	165	printf ("\b\b\b%02d\%", bytecount * 100 / bsize);
	166	}
	167	}
	168
	169	/* 4. Set one last clock and check conf done signal */
	170	fns->clk (1, 1, cookie);
07e11146	171	udelay(100);
3c735e74	172	if (!fns->done (cookie)) {
	173	printf (" error!.\n");
	174	fns->abort (cookie);
	175	return FPGA_FAIL;
	176	} else {
	177	printf ("\b\b\b done.\n");
	178	}
	179
	180	/* 5. call lower layer post configuration */
	181	if (fns->post) {
	182	if ((ret_val = fns->post (cookie)) < 0) {
	183	fns->abort (cookie);
	184	return ret_val;
	185	}
	186	}
	187
	188	return FPGA_SUCCESS;
	189	}