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Merge tag 'u-boot-imx-master-20250127' of https://gitlab.denx.de/u-boot/custodians...
[J-u-boot.git] / drivers / ram / rockchip / sdram_rk322x.c
CommitLineData
c43acfdc 1// SPDX-License-Identifier: GPL-2.0+ OR BSD-3-Clause
0176399b
KY		 2/*
3 * (C) Copyright 2017 Rockchip Electronics Co., Ltd
0176399b 4 */
03de305e 5#include <config.h>
0176399b
KY		 6#include <clk.h>
7#include <dm.h>
8#include <dt-structs.h>
9#include <errno.h>
691d719d 10#include <init.h>
0176399b
KY		 11#include <ram.h>
12#include <regmap.h>
13#include <syscon.h>
401d1c4f 14#include <asm/global_data.h>
15f09a1a
KY		 15#include <asm/arch-rockchip/clock.h>
16#include <asm/arch-rockchip/cru_rk322x.h>
17#include <asm/arch-rockchip/grf_rk322x.h>
18#include <asm/arch-rockchip/hardware.h>
19#include <asm/arch-rockchip/sdram_rk322x.h>
15f09a1a 20#include <asm/arch-rockchip/uart.h>
5d19ddf0 21#include <asm/arch-rockchip/sdram.h>
0176399b 22#include <asm/types.h>
c05ed00a 23#include <linux/delay.h>
0176399b
KY		 24#include <linux/err.h>
25
26DECLARE_GLOBAL_DATA_PTR;
27struct chan_info {
28 struct rk322x_ddr_pctl *pctl;
29 struct rk322x_ddr_phy *phy;
30 struct rk322x_service_sys *msch;
31};
32
33struct dram_info {
34 struct chan_info chan[1];
35 struct ram_info info;
36 struct clk ddr_clk;
37 struct rk322x_cru *cru;
38 struct rk322x_grf *grf;
39};
40
41struct rk322x_sdram_params {
42#if CONFIG_IS_ENABLED(OF_PLATDATA)
43 struct dtd_rockchip_rk3228_dmc of_plat;
44#endif
45 struct rk322x_sdram_channel ch[1];
46 struct rk322x_pctl_timing pctl_timing;
47 struct rk322x_phy_timing phy_timing;
48 struct rk322x_base_params base;
49 int num_channels;
50 struct regmap *map;
51};
52
2f523787 53#ifdef CONFIG_TPL_BUILD
0176399b
KY		 54/*
55 * [7:6] bank(n:n bit bank)
56 * [5:4] row(13+n)
57 * [3] cs(0:1 cs, 1:2 cs)
58 * [2:1] bank(n:n bit bank)
59 * [0] col(10+n)
60 */
61const char ddr_cfg_2_rbc[] = {
62 ((0 << 6) | (0 << 4) | (0 << 3) | (1 << 2) | 1),
63 ((0 << 6) | (1 << 4) | (0 << 3) | (1 << 2) | 1),
64 ((0 << 6) | (2 << 4) | (0 << 3) | (1 << 2) | 1),
65 ((0 << 6) | (3 << 4) | (0 << 3) | (1 << 2) | 1),
66 ((0 << 6) | (1 << 4) | (0 << 3) | (1 << 2) | 2),
67 ((0 << 6) | (2 << 4) | (0 << 3) | (1 << 2) | 2),
68 ((0 << 6) | (3 << 4) | (0 << 3) | (1 << 2) | 2),
69 ((0 << 6) | (0 << 4) | (0 << 3) | (1 << 2) | 0),
70 ((0 << 6) | (1 << 4) | (0 << 3) | (1 << 2) | 0),
71 ((0 << 6) | (2 << 4) | (0 << 3) | (1 << 2) | 0),
72 ((0 << 6) | (3 << 4) | (0 << 3) | (1 << 2) | 0),
73 ((0 << 6) | (2 << 4) | (0 << 3) | (0 << 2) | 1),
74 ((1 << 6) | (1 << 4) | (0 << 3) | (0 << 2) | 2),
75 ((1 << 6) | (1 << 4) | (0 << 3) | (0 << 2) | 1),
76 ((0 << 6) | (3 << 4) | (1 << 3) | (1 << 2) | 1),
77 ((0 << 6) | (3 << 4) | (1 << 3) | (1 << 2) | 0),
78};
79
80static void copy_to_reg(u32 *dest, const u32 *src, u32 n)
81{
82 int i;
83
84 for (i = 0; i < n / sizeof(u32); i++) {
85 writel(*src, dest);
86 src++;
87 dest++;
88 }
89}
90
91void phy_pctrl_reset(struct rk322x_cru *cru,
92 struct rk322x_ddr_phy *ddr_phy)
93{
94 rk_clrsetreg(&cru->cru_softrst_con[5], 1 << DDRCTRL_PSRST_SHIFT |
95 1 << DDRCTRL_SRST_SHIFT | 1 << DDRPHY_PSRST_SHIFT |
96 1 << DDRPHY_SRST_SHIFT,
97 1 << DDRCTRL_PSRST_SHIFT | 1 << DDRCTRL_SRST_SHIFT |
98 1 << DDRPHY_PSRST_SHIFT | 1 << DDRPHY_SRST_SHIFT);
99
f3d689c0 100 udelay(10);
0176399b
KY		 101
102 rk_clrreg(&cru->cru_softrst_con[5], 1 << DDRPHY_PSRST_SHIFT |
103 1 << DDRPHY_SRST_SHIFT);
f3d689c0 104 udelay(10);
0176399b
KY		 105
106 rk_clrreg(&cru->cru_softrst_con[5], 1 << DDRCTRL_PSRST_SHIFT |
107 1 << DDRCTRL_SRST_SHIFT);
f3d689c0 108 udelay(10);
0176399b
KY		 109
110 clrbits_le32(&ddr_phy->ddrphy_reg[0],
111 SOFT_RESET_MASK << SOFT_RESET_SHIFT);
f3d689c0 112 udelay(10);
0176399b
KY		 113 setbits_le32(&ddr_phy->ddrphy_reg[0],
114 SOFT_DERESET_ANALOG);
f3d689c0 115 udelay(5);
0176399b
KY		 116 setbits_le32(&ddr_phy->ddrphy_reg[0],
117 SOFT_DERESET_DIGITAL);
118
f3d689c0 119 udelay(1);
0176399b
KY		 120}
121
122void phy_dll_bypass_set(struct rk322x_ddr_phy *ddr_phy, u32 freq)
123{
124 u32 tmp;
125
126 setbits_le32(&ddr_phy->ddrphy_reg[0x13], 0x10);
127 setbits_le32(&ddr_phy->ddrphy_reg[0x26], 0x10);
128 setbits_le32(&ddr_phy->ddrphy_reg[0x36], 0x10);
129 setbits_le32(&ddr_phy->ddrphy_reg[0x46], 0x10);
130 setbits_le32(&ddr_phy->ddrphy_reg[0x56], 0x10);
131
132 clrbits_le32(&ddr_phy->ddrphy_reg[0x14], 0x8);
133 clrbits_le32(&ddr_phy->ddrphy_reg[0x27], 0x8);
134 clrbits_le32(&ddr_phy->ddrphy_reg[0x37], 0x8);
135 clrbits_le32(&ddr_phy->ddrphy_reg[0x47], 0x8);
136 clrbits_le32(&ddr_phy->ddrphy_reg[0x57], 0x8);
137
138 if (freq <= 400)
139 setbits_le32(&ddr_phy->ddrphy_reg[0xa4], 0x1f);
140 else
141 clrbits_le32(&ddr_phy->ddrphy_reg[0xa4], 0x1f);
142
143 if (freq <= 680)
144 tmp = 3;
145 else
146 tmp = 2;
147
148 writel(tmp, &ddr_phy->ddrphy_reg[0x28]);
149 writel(tmp, &ddr_phy->ddrphy_reg[0x38]);
150 writel(tmp, &ddr_phy->ddrphy_reg[0x48]);
151 writel(tmp, &ddr_phy->ddrphy_reg[0x58]);
152}
153
154static void send_command(struct rk322x_ddr_pctl *pctl,
155 u32 rank, u32 cmd, u32 arg)
156{
157 writel((START_CMD | (rank << 20) | arg | cmd), &pctl->mcmd);
f3d689c0 158 udelay(1);
0176399b
KY		 159 while (readl(&pctl->mcmd) & START_CMD)
160 ;
161}
162
163static void memory_init(struct chan_info *chan,
164 struct rk322x_sdram_params *sdram_params)
165{
166 struct rk322x_ddr_pctl *pctl = chan->pctl;
167 u32 dramtype = sdram_params->base.dramtype;
168
169 if (dramtype == DDR3) {
170 send_command(pctl, 3, DESELECT_CMD, 0);
f3d689c0 171 udelay(1);
0176399b
KY		 172 send_command(pctl, 3, PREA_CMD, 0);
173 send_command(pctl, 3, MRS_CMD,
174 (0x02 & BANK_ADDR_MASK) << BANK_ADDR_SHIFT |
175 (sdram_params->phy_timing.mr[2] & CMD_ADDR_MASK) <<
176 CMD_ADDR_SHIFT);
177
178 send_command(pctl, 3, MRS_CMD,
179 (0x03 & BANK_ADDR_MASK) << BANK_ADDR_SHIFT |
180 (sdram_params->phy_timing.mr[3] & CMD_ADDR_MASK) <<
181 CMD_ADDR_SHIFT);
182
183 send_command(pctl, 3, MRS_CMD,
184 (0x01 & BANK_ADDR_MASK) << BANK_ADDR_SHIFT |
185 (sdram_params->phy_timing.mr[1] & CMD_ADDR_MASK) <<
186 CMD_ADDR_SHIFT);
187
188 send_command(pctl, 3, MRS_CMD,
189 (0x00 & BANK_ADDR_MASK) << BANK_ADDR_SHIFT |
190 ((sdram_params->phy_timing.mr[0] |
191 DDR3_DLL_RESET) &
192 CMD_ADDR_MASK) << CMD_ADDR_SHIFT);
193
194 send_command(pctl, 3, ZQCL_CMD, 0);
195 } else {
196 send_command(pctl, 3, MRS_CMD,
197 (0x63 & LPDDR23_MA_MASK) << LPDDR23_MA_SHIFT |
198 (0 & LPDDR23_OP_MASK) <<
199 LPDDR23_OP_SHIFT);
f3d689c0 200 udelay(10);
0176399b
KY		 201 send_command(pctl, 3, MRS_CMD,
202 (0x10 & LPDDR23_MA_MASK) << LPDDR23_MA_SHIFT |
203 (0xff & LPDDR23_OP_MASK) <<
204 LPDDR23_OP_SHIFT);
f3d689c0 205 udelay(1);
0176399b
KY		 206 send_command(pctl, 3, MRS_CMD,
207 (0x10 & LPDDR23_MA_MASK) << LPDDR23_MA_SHIFT |
208 (0xff & LPDDR23_OP_MASK) <<
209 LPDDR23_OP_SHIFT);
f3d689c0 210 udelay(1);
0176399b
KY		 211 send_command(pctl, 3, MRS_CMD,
212 (1 & LPDDR23_MA_MASK) << LPDDR23_MA_SHIFT |
213 (sdram_params->phy_timing.mr[1] &
214 LPDDR23_OP_MASK) << LPDDR23_OP_SHIFT);
215 send_command(pctl, 3, MRS_CMD,
216 (2 & LPDDR23_MA_MASK) << LPDDR23_MA_SHIFT |
217 (sdram_params->phy_timing.mr[2] &
218 LPDDR23_OP_MASK) << LPDDR23_OP_SHIFT);
219 send_command(pctl, 3, MRS_CMD,
220 (3 & LPDDR23_MA_MASK) << LPDDR23_MA_SHIFT |
221 (sdram_params->phy_timing.mr[3] &
222 LPDDR23_OP_MASK) << LPDDR23_OP_SHIFT);
223 if (dramtype == LPDDR3)
224 send_command(pctl, 3, MRS_CMD, (11 & LPDDR23_MA_MASK) <<
225 LPDDR23_MA_SHIFT |
226 (sdram_params->phy_timing.mr11 &
227 LPDDR23_OP_MASK) << LPDDR23_OP_SHIFT);
228 }
229}
230
231static u32 data_training(struct chan_info *chan)
232{
233 struct rk322x_ddr_phy *ddr_phy = chan->phy;
234 struct rk322x_ddr_pctl *pctl = chan->pctl;
235 u32 value;
236 u32 bw = (readl(&ddr_phy->ddrphy_reg[0]) >> 4) & 0xf;
237 u32 ret;
238
239 /* disable auto refresh */
240 value = readl(&pctl->trefi) | (1 << 31);
241 writel(1 << 31, &pctl->trefi);
242
243 clrsetbits_le32(&ddr_phy->ddrphy_reg[2], 0x30,
244 DQS_SQU_CAL_SEL_CS0);
245 setbits_le32(&ddr_phy->ddrphy_reg[2], DQS_SQU_CAL_START);
246
f3d689c0 247 udelay(30);
0176399b
KY		 248 ret = readl(&ddr_phy->ddrphy_reg[0xff]);
249
250 clrbits_le32(&ddr_phy->ddrphy_reg[2],
251 DQS_SQU_CAL_START);
252
253 /*
254 * since data training will take about 20us, so send some auto
255 * refresh(about 7.8us) to complement the lost time
256 */
257 send_command(pctl, 3, PREA_CMD, 0);
258 send_command(pctl, 3, REF_CMD, 0);
259
260 writel(value, &pctl->trefi);
261
262 if (ret & 0x10) {
263 ret = -1;
264 } else {
265 ret = (ret & 0xf) ^ bw;
266 ret = (ret == 0) ? 0 : -1;
267 }
268 return ret;
269}
270
271static void move_to_config_state(struct rk322x_ddr_pctl *pctl)
272{
273 unsigned int state;
274
275 while (1) {
276 state = readl(&pctl->stat) & PCTL_STAT_MASK;
277 switch (state) {
278 case LOW_POWER:
279 writel(WAKEUP_STATE, &pctl->sctl);
280 while ((readl(&pctl->stat) & PCTL_STAT_MASK)
281 != ACCESS)
282 ;
283 /*
284 * If at low power state, need wakeup first, and then
285 * enter the config, so fallthrough
286 */
287 case ACCESS:
288 /* fallthrough */
289 case INIT_MEM:
290 writel(CFG_STATE, &pctl->sctl);
291 while ((readl(&pctl->stat) & PCTL_STAT_MASK) != CONFIG)
292 ;
293 break;
294 case CONFIG:
295 return;
296 default:
297 break;
298 }
299 }
300}
301
302static void move_to_access_state(struct rk322x_ddr_pctl *pctl)
303{
304 unsigned int state;
305
306 while (1) {
307 state = readl(&pctl->stat) & PCTL_STAT_MASK;
308 switch (state) {
309 case LOW_POWER:
310 writel(WAKEUP_STATE, &pctl->sctl);
311 while ((readl(&pctl->stat) & PCTL_STAT_MASK) != ACCESS)
312 ;
313 break;
314 case INIT_MEM:
315 writel(CFG_STATE, &pctl->sctl);
316 while ((readl(&pctl->stat) & PCTL_STAT_MASK) != CONFIG)
317 ;
318 /* fallthrough */
319 case CONFIG:
320 writel(GO_STATE, &pctl->sctl);
321 while ((readl(&pctl->stat) & PCTL_STAT_MASK) != ACCESS)
322 ;
323 break;
324 case ACCESS:
325 return;
326 default:
327 break;
328 }
329 }
330}
331
332static void move_to_lowpower_state(struct rk322x_ddr_pctl *pctl)
333{
334 unsigned int state;
335
336 while (1) {
337 state = readl(&pctl->stat) & PCTL_STAT_MASK;
338 switch (state) {
339 case INIT_MEM:
340 writel(CFG_STATE, &pctl->sctl);
341 while ((readl(&pctl->stat) & PCTL_STAT_MASK) != CONFIG)
342 ;
343 /* fallthrough */
344 case CONFIG:
345 writel(GO_STATE, &pctl->sctl);
346 while ((readl(&pctl->stat) & PCTL_STAT_MASK) != ACCESS)
347 ;
348 break;
349 case ACCESS:
350 writel(SLEEP_STATE, &pctl->sctl);
351 while ((readl(&pctl->stat) & PCTL_STAT_MASK) !=
352 LOW_POWER)
353 ;
354 break;
355 case LOW_POWER:
356 return;
357 default:
358 break;
359 }
360 }
361}
362
363/* pctl should in low power mode when call this function */
364static void phy_softreset(struct dram_info *dram)
365{
366 struct rk322x_ddr_phy *ddr_phy = dram->chan[0].phy;
367 struct rk322x_grf *grf = dram->grf;
368
369 writel(GRF_DDRPHY_BUFFEREN_CORE_EN, &grf->soc_con[0]);
370 clrbits_le32(&ddr_phy->ddrphy_reg[0], 0x3 << 2);
f3d689c0 371 udelay(1);
0176399b 372 setbits_le32(&ddr_phy->ddrphy_reg[0], 1 << 2);
f3d689c0 373 udelay(5);
0176399b
KY		 374 setbits_le32(&ddr_phy->ddrphy_reg[0], 1 << 3);
375 writel(GRF_DDRPHY_BUFFEREN_CORE_DIS, &grf->soc_con[0]);
376}
377
378/* bw: 2: 32bit, 1:16bit */
379static void set_bw(struct dram_info *dram, u32 bw)
380{
381 struct rk322x_ddr_pctl *pctl = dram->chan[0].pctl;
382 struct rk322x_ddr_phy *ddr_phy = dram->chan[0].phy;
383 struct rk322x_grf *grf = dram->grf;
384
385 if (bw == 1) {
386 setbits_le32(&pctl->ppcfg, 1);
387 clrbits_le32(&ddr_phy->ddrphy_reg[0], 0xc << 4);
388 writel(GRF_MSCH_NOC_16BIT_EN, &grf->soc_con[0]);
389 clrbits_le32(&ddr_phy->ddrphy_reg[0x46], 0x8);
390 clrbits_le32(&ddr_phy->ddrphy_reg[0x56], 0x8);
391 } else {
392 clrbits_le32(&pctl->ppcfg, 1);
393 setbits_le32(&ddr_phy->ddrphy_reg[0], 0xf << 4);
394 writel(GRF_DDR_32BIT_EN | GRF_MSCH_NOC_32BIT_EN,
395 &grf->soc_con[0]);
396 setbits_le32(&ddr_phy->ddrphy_reg[0x46], 0x8);
397 setbits_le32(&ddr_phy->ddrphy_reg[0x56], 0x8);
398 }
399}
400
401static void pctl_cfg(struct rk322x_ddr_pctl *pctl,
402 struct rk322x_sdram_params *sdram_params,
403 struct rk322x_grf *grf)
404{
405 u32 burst_len;
406 u32 bw;
407 u32 dramtype = sdram_params->base.dramtype;
408
409 if (sdram_params->ch[0].bw == 2)
410 bw = GRF_DDR_32BIT_EN | GRF_MSCH_NOC_32BIT_EN;
411 else
412 bw = GRF_MSCH_NOC_16BIT_EN;
413
414 writel(DFI_INIT_START | DFI_DATA_BYTE_DISABLE_EN, &pctl->dfistcfg0);
415 writel(DFI_DRAM_CLK_SR_EN | DFI_DRAM_CLK_DPD_EN, &pctl->dfistcfg1);
416 writel(DFI_PARITY_INTR_EN | DFI_PARITY_EN, &pctl->dfistcfg2);
417 writel(0x51010, &pctl->dfilpcfg0);
418
419 writel(1, &pctl->dfitphyupdtype0);
420 writel(0x0d, &pctl->dfitphyrdlat);
421 writel(0, &pctl->dfitphywrdata);
422
423 writel(0, &pctl->dfiupdcfg);
424 copy_to_reg(&pctl->togcnt1u, &sdram_params->pctl_timing.togcnt1u,
425 sizeof(struct rk322x_pctl_timing));
426 if (dramtype == DDR3) {
427 writel((1 << 3) | (1 << 11),
428 &pctl->dfiodtcfg);
429 writel(7 << 16, &pctl->dfiodtcfg1);
430 writel((readl(&pctl->tcl) - 1) / 2 - 1, &pctl->dfitrddataen);
431 writel((readl(&pctl->tcwl) - 1) / 2 - 1, &pctl->dfitphywrlat);
432 writel(500, &pctl->trsth);
433 writel(0 << MDDR_LPDDR2_CLK_STOP_IDLE_SHIFT | DDR3_EN |
434 DDR2_DDR3_BL_8 | (6 - 4) << TFAW_SHIFT | PD_EXIT_SLOW |
435 1 << PD_TYPE_SHIFT | 0 << PD_IDLE_SHIFT,
436 &pctl->mcfg);
437 writel(bw | GRF_DDR3_EN, &grf->soc_con[0]);
438 } else {
439 if (sdram_params->phy_timing.bl & PHT_BL_8)
440 burst_len = MDDR_LPDDR2_BL_8;
441 else
442 burst_len = MDDR_LPDDR2_BL_4;
443
444 writel(readl(&pctl->tcl) / 2 - 1, &pctl->dfitrddataen);
445 writel(readl(&pctl->tcwl) / 2 - 1, &pctl->dfitphywrlat);
446 writel(0, &pctl->trsth);
447 if (dramtype == LPDDR2) {
448 writel(0 << MDDR_LPDDR2_CLK_STOP_IDLE_SHIFT |
449 LPDDR2_S4 | LPDDR2_EN | burst_len |
450 (6 - 4) << TFAW_SHIFT | PD_EXIT_FAST |
451 1 << PD_TYPE_SHIFT | 0 << PD_IDLE_SHIFT,
452 &pctl->mcfg);
453 writel(0, &pctl->dfiodtcfg);
454 writel(0, &pctl->dfiodtcfg1);
455 } else {
456 writel(0 << MDDR_LPDDR2_CLK_STOP_IDLE_SHIFT |
457 LPDDR2_S4 | LPDDR3_EN | burst_len |
458 (6 - 4) << TFAW_SHIFT | PD_EXIT_FAST |
459 1 << PD_TYPE_SHIFT | 0 << PD_IDLE_SHIFT,
460 &pctl->mcfg);
461 writel((1 << 3) | (1 << 2), &pctl->dfiodtcfg);
462 writel((7 << 16) | 4, &pctl->dfiodtcfg1);
463 }
464 writel(bw | GRF_LPDDR2_3_EN, &grf->soc_con[0]);
465 }
466 setbits_le32(&pctl->scfg, 1);
467}
468
469static void phy_cfg(struct chan_info *chan,
470 struct rk322x_sdram_params *sdram_params)
471{
472 struct rk322x_ddr_phy *ddr_phy = chan->phy;
473 struct rk322x_service_sys *axi_bus = chan->msch;
474 struct rk322x_msch_timings *noc_timing = &sdram_params->base.noc_timing;
475 struct rk322x_phy_timing *phy_timing = &sdram_params->phy_timing;
476 struct rk322x_pctl_timing *pctl_timing = &sdram_params->pctl_timing;
477 u32 cmd_drv, clk_drv, dqs_drv, dqs_odt;
478
479 writel(noc_timing->ddrtiming, &axi_bus->ddrtiming);
480 writel(noc_timing->ddrmode, &axi_bus->ddrmode);
481 writel(noc_timing->readlatency, &axi_bus->readlatency);
482 writel(noc_timing->activate, &axi_bus->activate);
483 writel(noc_timing->devtodev, &axi_bus->devtodev);
484
485 switch (sdram_params->base.dramtype) {
486 case DDR3:
487 writel(PHY_DDR3 | phy_timing->bl, &ddr_phy->ddrphy_reg[1]);
488 break;
489 case LPDDR2:
490 writel(PHY_LPDDR2 | phy_timing->bl, &ddr_phy->ddrphy_reg[1]);
491 break;
492 default:
493 writel(PHY_LPDDR2 | phy_timing->bl, &ddr_phy->ddrphy_reg[1]);
494 break;
495 }
496
497 writel(phy_timing->cl_al, &ddr_phy->ddrphy_reg[0xb]);
498 writel(pctl_timing->tcwl, &ddr_phy->ddrphy_reg[0xc]);
499
500 cmd_drv = PHY_RON_RTT_34OHM;
501 clk_drv = PHY_RON_RTT_45OHM;
502 dqs_drv = PHY_RON_RTT_34OHM;
503 if (sdram_params->base.dramtype == LPDDR2)
504 dqs_odt = PHY_RON_RTT_DISABLE;
505 else
506 dqs_odt = PHY_RON_RTT_225OHM;
507
508 writel(cmd_drv, &ddr_phy->ddrphy_reg[0x11]);
509 clrsetbits_le32(&ddr_phy->ddrphy_reg[0x12], (0x1f << 3), cmd_drv << 3);
510 writel(clk_drv, &ddr_phy->ddrphy_reg[0x16]);
511 writel(clk_drv, &ddr_phy->ddrphy_reg[0x18]);
512
513 writel(dqs_drv, &ddr_phy->ddrphy_reg[0x20]);
514 writel(dqs_drv, &ddr_phy->ddrphy_reg[0x2f]);
515 writel(dqs_drv, &ddr_phy->ddrphy_reg[0x30]);
516 writel(dqs_drv, &ddr_phy->ddrphy_reg[0x3f]);
517 writel(dqs_drv, &ddr_phy->ddrphy_reg[0x40]);
518 writel(dqs_drv, &ddr_phy->ddrphy_reg[0x4f]);
519 writel(dqs_drv, &ddr_phy->ddrphy_reg[0x50]);
520 writel(dqs_drv, &ddr_phy->ddrphy_reg[0x5f]);
521
522 writel(dqs_odt, &ddr_phy->ddrphy_reg[0x21]);
523 writel(dqs_odt, &ddr_phy->ddrphy_reg[0x2e]);
524 writel(dqs_odt, &ddr_phy->ddrphy_reg[0x31]);
525 writel(dqs_odt, &ddr_phy->ddrphy_reg[0x3e]);
526 writel(dqs_odt, &ddr_phy->ddrphy_reg[0x41]);
527 writel(dqs_odt, &ddr_phy->ddrphy_reg[0x4e]);
528 writel(dqs_odt, &ddr_phy->ddrphy_reg[0x51]);
529 writel(dqs_odt, &ddr_phy->ddrphy_reg[0x5e]);
530}
531
532void dram_cfg_rbc(struct chan_info *chan,
533 struct rk322x_sdram_params *sdram_params)
534{
535 char noc_config;
536 int i = 0;
537 struct rk322x_sdram_channel *config = &sdram_params->ch[0];
538 struct rk322x_service_sys *axi_bus = chan->msch;
539
540 move_to_config_state(chan->pctl);
541
542 if ((config->rank == 2) && (config->cs1_row == config->cs0_row)) {
543 if ((config->col + config->bw) == 12) {
544 i = 14;
545 goto finish;
546 } else if ((config->col + config->bw) == 11) {
547 i = 15;
548 goto finish;
549 }
550 }
551 noc_config = ((config->cs0_row - 13) << 4) | ((config->bk - 2) << 2) |
552 (config->col + config->bw - 11);
553 for (i = 0; i < 11; i++) {
554 if (noc_config == ddr_cfg_2_rbc[i])
555 break;
556 }
557
558 if (i < 11)
559 goto finish;
560
561 noc_config = ((config->bk - 2) << 6) | ((config->cs0_row - 13) << 4) |
562 (config->col + config->bw - 11);
563
564 for (i = 11; i < 14; i++) {
565 if (noc_config == ddr_cfg_2_rbc[i])
566 break;
567 }
568 if (i < 14)
569 goto finish;
570 else
571 i = 0;
572
573finish:
574 writel(i, &axi_bus->ddrconf);
575 move_to_access_state(chan->pctl);
576}
577
578static void dram_all_config(const struct dram_info *dram,
579 struct rk322x_sdram_params *sdram_params)
580{
581 struct rk322x_sdram_channel *info = &sdram_params->ch[0];
582 u32 sys_reg = 0;
583
584 sys_reg |= sdram_params->base.dramtype << SYS_REG_DDRTYPE_SHIFT;
585 sys_reg |= (1 - 1) << SYS_REG_NUM_CH_SHIFT;
586 sys_reg |= info->row_3_4 << SYS_REG_ROW_3_4_SHIFT(0);
587 sys_reg |= 1 << SYS_REG_CHINFO_SHIFT(0);
588 sys_reg |= (info->rank - 1) << SYS_REG_RANK_SHIFT(0);
589 sys_reg |= (info->col - 9) << SYS_REG_COL_SHIFT(0);
590 sys_reg |= info->bk == 3 ? 0 : 1 << SYS_REG_BK_SHIFT(0);
591 sys_reg |= (info->cs0_row - 13) << SYS_REG_CS0_ROW_SHIFT(0);
592 sys_reg |= (info->cs1_row - 13) << SYS_REG_CS1_ROW_SHIFT(0);
593 sys_reg |= (2 >> info->bw) << SYS_REG_BW_SHIFT(0);
594 sys_reg |= (2 >> info->dbw) << SYS_REG_DBW_SHIFT(0);
595
596 writel(sys_reg, &dram->grf->os_reg[2]);
597}
598
599#define TEST_PATTEN 0x5aa5f00f
600
601static int dram_cap_detect(struct dram_info *dram,
602 struct rk322x_sdram_params *sdram_params)
603{
604 u32 bw, row, col, addr;
605 u32 ret = 0;
606 struct rk322x_service_sys *axi_bus = dram->chan[0].msch;
607
608 if (sdram_params->base.dramtype == DDR3)
609 sdram_params->ch[0].dbw = 1;
610 else
611 sdram_params->ch[0].dbw = 2;
612
613 move_to_config_state(dram->chan[0].pctl);
614 /* bw detect */
615 set_bw(dram, 2);
616 if (data_training(&dram->chan[0]) == 0) {
617 bw = 2;
618 } else {
619 bw = 1;
620 set_bw(dram, 1);
621 move_to_lowpower_state(dram->chan[0].pctl);
622 phy_softreset(dram);
623 move_to_config_state(dram->chan[0].pctl);
624 if (data_training(&dram->chan[0])) {
625 printf("BW detect error\n");
626 ret = -EINVAL;
627 }
628 }
629 sdram_params->ch[0].bw = bw;
630 sdram_params->ch[0].bk = 3;
631
632 if (bw == 2)
633 writel(6, &axi_bus->ddrconf);
634 else
635 writel(3, &axi_bus->ddrconf);
636 move_to_access_state(dram->chan[0].pctl);
637 for (col = 11; col >= 9; col--) {
aa6e94de
TR		 638 writel(0, CFG_SYS_SDRAM_BASE);
639 addr = CFG_SYS_SDRAM_BASE +
0176399b
KY		 640 (1 << (col + bw - 1));
641 writel(TEST_PATTEN, addr);
642 if ((readl(addr) == TEST_PATTEN) &&
aa6e94de 643 (readl(CFG_SYS_SDRAM_BASE) == 0))
0176399b
KY		 644 break;
645 }
646 if (col == 8) {
647 printf("Col detect error\n");
648 ret = -EINVAL;
649 goto out;
650 } else {
651 sdram_params->ch[0].col = col;
652 }
653
654 writel(10, &axi_bus->ddrconf);
655
656 /* Detect row*/
657 for (row = 16; row >= 12; row--) {
aa6e94de
TR		 658 writel(0, CFG_SYS_SDRAM_BASE);
659 addr = CFG_SYS_SDRAM_BASE + (1u << (row + 11 + 3 - 1));
0176399b
KY		 660 writel(TEST_PATTEN, addr);
661 if ((readl(addr) == TEST_PATTEN) &&
aa6e94de 662 (readl(CFG_SYS_SDRAM_BASE) == 0))
0176399b
KY		 663 break;
664 }
665 if (row == 11) {
666 printf("Row detect error\n");
667 ret = -EINVAL;
668 } else {
669 sdram_params->ch[0].cs1_row = row;
670 sdram_params->ch[0].row_3_4 = 0;
671 sdram_params->ch[0].cs0_row = row;
672 }
673 /* cs detect */
aa6e94de
TR		 674 writel(0, CFG_SYS_SDRAM_BASE);
675 writel(TEST_PATTEN, CFG_SYS_SDRAM_BASE + (1u << 30));
676 writel(~TEST_PATTEN, CFG_SYS_SDRAM_BASE + (1u << 30) + 4);
677 if ((readl(CFG_SYS_SDRAM_BASE + (1u << 30)) == TEST_PATTEN) &&
678 (readl(CFG_SYS_SDRAM_BASE) == 0))
0176399b
KY		 679 sdram_params->ch[0].rank = 2;
680 else
681 sdram_params->ch[0].rank = 1;
682out:
683 return ret;
684}
685
686static int sdram_init(struct dram_info *dram,
687 struct rk322x_sdram_params *sdram_params)
688{
689 int ret;
690
691 ret = clk_set_rate(&dram->ddr_clk,
692 sdram_params->base.ddr_freq * MHz * 2);
693 if (ret < 0) {
694 printf("Could not set DDR clock\n");
695 return ret;
696 }
697
698 phy_pctrl_reset(dram->cru, dram->chan[0].phy);
699 phy_dll_bypass_set(dram->chan[0].phy, sdram_params->base.ddr_freq);
700 pctl_cfg(dram->chan[0].pctl, sdram_params, dram->grf);
701 phy_cfg(&dram->chan[0], sdram_params);
702 writel(POWER_UP_START, &dram->chan[0].pctl->powctl);
703 while (!(readl(&dram->chan[0].pctl->powstat) & POWER_UP_DONE))
704 ;
705 memory_init(&dram->chan[0], sdram_params);
706 move_to_access_state(dram->chan[0].pctl);
707 ret = dram_cap_detect(dram, sdram_params);
708 if (ret)
709 goto out;
710 dram_cfg_rbc(&dram->chan[0], sdram_params);
711 dram_all_config(dram, sdram_params);
712out:
713 return ret;
714}
715
d1998a9f 716static int rk322x_dmc_of_to_plat(struct udevice *dev)
0176399b 717{
c69cda25 718 struct rk322x_sdram_params *params = dev_get_plat(dev);
0176399b
KY		 719 const void *blob = gd->fdt_blob;
720 int node = dev_of_offset(dev);
721 int ret;
722
dcfc42b1
SG		 723 if (!CONFIG_IS_ENABLED(OF_REAL))
724 return 0;
725
0176399b
KY		 726 params->num_channels = 1;
727
728 ret = fdtdec_get_int_array(blob, node, "rockchip,pctl-timing",
729 (u32 *)&params->pctl_timing,
730 sizeof(params->pctl_timing) / sizeof(u32));
731 if (ret) {
732 printf("%s: Cannot read rockchip,pctl-timing\n", __func__);
733 return -EINVAL;
734 }
735 ret = fdtdec_get_int_array(blob, node, "rockchip,phy-timing",
736 (u32 *)&params->phy_timing,
737 sizeof(params->phy_timing) / sizeof(u32));
738 if (ret) {
739 printf("%s: Cannot read rockchip,phy-timing\n", __func__);
740 return -EINVAL;
741 }
742 ret = fdtdec_get_int_array(blob, node, "rockchip,sdram-params",
743 (u32 *)&params->base,
744 sizeof(params->base) / sizeof(u32));
745 if (ret) {
746 printf("%s: Cannot read rockchip,sdram-params\n", __func__);
747 return -EINVAL;
748 }
d3581236 749 ret = regmap_init_mem(dev_ofnode(dev), &params->map);
0176399b
KY		 750 if (ret)
751 return ret;
0176399b
KY		 752
753 return 0;
754}
2f523787 755#endif /* CONFIG_TPL_BUILD */
0176399b
KY		 756
757#if CONFIG_IS_ENABLED(OF_PLATDATA)
8a8d24bd 758static int conv_of_plat(struct udevice *dev)
0176399b 759{
c69cda25 760 struct rk322x_sdram_params *plat = dev_get_plat(dev);
0176399b
KY		 761 struct dtd_rockchip_rk322x_dmc *of_plat = &plat->of_plat;
762 int ret;
763
764 memcpy(&plat->pctl_timing, of_plat->rockchip_pctl_timing,
765 sizeof(plat->pctl_timing));
766 memcpy(&plat->phy_timing, of_plat->rockchip_phy_timing,
767 sizeof(plat->phy_timing));
768 memcpy(&plat->base, of_plat->rockchip_sdram_params, sizeof(plat->base));
769
770 plat->num_channels = 1;
0fbb9696 771 ret = regmap_init_mem_plat(dev, of_plat->reg, sizeof(of_plat->reg[0]),
8a8d24bd 772 ARRAY_SIZE(of_plat->reg) / 2, &plat->map);
0176399b
KY		 773 if (ret)
774 return ret;
775
776 return 0;
777}
778#endif
779
780static int rk322x_dmc_probe(struct udevice *dev)
781{
2f523787 782#ifdef CONFIG_TPL_BUILD
c69cda25 783 struct rk322x_sdram_params *plat = dev_get_plat(dev);
0176399b
KY		 784 int ret;
785 struct udevice *dev_clk;
786#endif
787 struct dram_info *priv = dev_get_priv(dev);
788
789 priv->grf = syscon_get_first_range(ROCKCHIP_SYSCON_GRF);
2f523787 790#ifdef CONFIG_TPL_BUILD
0176399b 791#if CONFIG_IS_ENABLED(OF_PLATDATA)
8a8d24bd 792 ret = conv_of_plat(dev);
0176399b
KY		 793 if (ret)
794 return ret;
795#endif
796
797 priv->chan[0].msch = syscon_get_first_range(ROCKCHIP_SYSCON_MSCH);
798 priv->chan[0].pctl = regmap_get_range(plat->map, 0);
799 priv->chan[0].phy = regmap_get_range(plat->map, 1);
800 ret = rockchip_get_clk(&dev_clk);
801 if (ret)
802 return ret;
803 priv->ddr_clk.id = CLK_DDR;
804 ret = clk_request(dev_clk, &priv->ddr_clk);
805 if (ret)
806 return ret;
807
808 priv->cru = rockchip_get_cru();
809 if (IS_ERR(priv->cru))
810 return PTR_ERR(priv->cru);
811 ret = sdram_init(priv, plat);
812 if (ret)
813 return ret;
814#else
aa6e94de 815 priv->info.base = CFG_SYS_SDRAM_BASE;
0176399b
KY		 816 priv->info.size = rockchip_sdram_size(
817 (phys_addr_t)&priv->grf->os_reg[2]);
818#endif
819
820 return 0;
821}
822
823static int rk322x_dmc_get_info(struct udevice *dev, struct ram_info *info)
824{
825 struct dram_info *priv = dev_get_priv(dev);
826
827 *info = priv->info;
828
829 return 0;
830}
831
832static struct ram_ops rk322x_dmc_ops = {
833 .get_info = rk322x_dmc_get_info,
834};
835
836static const struct udevice_id rk322x_dmc_ids[] = {
837 { .compatible = "rockchip,rk3228-dmc" },
838 { }
839};
840
841U_BOOT_DRIVER(dmc_rk322x) = {
842 .name = "rockchip_rk322x_dmc",
843 .id = UCLASS_RAM,
844 .of_match = rk322x_dmc_ids,
845 .ops = &rk322x_dmc_ops,
2f523787 846#ifdef CONFIG_TPL_BUILD
d1998a9f 847 .of_to_plat = rk322x_dmc_of_to_plat,
0176399b
KY		 848#endif
849 .probe = rk322x_dmc_probe,
41575d8e 850 .priv_auto = sizeof(struct dram_info),
2f523787 851#ifdef CONFIG_TPL_BUILD
caa4daa2 852 .plat_auto = sizeof(struct rk322x_sdram_params),
0176399b
KY		 853#endif
854};
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