[J-u-boot.git] / drivers / pci / pcie_plda_common.h

/* SPDX-License-Identifier: GPL-2.0+ */
/*
 * Copyright (C) 2023 StarFive Technology Co., Ltd.
 * Author: Minda Chen <[email protected]>
 *
 */

#ifndef PCIE_PLDA_COMMON_H
#define PCIE_PLDA_COMMON_H

#define GEN_SETTINGS			0x80
#define PCIE_PCI_IDS			0x9C
#define PCIE_WINROM			0xFC
#define PMSG_SUPPORT_RX			0x3F0
#define PCI_MISC			0xB4

#define PLDA_EP_ENABLE			0
#define PLDA_RP_ENABLE			1

#define IDS_CLASS_CODE_SHIFT		8

#define PREF_MEM_WIN_64_SUPPORT		BIT(3)
#define PMSG_LTR_SUPPORT		BIT(2)
#define PLDA_FUNCTION_DIS		BIT(15)
#define PLDA_FUNC_NUM			4
#define PLDA_PHY_FUNC_SHIFT		9

#define XR3PCI_ATR_AXI4_SLV0		0x800
#define XR3PCI_ATR_SRC_ADDR_LOW		0x0
#define XR3PCI_ATR_SRC_ADDR_HIGH	0x4
#define XR3PCI_ATR_TRSL_ADDR_LOW	0x8
#define XR3PCI_ATR_TRSL_ADDR_HIGH	0xc
#define XR3PCI_ATR_TRSL_PARAM		0x10
#define XR3PCI_ATR_TABLE_OFFSET		0x20
#define XR3PCI_ATR_MAX_TABLE_NUM	8

#define XR3PCI_ATR_SRC_WIN_SIZE_SHIFT	1
#define XR3PCI_ATR_SRC_ADDR_MASK	GENMASK(31, 12)
#define XR3PCI_ATR_TRSL_ADDR_MASK	GENMASK(31, 12)
#define XR3PCI_ATR_TRSL_DIR		BIT(22)
/* IDs used in the XR3PCI_ATR_TRSL_PARAM */
#define XR3PCI_ATR_TRSLID_PCIE_MEMORY	0x0
#define XR3PCI_ATR_TRSLID_PCIE_CONFIG	0x1

/**
 * struct pcie_plda - PLDA PCIe controller state
 *
 * @reg_base: The base address of controller register space
 * @cfg_base: The base address of configuration space
 * @cfg_size: The size of configuration space
 * @sec_busno: Secondary bus number.
 * @atr_table_num: Total ATR table numbers.
 */
struct pcie_plda {
	struct udevice	*dev;
	void __iomem *reg_base;
	void __iomem *cfg_base;
	phys_size_t cfg_size;
	int sec_busno;
	int atr_table_num;
};

int plda_pcie_config_read(const struct udevice *udev, pci_dev_t bdf,
			  uint offset, ulong *valuep,
			  enum pci_size_t size);
int plda_pcie_config_write(struct udevice *udev, pci_dev_t bdf,
			   uint offset, ulong value,
			   enum pci_size_t size);
int plda_pcie_set_atr_entry(struct pcie_plda *plda, phys_addr_t src_addr,
			    phys_addr_t trsl_addr, phys_size_t window_size,
			    int trsl_param);

static inline void plda_pcie_enable_root_port(struct pcie_plda *plda)
{
	u32 value;

	value = readl(plda->reg_base + GEN_SETTINGS);
	value |= PLDA_RP_ENABLE;
	writel(value, plda->reg_base + GEN_SETTINGS);
}

static inline void plda_pcie_set_standard_class(struct pcie_plda *plda)
{
	u32 value;

	value = readl(plda->reg_base + PCIE_PCI_IDS);
	value &= 0xff;
	value |= (PCI_CLASS_BRIDGE_PCI_NORMAL << IDS_CLASS_CODE_SHIFT);
	writel(value, plda->reg_base + PCIE_PCI_IDS);
}

static inline void plda_pcie_set_pref_win_64bit(struct pcie_plda *plda)
{
	u32 value;

	value = readl(plda->reg_base + PCIE_WINROM);
	value |= PREF_MEM_WIN_64_SUPPORT;
	writel(value, plda->reg_base + PCIE_WINROM);
}

static inline void plda_pcie_disable_ltr(struct pcie_plda *plda)
{
	u32 value;

	value = readl(plda->reg_base + PMSG_SUPPORT_RX);
	value &= ~PMSG_LTR_SUPPORT;
	writel(value, plda->reg_base + PMSG_SUPPORT_RX);
}

static inline void plda_pcie_disable_func(struct pcie_plda *plda)
{
	u32 value;

	value = readl(plda->reg_base + PCI_MISC);
	value |= PLDA_FUNCTION_DIS;
	writel(value, plda->reg_base + PCI_MISC);
}
#endif
Commit	Line	Data
7870a055 MH	1	/* SPDX-License-Identifier: GPL-2.0+ */
	2	/*
	3	* Copyright (C) 2023 StarFive Technology Co., Ltd.
	4	* Author: Minda Chen <[email protected]>
	5	*
	6	*/
	7
	8	#ifndef PCIE_PLDA_COMMON_H
	9	#define PCIE_PLDA_COMMON_H
	10
	11	#define GEN_SETTINGS 0x80
	12	#define PCIE_PCI_IDS 0x9C
	13	#define PCIE_WINROM 0xFC
	14	#define PMSG_SUPPORT_RX 0x3F0
	15	#define PCI_MISC 0xB4
	16
	17	#define PLDA_EP_ENABLE 0
	18	#define PLDA_RP_ENABLE 1
	19
	20	#define IDS_CLASS_CODE_SHIFT 8
	21
	22	#define PREF_MEM_WIN_64_SUPPORT BIT(3)
	23	#define PMSG_LTR_SUPPORT BIT(2)
	24	#define PLDA_FUNCTION_DIS BIT(15)
	25	#define PLDA_FUNC_NUM 4
	26	#define PLDA_PHY_FUNC_SHIFT 9
	27
	28	#define XR3PCI_ATR_AXI4_SLV0 0x800
	29	#define XR3PCI_ATR_SRC_ADDR_LOW 0x0
	30	#define XR3PCI_ATR_SRC_ADDR_HIGH 0x4
	31	#define XR3PCI_ATR_TRSL_ADDR_LOW 0x8
	32	#define XR3PCI_ATR_TRSL_ADDR_HIGH 0xc
	33	#define XR3PCI_ATR_TRSL_PARAM 0x10
	34	#define XR3PCI_ATR_TABLE_OFFSET 0x20
	35	#define XR3PCI_ATR_MAX_TABLE_NUM 8
	36
	37	#define XR3PCI_ATR_SRC_WIN_SIZE_SHIFT 1
	38	#define XR3PCI_ATR_SRC_ADDR_MASK GENMASK(31, 12)
	39	#define XR3PCI_ATR_TRSL_ADDR_MASK GENMASK(31, 12)
	40	#define XR3PCI_ATR_TRSL_DIR BIT(22)
	41	/* IDs used in the XR3PCI_ATR_TRSL_PARAM */
	42	#define XR3PCI_ATR_TRSLID_PCIE_MEMORY 0x0
	43	#define XR3PCI_ATR_TRSLID_PCIE_CONFIG 0x1
	44
	45	/**
	46	* struct pcie_plda - PLDA PCIe controller state
	47	*
	48	* @reg_base: The base address of controller register space
	49	* @cfg_base: The base address of configuration space
	50	* @cfg_size: The size of configuration space
	51	* @sec_busno: Secondary bus number.
	52	* @atr_table_num: Total ATR table numbers.
	53	*/
	54	struct pcie_plda {
	55	struct udevice *dev;
	56	void __iomem *reg_base;
	57	void __iomem *cfg_base;
	58	phys_size_t cfg_size;
	59	int sec_busno;
	60	int atr_table_num;
	61	};
	62
	63	int plda_pcie_config_read(const struct udevice *udev, pci_dev_t bdf,
	64	uint offset, ulong *valuep,
65	enum pci_size_t size);
66	int plda_pcie_config_write(struct udevice *udev, pci_dev_t bdf,
67	uint offset, ulong value,
68	enum pci_size_t size);
69	int plda_pcie_set_atr_entry(struct pcie_plda *plda, phys_addr_t src_addr,
70	phys_addr_t trsl_addr, phys_size_t window_size,
71	int trsl_param);
72
73	static inline void plda_pcie_enable_root_port(struct pcie_plda *plda)
74	{
75	u32 value;
76
77	value = readl(plda->reg_base + GEN_SETTINGS);
78	value \|= PLDA_RP_ENABLE;
79	writel(value, plda->reg_base + GEN_SETTINGS);
80	}
81
82	static inline void plda_pcie_set_standard_class(struct pcie_plda *plda)
83	{
84	u32 value;
85
86	value = readl(plda->reg_base + PCIE_PCI_IDS);
87	value &= 0xff;
88	value \|= (PCI_CLASS_BRIDGE_PCI_NORMAL << IDS_CLASS_CODE_SHIFT);
89	writel(value, plda->reg_base + PCIE_PCI_IDS);
90	}
91
92	static inline void plda_pcie_set_pref_win_64bit(struct pcie_plda *plda)
93	{
94	u32 value;
95
96	value = readl(plda->reg_base + PCIE_WINROM);
97	value \|= PREF_MEM_WIN_64_SUPPORT;
98	writel(value, plda->reg_base + PCIE_WINROM);
99	}
100
101	static inline void plda_pcie_disable_ltr(struct pcie_plda *plda)
102	{
103	u32 value;
104
105	value = readl(plda->reg_base + PMSG_SUPPORT_RX);
106	value &= ~PMSG_LTR_SUPPORT;
107	writel(value, plda->reg_base + PMSG_SUPPORT_RX);
108	}
109
110	static inline void plda_pcie_disable_func(struct pcie_plda *plda)
111	{
112	u32 value;
113
114	value = readl(plda->reg_base + PCI_MISC);
115	value \|= PLDA_FUNCTION_DIS;
116	writel(value, plda->reg_base + PCI_MISC);
117	}
118	#endif