[J-u-boot.git] / drivers / pci / pcie_fsl.h

/* SPDX-License-Identifier: GPL-2.0+ */
/*
 * Copyright 2019 NXP
 *
 * PCIe DM U-Boot driver for Freescale PowerPC SoCs
 * Author: Hou Zhiqiang <[email protected]>
 */

#ifndef _PCIE_FSL_H_
#define _PCIE_FSL_H_

/* GPEX CSR */
#define CSR_CLASSCODE			0x474

#ifdef CONFIG_SYS_FSL_PCI_VER_3_X
#define FSL_PCIE_CAP_ID			0x70
#else
#define FSL_PCIE_CAP_ID			0x4c
#endif
/* PCIe Device Control Register */
#define PCI_DCR				(FSL_PCIE_CAP_ID + 0x08)
/* PCIe Device Status Register */
#define PCI_DSR				(FSL_PCIE_CAP_ID + 0x0a)
/* PCIe Link Control Register */
#define PCI_LCR				(FSL_PCIE_CAP_ID + 0x10)
/* PCIe Link Status Register */
#define PCI_LSR				(FSL_PCIE_CAP_ID + 0x12)

#define DBI_RO_WR_EN			0x8bc

#ifndef CFG_SYS_PCI_MEMORY_BUS
#define CFG_SYS_PCI_MEMORY_BUS	0
#endif

#ifndef CFG_SYS_PCI_MEMORY_PHYS
#define CFG_SYS_PCI_MEMORY_PHYS	0
#endif

#if defined(CONFIG_SYS_PCI_64BIT) && !defined(CFG_SYS_PCI64_MEMORY_BUS)
#define CFG_SYS_PCI64_MEMORY_BUS	(64ull * 1024 * 1024 * 1024)
#endif

#define PEX_CSR0_LTSSM_MASK		0xFC
#define PEX_CSR0_LTSSM_SHIFT		2
#define LTSSM_L0_REV3			0x11
#define LTSSM_L0			0x16

struct fsl_pcie_data {
	u32 block_offset;		/* Offset from CCSR of 1st controller */
	u32 block_offset_mask;		/* Mask out the CCSR base */
	u32 stride;			/* Offset stride between controllers */
};

struct fsl_pcie {
	int idx;
	struct udevice *bus;
	void __iomem *regs;
	u32 law_trgt_if;		/* LAW target ID */
	u32 block_rev;			/* IP block revision */
	bool mode;			/* RC&EP mode flag */
	bool enabled;			/* Enable status */
	struct list_head list;
	struct fsl_pcie_data *info;
};

extern struct list_head fsl_pcie_list;

#endif /* _PCIE_FSL_H_ */
Commit	Line	Data
b89e3d92 HZ	1	/* SPDX-License-Identifier: GPL-2.0+ */
	2	/*
	3	* Copyright 2019 NXP
	4	*
	5	* PCIe DM U-Boot driver for Freescale PowerPC SoCs
	6	* Author: Hou Zhiqiang <[email protected]>
	7	*/
	8
	9	#ifndef _PCIE_FSL_H_
	10	#define _PCIE_FSL_H_
	11
d18d06ac HZ	12	/* GPEX CSR */
	13	#define CSR_CLASSCODE 0x474
	14
b89e3d92 HZ	15	#ifdef CONFIG_SYS_FSL_PCI_VER_3_X
	16	#define FSL_PCIE_CAP_ID 0x70
	17	#else
	18	#define FSL_PCIE_CAP_ID 0x4c
	19	#endif
	20	/* PCIe Device Control Register */
	21	#define PCI_DCR (FSL_PCIE_CAP_ID + 0x08)
	22	/* PCIe Device Status Register */
	23	#define PCI_DSR (FSL_PCIE_CAP_ID + 0x0a)
	24	/* PCIe Link Control Register */
	25	#define PCI_LCR (FSL_PCIE_CAP_ID + 0x10)
	26	/* PCIe Link Status Register */
	27	#define PCI_LSR (FSL_PCIE_CAP_ID + 0x12)
	28
0205beb1 HZ	29	#define DBI_RO_WR_EN 0x8bc
0205beb1 HZ	30
ecc8d425 TR	31	#ifndef CFG_SYS_PCI_MEMORY_BUS
ecc8d425 TR	32	#define CFG_SYS_PCI_MEMORY_BUS 0
b89e3d92 HZ	33	#endif
b89e3d92 HZ	34
ecc8d425 TR	35	#ifndef CFG_SYS_PCI_MEMORY_PHYS
ecc8d425 TR	36	#define CFG_SYS_PCI_MEMORY_PHYS 0
b89e3d92 HZ	37	#endif
b89e3d92 HZ	38
ecc8d425 TR	39	#if defined(CONFIG_SYS_PCI_64BIT) && !defined(CFG_SYS_PCI64_MEMORY_BUS)
ecc8d425 TR	40	#define CFG_SYS_PCI64_MEMORY_BUS (64ull * 1024 * 1024 * 1024)
b89e3d92 HZ	41	#endif
	42
	43	#define PEX_CSR0_LTSSM_MASK 0xFC
	44	#define PEX_CSR0_LTSSM_SHIFT 2
	45	#define LTSSM_L0_REV3 0x11
	46	#define LTSSM_L0 0x16
	47
fbcb2ff5 HZ	48	struct fsl_pcie_data {
	49	u32 block_offset; /* Offset from CCSR of 1st controller */
	50	u32 block_offset_mask; /* Mask out the CCSR base */
	51	u32 stride; /* Offset stride between controllers */
	52	};
	53
b89e3d92 HZ	54	struct fsl_pcie {
	55	int idx;
	56	struct udevice *bus;
	57	void __iomem *regs;
	58	u32 law_trgt_if; /* LAW target ID */
	59	u32 block_rev; /* IP block revision */
	60	bool mode; /* RC&EP mode flag */
	61	bool enabled; /* Enable status */
	62	struct list_head list;
fbcb2ff5	63	struct fsl_pcie_data *info;
b89e3d92 HZ	64	};
	65
	66	extern struct list_head fsl_pcie_list;
	67
	68	#endif /* _PCIE_FSL_H_ */