[J-u-boot.git] / drivers / pci / pcie_dw_qcom.c

// SPDX-License-Identifier: GPL-2.0+

#include <clk.h>
#include <dm.h>
#include <generic-phy.h>
#include <pci.h>
#include <u-boot/crc.h>
#include <power-domain.h>
#include <reset.h>
#include <syscon.h>
#include <malloc.h>
#include <power/regulator.h>
#include <asm/global_data.h>
#include <asm/io.h>
#include <asm-generic/gpio.h>
#include <dm/device_compat.h>
#include <linux/iopoll.h>
#include <linux/delay.h>
#include <linux/log2.h>
#include <linux/bitfield.h>

#include "pcie_dw_common.h"

DECLARE_GLOBAL_DATA_PTR;

struct qcom_pcie;

struct qcom_pcie_ops {
	int (*config_sid)(struct qcom_pcie *priv);
};

#define NUM_SUPPLIES	2

struct qcom_pcie {
	/* Must be first member of the struct */
	struct pcie_dw dw;
	void *parf;
	struct phy phy;
	struct reset_ctl_bulk rsts;
	struct clk_bulk clks;
	struct gpio_desc rst_gpio;
	struct qcom_pcie_ops *ops;
	struct udevice *vregs[NUM_SUPPLIES];
};

/* PARF registers */
#define PARF_SYS_CTRL				0x00
#define PARF_PM_CTRL				0x20
#define PARF_PCS_DEEMPH				0x34
#define PARF_PCS_SWING				0x38
#define PARF_PHY_CTRL				0x40
#define PARF_PHY_REFCLK				0x4c
#define PARF_CONFIG_BITS			0x50
#define PARF_DBI_BASE_ADDR			0x168
#define PARF_MHI_CLOCK_RESET_CTRL		0x174
#define PARF_AXI_MSTR_WR_ADDR_HALT		0x178
#define PARF_AXI_MSTR_WR_ADDR_HALT_V2		0x1a8
#define PARF_Q2A_FLUSH				0x1ac
#define PARF_LTSSM				0x1b0
#define PARF_SID_OFFSET				0x234
#define PARF_BDF_TRANSLATE_CFG			0x24c
#define PARF_SLV_ADDR_SPACE_SIZE		0x358
#define PARF_DEVICE_TYPE			0x1000
#define PARF_BDF_TO_SID_TABLE_N			0x2000

/* ELBI registers */
#define ELBI_SYS_CTRL				0x04

/* DBI registers */
#define AXI_MSTR_RESP_COMP_CTRL0		0x818
#define AXI_MSTR_RESP_COMP_CTRL1		0x81c
#define MISC_CONTROL_1_REG			0x8bc

/* MHI registers */
#define PARF_DEBUG_CNT_PM_LINKST_IN_L2		0xc04
#define PARF_DEBUG_CNT_PM_LINKST_IN_L1		0xc0c
#define PARF_DEBUG_CNT_PM_LINKST_IN_L0S		0xc10
#define PARF_DEBUG_CNT_AUX_CLK_IN_L1SUB_L1	0xc84
#define PARF_DEBUG_CNT_AUX_CLK_IN_L1SUB_L2	0xc88

/* PARF_SYS_CTRL register fields */
#define MAC_PHY_POWERDOWN_IN_P2_D_MUX_EN	BIT(29)
#define MST_WAKEUP_EN				BIT(13)
#define SLV_WAKEUP_EN				BIT(12)
#define MSTR_ACLK_CGC_DIS			BIT(10)
#define SLV_ACLK_CGC_DIS			BIT(9)
#define CORE_CLK_CGC_DIS			BIT(6)
#define AUX_PWR_DET				BIT(4)
#define L23_CLK_RMV_DIS				BIT(2)
#define L1_CLK_RMV_DIS				BIT(1)

/* PARF_PM_CTRL register fields */
#define REQ_NOT_ENTR_L1				BIT(5)

/* PARF_PCS_DEEMPH register fields */
#define PCS_DEEMPH_TX_DEEMPH_GEN1(x)		FIELD_PREP(GENMASK(21, 16), x)
#define PCS_DEEMPH_TX_DEEMPH_GEN2_3_5DB(x)	FIELD_PREP(GENMASK(13, 8), x)
#define PCS_DEEMPH_TX_DEEMPH_GEN2_6DB(x)	FIELD_PREP(GENMASK(5, 0), x)

/* PARF_PCS_SWING register fields */
#define PCS_SWING_TX_SWING_FULL(x)		FIELD_PREP(GENMASK(14, 8), x)
#define PCS_SWING_TX_SWING_LOW(x)		FIELD_PREP(GENMASK(6, 0), x)

/* PARF_PHY_CTRL register fields */
#define PHY_CTRL_PHY_TX0_TERM_OFFSET_MASK	GENMASK(20, 16)
#define PHY_CTRL_PHY_TX0_TERM_OFFSET(x)		FIELD_PREP(PHY_CTRL_PHY_TX0_TERM_OFFSET_MASK, x)
#define PHY_TEST_PWR_DOWN			BIT(0)

/* PARF_PHY_REFCLK register fields */
#define PHY_REFCLK_SSP_EN			BIT(16)
#define PHY_REFCLK_USE_PAD			BIT(12)

/* PARF_CONFIG_BITS register fields */
#define PHY_RX0_EQ(x)				FIELD_PREP(GENMASK(26, 24), x)

/* PARF_SLV_ADDR_SPACE_SIZE register value */
#define SLV_ADDR_SPACE_SZ			0x10000000

/* PARF_MHI_CLOCK_RESET_CTRL register fields */
#define AHB_CLK_EN				BIT(0)
#define MSTR_AXI_CLK_EN				BIT(1)
#define BYPASS					BIT(4)

/* PARF_AXI_MSTR_WR_ADDR_HALT register fields */
#define EN					BIT(31)

/* PARF_LTSSM register fields */
#define LTSSM_EN				BIT(8)

/* PARF_DEVICE_TYPE register fields */
#define DEVICE_TYPE_RC				0x4

/* ELBI_SYS_CTRL register fields */
#define ELBI_SYS_CTRL_LT_ENABLE			BIT(0)

/* AXI_MSTR_RESP_COMP_CTRL0 register fields */
#define CFG_REMOTE_RD_REQ_BRIDGE_SIZE_2K	0x4
#define CFG_REMOTE_RD_REQ_BRIDGE_SIZE_4K	0x5

/* AXI_MSTR_RESP_COMP_CTRL1 register fields */
#define CFG_BRIDGE_SB_INIT			BIT(0)

/* MISC_CONTROL_1_REG register fields */
#define DBI_RO_WR_EN				1

/* PCI_EXP_SLTCAP register fields */
#define PCIE_CAP_SLOT_POWER_LIMIT_VAL		FIELD_PREP(PCI_EXP_SLTCAP_SPLV, 250)
#define PCIE_CAP_SLOT_POWER_LIMIT_SCALE		FIELD_PREP(PCI_EXP_SLTCAP_SPLS, 1)
#define PCIE_CAP_SLOT_VAL			(PCI_EXP_SLTCAP_ABP | \
						PCI_EXP_SLTCAP_PCP | \
						PCI_EXP_SLTCAP_MRLSP | \
						PCI_EXP_SLTCAP_AIP | \
						PCI_EXP_SLTCAP_PIP | \
						PCI_EXP_SLTCAP_HPS | \
						PCI_EXP_SLTCAP_HPC | \
						PCI_EXP_SLTCAP_EIP | \
						PCIE_CAP_SLOT_POWER_LIMIT_VAL | \
						PCIE_CAP_SLOT_POWER_LIMIT_SCALE)

#define PERST_DELAY_US				1000

#define LINK_WAIT_MAX_RETRIES			10
#define LINK_WAIT_USLEEP			100000

#define QCOM_PCIE_CRC8_POLYNOMIAL		(BIT(2) | BIT(1) | BIT(0))

#define CRC8_TABLE_SIZE				256

static bool qcom_pcie_wait_link_up(struct qcom_pcie *priv)
{
	u8 offset = pcie_dw_find_capability(&priv->dw, PCI_CAP_ID_EXP);
	unsigned int cnt = 0;
	u16 val;

	do {
		val = readw(priv->dw.dbi_base + offset + PCI_EXP_LNKSTA);

		if ((val & PCI_EXP_LNKSTA_DLLLA))
			return true;
		cnt++;

		udelay(LINK_WAIT_USLEEP);
	} while (cnt < LINK_WAIT_MAX_RETRIES);

	return false;
}

static void qcom_pcie_clear_aspm_l0s(struct qcom_pcie *priv)
{
	u8 offset = pcie_dw_find_capability(&priv->dw, PCI_CAP_ID_EXP);
	u32 val;

	dw_pcie_dbi_write_enable(&priv->dw, true);

	val = readl(priv->dw.dbi_base + offset + PCI_EXP_LNKCAP);
	val &= ~PCI_EXP_LNKCAP_ASPM_L0S;
	writel(val, priv->dw.dbi_base + offset + PCI_EXP_LNKCAP);

	dw_pcie_dbi_write_enable(&priv->dw, false);
}

static void qcom_pcie_clear_hpc(struct qcom_pcie *priv)
{
	u8 offset = pcie_dw_find_capability(&priv->dw, PCI_CAP_ID_EXP);
	u32 val;

	dw_pcie_dbi_write_enable(&priv->dw, true);

	val = readl(priv->dw.dbi_base + offset + PCI_EXP_SLTCAP);
	val &= ~PCI_EXP_SLTCAP_HPC;
	writel(val, priv->dw.dbi_base + offset + PCI_EXP_SLTCAP);

	dw_pcie_dbi_write_enable(&priv->dw, false);
}

static void qcom_pcie_set_lanes(struct qcom_pcie *priv, unsigned int lanes)
{
	u8 offset = pcie_dw_find_capability(&priv->dw, PCI_CAP_ID_EXP);
	u32 val;

	val = readl(priv->dw.dbi_base + offset + PCI_EXP_LNKCAP);
	val &= ~PCI_EXP_LNKCAP_MLW;
	val |= FIELD_PREP(PCI_EXP_LNKCAP_MLW, lanes);
	writel(val, priv->dw.dbi_base + offset + PCI_EXP_LNKCAP);
}

static int qcom_pcie_config_sid_1_9_0(struct qcom_pcie *priv)
{
	/* iommu map structure */
	struct {
		u32 bdf;
		u32 phandle;
		u32 smmu_sid;
		u32 smmu_sid_len;
	} *map;
	void *bdf_to_sid_base = priv->parf + PARF_BDF_TO_SID_TABLE_N;
	int i, nr_map, size = 0;
	u32 smmu_sid_base;

	dev_read_prop(priv->dw.dev, "iommu-map", &size);
	if (!size)
		return 0;

	map = malloc(size);
	if (!map)
		return -ENOMEM;

	dev_read_u32_array(priv->dw.dev, "iommu-map", (u32 *)map, size / sizeof(u32));

	nr_map = size / (sizeof(*map));

	/* Registers need to be zero out first */
	memset_io(bdf_to_sid_base, 0, CRC8_TABLE_SIZE * sizeof(u32));

	/* Extract the SMMU SID base from the first entry of iommu-map */
	smmu_sid_base = map[0].smmu_sid;

	/* Look for an available entry to hold the mapping */
	for (i = 0; i < nr_map; i++) {
		__be16 bdf_be = cpu_to_be16(map[i].bdf);
		u32 val;
		u8 hash;

		hash = crc8(QCOM_PCIE_CRC8_POLYNOMIAL, (u8 *)&bdf_be, sizeof(bdf_be));

		val = readl(bdf_to_sid_base + hash * sizeof(u32));

		/* If the register is already populated, look for next available entry */
		while (val) {
			u8 current_hash = hash++;
			u8 next_mask = 0xff;

			/* If NEXT field is NULL then update it with next hash */
			if (!(val & next_mask)) {
				val |= (u32)hash;
				writel(val, bdf_to_sid_base + current_hash * sizeof(u32));
			}

			val = readl(bdf_to_sid_base + hash * sizeof(u32));
		}

		/* BDF [31:16] | SID [15:8] | NEXT [7:0] */
		val = map[i].bdf << 16 | (map[i].smmu_sid - smmu_sid_base) << 8 | 0;
		writel(val, bdf_to_sid_base + hash * sizeof(u32));
	}

	free(map);

	return 0;
}

static void qcom_pcie_configure(struct qcom_pcie *priv)
{
	u32 val;

	dw_pcie_dbi_write_enable(&priv->dw, true);

	val = readl(priv->dw.dbi_base + PCIE_PORT_LINK_CONTROL);
	val &= ~PORT_LINK_FAST_LINK_MODE;
	val |= PORT_LINK_DLL_LINK_EN;
	val &= ~PORT_LINK_MODE_MASK;
	val |= PORT_LINK_MODE_2_LANES;
	writel(val, priv->dw.dbi_base + PCIE_PORT_LINK_CONTROL);

	val = readl(priv->dw.dbi_base + PCIE_LINK_WIDTH_SPEED_CONTROL);
	val &= ~PORT_LOGIC_LINK_WIDTH_MASK;
	val |= PORT_LOGIC_LINK_WIDTH_2_LANES;
	writel(val, priv->dw.dbi_base + PCIE_LINK_WIDTH_SPEED_CONTROL);

	qcom_pcie_set_lanes(priv, 2);

	dw_pcie_dbi_write_enable(&priv->dw, false);
}

static int qcom_pcie_init_port(struct udevice *dev)
{
	struct qcom_pcie *priv = dev_get_priv(dev);
	int vreg, ret;
	u32 val;

	dm_gpio_set_value(&priv->rst_gpio, 1);
	udelay(PERST_DELAY_US);

	ret = generic_phy_init(&priv->phy);
	if (ret) {
		dev_err(dev, "failed to init phy (%d)\n", ret);
		return ret;
	}

	udelay(PERST_DELAY_US);

	for (vreg = 0; vreg < NUM_SUPPLIES; ++vreg) {
		ret = regulator_set_enable(priv->vregs[vreg], true);
		if (ret && ret != -ENOSYS)
			dev_warn(dev, "failed to enable regulator %d (%d)\n", vreg, ret);
	}

	ret = clk_enable_bulk(&priv->clks);
	if (ret) {
		dev_err(dev, "failed to enable clocks (%d)\n", ret);
		goto err_power_off_phy;
	}

	ret = reset_assert_bulk(&priv->rsts);
	if (ret) {
		dev_err(dev, "failed to assert resets (%d)\n", ret);
		goto err_disable_clks;
	}

	udelay(PERST_DELAY_US);

	ret = reset_deassert_bulk(&priv->rsts);
	if (ret) {
		dev_err(dev, "failed to deassert resets (%d)\n", ret);
		goto err_power_off_phy;
	}

	udelay(PERST_DELAY_US);

	/* configure PCIe to RC mode */
	writel(DEVICE_TYPE_RC, priv->parf + PARF_DEVICE_TYPE);

	/* enable PCIe clocks and resets */
	val = readl(priv->parf + PARF_PHY_CTRL);
	val &= ~PHY_TEST_PWR_DOWN;
	writel(val, priv->parf + PARF_PHY_CTRL);

	/* change DBI base address */
	writel(0, priv->parf + PARF_DBI_BASE_ADDR);

	/* MAC PHY_POWERDOWN MUX DISABLE  */
	val = readl(priv->parf + PARF_SYS_CTRL);
	val &= ~MAC_PHY_POWERDOWN_IN_P2_D_MUX_EN;
	writel(val, priv->parf + PARF_SYS_CTRL);

	val = readl(priv->parf + PARF_MHI_CLOCK_RESET_CTRL);
	val |= BYPASS;
	writel(val, priv->parf + PARF_MHI_CLOCK_RESET_CTRL);

	/* Enable L1 and L1SS */
	val = readl(priv->parf + PARF_PM_CTRL);
	val &= ~REQ_NOT_ENTR_L1;
	writel(val, priv->parf + PARF_PM_CTRL);

	val = readl(priv->parf + PARF_AXI_MSTR_WR_ADDR_HALT_V2);
	val |= EN;
	writel(val, priv->parf + PARF_AXI_MSTR_WR_ADDR_HALT_V2);

	ret = generic_phy_power_on(&priv->phy);
	if (ret) {
		dev_err(dev, "failed to power on phy (%d)\n", ret);
		goto err_exit_phy;
	}

	qcom_pcie_clear_aspm_l0s(priv);
	qcom_pcie_clear_hpc(priv);

	mdelay(100);
	dm_gpio_set_value(&priv->rst_gpio, 0);
	udelay(PERST_DELAY_US);

	if (priv->ops && priv->ops->config_sid) {
		ret = priv->ops->config_sid(priv);
		if (ret)
			goto err_deassert_bulk;
	}

	qcom_pcie_configure(priv);

	pcie_dw_setup_host(&priv->dw);

	/* enable link training */
	val = readl(priv->parf + PARF_LTSSM);
	val |= LTSSM_EN;
	writel(val, priv->parf + PARF_LTSSM);

	return 0;
err_deassert_bulk:
	reset_assert_bulk(&priv->rsts);
err_disable_clks:
	clk_disable_bulk(&priv->clks);
err_power_off_phy:
	generic_phy_power_off(&priv->phy);
err_exit_phy:
	generic_phy_exit(&priv->phy);

	return ret;
}

static const char *qcom_pcie_vregs[NUM_SUPPLIES] = {
	"vdda-supply",
	"vddpe-3v3-supply",
};

static int qcom_pcie_parse_dt(struct udevice *dev)
{
	struct qcom_pcie *priv = dev_get_priv(dev);
	int vreg, ret;

	priv->dw.dbi_base = dev_read_addr_name_ptr(dev, "dbi");
	if (!priv->dw.dbi_base)
		return -EINVAL;

	dev_dbg(dev, "DBI address is 0x%p\n", priv->dw.dbi_base);

	priv->dw.atu_base = dev_read_addr_name_ptr(dev, "atu");
	if (!priv->dw.atu_base)
		return -EINVAL;

	dev_dbg(dev, "ATU address is 0x%p\n", priv->dw.atu_base);

	priv->parf = dev_read_addr_name_ptr(dev, "parf");
	if (!priv->parf)
		return -EINVAL;

	dev_dbg(dev, "PARF address is 0x%p\n", priv->parf);

	ret = gpio_request_by_name(dev, "perst-gpios", 0,
				   &priv->rst_gpio, GPIOD_IS_OUT);
	if (ret) {
		dev_err(dev, "failed to find reset-gpios property\n");
		return ret;
	}

	ret = reset_get_bulk(dev, &priv->rsts);
	if (ret) {
		dev_err(dev, "failed to get resets (%d)\n", ret);
		return ret;
	}

	ret = clk_get_bulk(dev, &priv->clks);
	if (ret) {
		dev_err(dev, "failed to get clocks (%d)\n", ret);
		return ret;
	}

	ret = generic_phy_get_by_index(dev, 0, &priv->phy);
	if (ret) {
		dev_err(dev, "failed to get pcie phy (%d)\n", ret);
		return ret;
	}

	for (vreg = 0; vreg < NUM_SUPPLIES; ++vreg) {
		ret = device_get_supply_regulator(dev, qcom_pcie_vregs[vreg], &priv->vregs[vreg]);
		if (ret)
			dev_warn(dev, "failed to get regulator %d (%d)\n", vreg, ret);
	}

	return 0;
}

/**
 * qcom_pcie_probe() - Probe the PCIe bus for active link
 *
 * @dev: A pointer to the device being operated on
 *
 * Probe for an active link on the PCIe bus and configure the controller
 * to enable this port.
 *
 * Return: 0 on success, else -ENODEV
 */
static int qcom_pcie_probe(struct udevice *dev)
{
	struct qcom_pcie *priv = dev_get_priv(dev);
	struct udevice *ctlr = pci_get_controller(dev);
	struct pci_controller *hose = dev_get_uclass_priv(ctlr);
	int ret = 0;

	priv->dw.first_busno = dev_seq(dev);
	priv->dw.dev = dev;

	ret = qcom_pcie_parse_dt(dev);
	if (ret)
		return ret;

	ret = qcom_pcie_init_port(dev);
	if (ret) {
		dm_gpio_free(dev, &priv->rst_gpio);
		return ret;
	}

	if (qcom_pcie_wait_link_up(priv))
		printf("PCIE-%d: Link up (Gen%d-x%d, Bus%d)\n",
		       dev_seq(dev), pcie_dw_get_link_speed(&priv->dw),
		       pcie_dw_get_link_width(&priv->dw),
		       hose->first_busno);
	else
		printf("PCIE-%d: Link up timeout\n", dev_seq(dev));

	return pcie_dw_prog_outbound_atu_unroll(&priv->dw,
						PCIE_ATU_REGION_INDEX0,
						PCIE_ATU_TYPE_MEM,
						priv->dw.mem.phys_start,
						priv->dw.mem.bus_start,
						priv->dw.mem.size);
}

static const struct dm_pci_ops qcom_pcie_ops = {
	.read_config	= pcie_dw_read_config,
	.write_config	= pcie_dw_write_config,
};

static const struct qcom_pcie_ops ops_1_9_0 = {
	.config_sid = qcom_pcie_config_sid_1_9_0,
};

static const struct udevice_id qcom_pcie_ids[] = {
	{ .compatible = "qcom,pcie-sa8540p", .data = (ulong)&ops_1_9_0 },
	{ .compatible = "qcom,pcie-sc7280", .data = (ulong)&ops_1_9_0 },
	{ .compatible = "qcom,pcie-sc8180x", .data = (ulong)&ops_1_9_0 },
	{ .compatible = "qcom,pcie-sc8280xp", .data = (ulong)&ops_1_9_0 },
	{ .compatible = "qcom,pcie-sdm845" },
	{ .compatible = "qcom,pcie-sdx55", .data = (ulong)&ops_1_9_0 },
	{ .compatible = "qcom,pcie-sm8150", .data = (ulong)&ops_1_9_0 },
	{ .compatible = "qcom,pcie-sm8250", .data = (ulong)&ops_1_9_0 },
	{ .compatible = "qcom,pcie-sm8350", .data = (ulong)&ops_1_9_0 },
	{ .compatible = "qcom,pcie-sm8450-pcie0", .data = (ulong)&ops_1_9_0 },
	{ .compatible = "qcom,pcie-sm8450-pcie1", .data = (ulong)&ops_1_9_0 },
	{ .compatible = "qcom,pcie-sm8550", .data = (ulong)&ops_1_9_0 },
	{ .compatible = "qcom,pcie-x1e80100", .data = (ulong)&ops_1_9_0 },
	{ }
};

U_BOOT_DRIVER(qcom_dw_pcie) = {
	.name			= "pcie_dw_qcom",
	.id			= UCLASS_PCI,
	.of_match		= qcom_pcie_ids,
	.ops			= &qcom_pcie_ops,
	.probe			= qcom_pcie_probe,
	.priv_auto		= sizeof(struct qcom_pcie),
};
Commit	Line	Data
5b7ec7fb NA	1	// SPDX-License-Identifier: GPL-2.0+
	2
	3	#include <clk.h>
	4	#include <dm.h>
	5	#include <generic-phy.h>
	6	#include <pci.h>
	7	#include <u-boot/crc.h>
	8	#include <power-domain.h>
	9	#include <reset.h>
	10	#include <syscon.h>
	11	#include <malloc.h>
	12	#include <power/regulator.h>
	13	#include <asm/global_data.h>
	14	#include <asm/io.h>
	15	#include <asm-generic/gpio.h>
	16	#include <dm/device_compat.h>
	17	#include <linux/iopoll.h>
	18	#include <linux/delay.h>
	19	#include <linux/log2.h>
	20	#include <linux/bitfield.h>
	21
	22	#include "pcie_dw_common.h"
	23
	24	DECLARE_GLOBAL_DATA_PTR;
	25
	26	struct qcom_pcie;
	27
	28	struct qcom_pcie_ops {
	29	int (config_sid)(struct qcom_pcie priv);
	30	};
	31
	32	#define NUM_SUPPLIES 2
	33
	34	struct qcom_pcie {
	35	/* Must be first member of the struct */
	36	struct pcie_dw dw;
	37	void *parf;
	38	struct phy phy;
	39	struct reset_ctl_bulk rsts;
	40	struct clk_bulk clks;
	41	struct gpio_desc rst_gpio;
	42	struct qcom_pcie_ops *ops;
	43	struct udevice *vregs[NUM_SUPPLIES];
	44	};
	45
	46	/* PARF registers */
	47	#define PARF_SYS_CTRL 0x00
	48	#define PARF_PM_CTRL 0x20
	49	#define PARF_PCS_DEEMPH 0x34
	50	#define PARF_PCS_SWING 0x38
	51	#define PARF_PHY_CTRL 0x40
	52	#define PARF_PHY_REFCLK 0x4c
	53	#define PARF_CONFIG_BITS 0x50
	54	#define PARF_DBI_BASE_ADDR 0x168
	55	#define PARF_MHI_CLOCK_RESET_CTRL 0x174
	56	#define PARF_AXI_MSTR_WR_ADDR_HALT 0x178
	57	#define PARF_AXI_MSTR_WR_ADDR_HALT_V2 0x1a8
	58	#define PARF_Q2A_FLUSH 0x1ac
	59	#define PARF_LTSSM 0x1b0
	60	#define PARF_SID_OFFSET 0x234
	61	#define PARF_BDF_TRANSLATE_CFG 0x24c
	62	#define PARF_SLV_ADDR_SPACE_SIZE 0x358
	63	#define PARF_DEVICE_TYPE 0x1000
	64	#define PARF_BDF_TO_SID_TABLE_N 0x2000
65
66	/* ELBI registers */
67	#define ELBI_SYS_CTRL 0x04
68
69	/* DBI registers */
70	#define AXI_MSTR_RESP_COMP_CTRL0 0x818
71	#define AXI_MSTR_RESP_COMP_CTRL1 0x81c
72	#define MISC_CONTROL_1_REG 0x8bc
73
74	/* MHI registers */
75	#define PARF_DEBUG_CNT_PM_LINKST_IN_L2 0xc04
76	#define PARF_DEBUG_CNT_PM_LINKST_IN_L1 0xc0c
77	#define PARF_DEBUG_CNT_PM_LINKST_IN_L0S 0xc10
78	#define PARF_DEBUG_CNT_AUX_CLK_IN_L1SUB_L1 0xc84
79	#define PARF_DEBUG_CNT_AUX_CLK_IN_L1SUB_L2 0xc88
80
81	/* PARF_SYS_CTRL register fields */
82	#define MAC_PHY_POWERDOWN_IN_P2_D_MUX_EN BIT(29)
83	#define MST_WAKEUP_EN BIT(13)
84	#define SLV_WAKEUP_EN BIT(12)
85	#define MSTR_ACLK_CGC_DIS BIT(10)
86	#define SLV_ACLK_CGC_DIS BIT(9)
87	#define CORE_CLK_CGC_DIS BIT(6)
88	#define AUX_PWR_DET BIT(4)
89	#define L23_CLK_RMV_DIS BIT(2)
90	#define L1_CLK_RMV_DIS BIT(1)
91
92	/* PARF_PM_CTRL register fields */
93	#define REQ_NOT_ENTR_L1 BIT(5)
94
95	/* PARF_PCS_DEEMPH register fields */
96	#define PCS_DEEMPH_TX_DEEMPH_GEN1(x) FIELD_PREP(GENMASK(21, 16), x)
97	#define PCS_DEEMPH_TX_DEEMPH_GEN2_3_5DB(x) FIELD_PREP(GENMASK(13, 8), x)
98	#define PCS_DEEMPH_TX_DEEMPH_GEN2_6DB(x) FIELD_PREP(GENMASK(5, 0), x)
99
100	/* PARF_PCS_SWING register fields */
101	#define PCS_SWING_TX_SWING_FULL(x) FIELD_PREP(GENMASK(14, 8), x)
102	#define PCS_SWING_TX_SWING_LOW(x) FIELD_PREP(GENMASK(6, 0), x)
103
104	/* PARF_PHY_CTRL register fields */
105	#define PHY_CTRL_PHY_TX0_TERM_OFFSET_MASK GENMASK(20, 16)
106	#define PHY_CTRL_PHY_TX0_TERM_OFFSET(x) FIELD_PREP(PHY_CTRL_PHY_TX0_TERM_OFFSET_MASK, x)
107	#define PHY_TEST_PWR_DOWN BIT(0)
108
109	/* PARF_PHY_REFCLK register fields */
110	#define PHY_REFCLK_SSP_EN BIT(16)
111	#define PHY_REFCLK_USE_PAD BIT(12)
112
113	/* PARF_CONFIG_BITS register fields */
114	#define PHY_RX0_EQ(x) FIELD_PREP(GENMASK(26, 24), x)
115
116	/* PARF_SLV_ADDR_SPACE_SIZE register value */
117	#define SLV_ADDR_SPACE_SZ 0x10000000
118
119	/* PARF_MHI_CLOCK_RESET_CTRL register fields */
120	#define AHB_CLK_EN BIT(0)
121	#define MSTR_AXI_CLK_EN BIT(1)
122	#define BYPASS BIT(4)
123
124	/* PARF_AXI_MSTR_WR_ADDR_HALT register fields */
125	#define EN BIT(31)
126
127	/* PARF_LTSSM register fields */
128	#define LTSSM_EN BIT(8)
129
130	/* PARF_DEVICE_TYPE register fields */
131	#define DEVICE_TYPE_RC 0x4
132
133	/* ELBI_SYS_CTRL register fields */
134	#define ELBI_SYS_CTRL_LT_ENABLE BIT(0)
135
136	/* AXI_MSTR_RESP_COMP_CTRL0 register fields */
137	#define CFG_REMOTE_RD_REQ_BRIDGE_SIZE_2K 0x4
138	#define CFG_REMOTE_RD_REQ_BRIDGE_SIZE_4K 0x5
139
140	/* AXI_MSTR_RESP_COMP_CTRL1 register fields */
141	#define CFG_BRIDGE_SB_INIT BIT(0)
142
143	/* MISC_CONTROL_1_REG register fields */
144	#define DBI_RO_WR_EN 1
145
146	/* PCI_EXP_SLTCAP register fields */
147	#define PCIE_CAP_SLOT_POWER_LIMIT_VAL FIELD_PREP(PCI_EXP_SLTCAP_SPLV, 250)
148	#define PCIE_CAP_SLOT_POWER_LIMIT_SCALE FIELD_PREP(PCI_EXP_SLTCAP_SPLS, 1)
149	#define PCIE_CAP_SLOT_VAL (PCI_EXP_SLTCAP_ABP \| \
150	PCI_EXP_SLTCAP_PCP \| \
151	PCI_EXP_SLTCAP_MRLSP \| \
152	PCI_EXP_SLTCAP_AIP \| \
153	PCI_EXP_SLTCAP_PIP \| \
154	PCI_EXP_SLTCAP_HPS \| \
155	PCI_EXP_SLTCAP_HPC \| \
156	PCI_EXP_SLTCAP_EIP \| \
157	PCIE_CAP_SLOT_POWER_LIMIT_VAL \| \
158	PCIE_CAP_SLOT_POWER_LIMIT_SCALE)
159
160	#define PERST_DELAY_US 1000
161
162	#define LINK_WAIT_MAX_RETRIES 10
163	#define LINK_WAIT_USLEEP 100000
164
165	#define QCOM_PCIE_CRC8_POLYNOMIAL (BIT(2) \| BIT(1) \| BIT(0))
166
167	#define CRC8_TABLE_SIZE 256
168
169	static bool qcom_pcie_wait_link_up(struct qcom_pcie *priv)
170	{
171	u8 offset = pcie_dw_find_capability(&priv->dw, PCI_CAP_ID_EXP);
172	unsigned int cnt = 0;
173	u16 val;
174
175	do {
176	val = readw(priv->dw.dbi_base + offset + PCI_EXP_LNKSTA);
177
178	if ((val & PCI_EXP_LNKSTA_DLLLA))
179	return true;
180	cnt++;
181
182	udelay(LINK_WAIT_USLEEP);
183	} while (cnt < LINK_WAIT_MAX_RETRIES);
184
185	return false;
186	}
187
188	static void qcom_pcie_clear_aspm_l0s(struct qcom_pcie *priv)
189	{
190	u8 offset = pcie_dw_find_capability(&priv->dw, PCI_CAP_ID_EXP);
191	u32 val;
192
193	dw_pcie_dbi_write_enable(&priv->dw, true);
194
195	val = readl(priv->dw.dbi_base + offset + PCI_EXP_LNKCAP);
196	val &= ~PCI_EXP_LNKCAP_ASPM_L0S;
197	writel(val, priv->dw.dbi_base + offset + PCI_EXP_LNKCAP);
198
199	dw_pcie_dbi_write_enable(&priv->dw, false);
200	}
201
202	static void qcom_pcie_clear_hpc(struct qcom_pcie *priv)
203	{
204	u8 offset = pcie_dw_find_capability(&priv->dw, PCI_CAP_ID_EXP);
205	u32 val;
206
207	dw_pcie_dbi_write_enable(&priv->dw, true);
208
209	val = readl(priv->dw.dbi_base + offset + PCI_EXP_SLTCAP);
210	val &= ~PCI_EXP_SLTCAP_HPC;
211	writel(val, priv->dw.dbi_base + offset + PCI_EXP_SLTCAP);
212
213	dw_pcie_dbi_write_enable(&priv->dw, false);
214	}
215
216	static void qcom_pcie_set_lanes(struct qcom_pcie *priv, unsigned int lanes)
217	{
218	u8 offset = pcie_dw_find_capability(&priv->dw, PCI_CAP_ID_EXP);
219	u32 val;
220
221	val = readl(priv->dw.dbi_base + offset + PCI_EXP_LNKCAP);
222	val &= ~PCI_EXP_LNKCAP_MLW;
223	val \|= FIELD_PREP(PCI_EXP_LNKCAP_MLW, lanes);
224	writel(val, priv->dw.dbi_base + offset + PCI_EXP_LNKCAP);
225	}
226
227	static int qcom_pcie_config_sid_1_9_0(struct qcom_pcie *priv)
228	{
229	/* iommu map structure */
230	struct {
231	u32 bdf;
232	u32 phandle;
233	u32 smmu_sid;
234	u32 smmu_sid_len;
235	} *map;
236	void *bdf_to_sid_base = priv->parf + PARF_BDF_TO_SID_TABLE_N;
237	int i, nr_map, size = 0;
238	u32 smmu_sid_base;
239
240	dev_read_prop(priv->dw.dev, "iommu-map", &size);
241	if (!size)
242	return 0;
243
244	map = malloc(size);
245	if (!map)
246	return -ENOMEM;
247
248	dev_read_u32_array(priv->dw.dev, "iommu-map", (u32 *)map, size / sizeof(u32));
249
250	nr_map = size / (sizeof(*map));
251
252	/* Registers need to be zero out first */
253	memset_io(bdf_to_sid_base, 0, CRC8_TABLE_SIZE * sizeof(u32));
254
255	/* Extract the SMMU SID base from the first entry of iommu-map */
256	smmu_sid_base = map[0].smmu_sid;
257
258	/* Look for an available entry to hold the mapping */
259	for (i = 0; i < nr_map; i++) {
260	__be16 bdf_be = cpu_to_be16(map[i].bdf);
261	u32 val;
262	u8 hash;
263
264	hash = crc8(QCOM_PCIE_CRC8_POLYNOMIAL, (u8 *)&bdf_be, sizeof(bdf_be));
265
266	val = readl(bdf_to_sid_base + hash * sizeof(u32));
267
268	/* If the register is already populated, look for next available entry */
269	while (val) {
270	u8 current_hash = hash++;
271	u8 next_mask = 0xff;
272
273	/* If NEXT field is NULL then update it with next hash */
274	if (!(val & next_mask)) {
275	val \|= (u32)hash;
276	writel(val, bdf_to_sid_base + current_hash * sizeof(u32));
277	}
278
279	val = readl(bdf_to_sid_base + hash * sizeof(u32));
280	}
281
282	/* BDF [31:16] \| SID [15:8] \| NEXT [7:0] */
283	val = map[i].bdf << 16 \| (map[i].smmu_sid - smmu_sid_base) << 8 \| 0;
284	writel(val, bdf_to_sid_base + hash * sizeof(u32));
285	}
286
287	free(map);
288
289	return 0;
290	}
291
292	static void qcom_pcie_configure(struct qcom_pcie *priv)
293	{
294	u32 val;
295
296	dw_pcie_dbi_write_enable(&priv->dw, true);
297
298	val = readl(priv->dw.dbi_base + PCIE_PORT_LINK_CONTROL);
299	val &= ~PORT_LINK_FAST_LINK_MODE;
300	val \|= PORT_LINK_DLL_LINK_EN;
301	val &= ~PORT_LINK_MODE_MASK;
302	val \|= PORT_LINK_MODE_2_LANES;
303	writel(val, priv->dw.dbi_base + PCIE_PORT_LINK_CONTROL);
304
305	val = readl(priv->dw.dbi_base + PCIE_LINK_WIDTH_SPEED_CONTROL);
306	val &= ~PORT_LOGIC_LINK_WIDTH_MASK;
307	val \|= PORT_LOGIC_LINK_WIDTH_2_LANES;
308	writel(val, priv->dw.dbi_base + PCIE_LINK_WIDTH_SPEED_CONTROL);
309
310	qcom_pcie_set_lanes(priv, 2);
311
312	dw_pcie_dbi_write_enable(&priv->dw, false);
313	}
314
315	static int qcom_pcie_init_port(struct udevice *dev)
316	{
317	struct qcom_pcie *priv = dev_get_priv(dev);
318	int vreg, ret;
319	u32 val;
320
321	dm_gpio_set_value(&priv->rst_gpio, 1);
322	udelay(PERST_DELAY_US);
323
324	ret = generic_phy_init(&priv->phy);
325	if (ret) {
326	dev_err(dev, "failed to init phy (%d)\n", ret);
327	return ret;
328	}
329
330	udelay(PERST_DELAY_US);
331
332	for (vreg = 0; vreg < NUM_SUPPLIES; ++vreg) {
333	ret = regulator_set_enable(priv->vregs[vreg], true);
334	if (ret && ret != -ENOSYS)
335	dev_warn(dev, "failed to enable regulator %d (%d)\n", vreg, ret);
336	}
337
338	ret = clk_enable_bulk(&priv->clks);
339	if (ret) {
340	dev_err(dev, "failed to enable clocks (%d)\n", ret);
341	goto err_power_off_phy;
342	}
343
344	ret = reset_assert_bulk(&priv->rsts);
345	if (ret) {
346	dev_err(dev, "failed to assert resets (%d)\n", ret);
347	goto err_disable_clks;
348	}
349
350	udelay(PERST_DELAY_US);
351
352	ret = reset_deassert_bulk(&priv->rsts);
353	if (ret) {
354	dev_err(dev, "failed to deassert resets (%d)\n", ret);
355	goto err_power_off_phy;
356	}
357
358	udelay(PERST_DELAY_US);
359
360	/* configure PCIe to RC mode */
361	writel(DEVICE_TYPE_RC, priv->parf + PARF_DEVICE_TYPE);
362
363	/* enable PCIe clocks and resets */
364	val = readl(priv->parf + PARF_PHY_CTRL);
365	val &= ~PHY_TEST_PWR_DOWN;
366	writel(val, priv->parf + PARF_PHY_CTRL);
367
368	/* change DBI base address */
369	writel(0, priv->parf + PARF_DBI_BASE_ADDR);
370
371	/* MAC PHY_POWERDOWN MUX DISABLE */
372	val = readl(priv->parf + PARF_SYS_CTRL);
373	val &= ~MAC_PHY_POWERDOWN_IN_P2_D_MUX_EN;
374	writel(val, priv->parf + PARF_SYS_CTRL);
375
376	val = readl(priv->parf + PARF_MHI_CLOCK_RESET_CTRL);
377	val \|= BYPASS;
378	writel(val, priv->parf + PARF_MHI_CLOCK_RESET_CTRL);
379
380	/* Enable L1 and L1SS */
381	val = readl(priv->parf + PARF_PM_CTRL);
382	val &= ~REQ_NOT_ENTR_L1;
383	writel(val, priv->parf + PARF_PM_CTRL);
384
385	val = readl(priv->parf + PARF_AXI_MSTR_WR_ADDR_HALT_V2);
386	val \|= EN;
387	writel(val, priv->parf + PARF_AXI_MSTR_WR_ADDR_HALT_V2);
388
389	ret = generic_phy_power_on(&priv->phy);
390	if (ret) {
391	dev_err(dev, "failed to power on phy (%d)\n", ret);
392	goto err_exit_phy;
393	}
394
395	qcom_pcie_clear_aspm_l0s(priv);
396	qcom_pcie_clear_hpc(priv);
397
398	mdelay(100);
399	dm_gpio_set_value(&priv->rst_gpio, 0);
400	udelay(PERST_DELAY_US);
401
402	if (priv->ops && priv->ops->config_sid) {
403	ret = priv->ops->config_sid(priv);
404	if (ret)
405	goto err_deassert_bulk;
406	}
407
408	qcom_pcie_configure(priv);
409
410	pcie_dw_setup_host(&priv->dw);
411
412	/* enable link training */
413	val = readl(priv->parf + PARF_LTSSM);
414	val \|= LTSSM_EN;
415	writel(val, priv->parf + PARF_LTSSM);
416
417	return 0;
418	err_deassert_bulk:
419	reset_assert_bulk(&priv->rsts);
420	err_disable_clks:
421	clk_disable_bulk(&priv->clks);
422	err_power_off_phy:
423	generic_phy_power_off(&priv->phy);
424	err_exit_phy:
425	generic_phy_exit(&priv->phy);
426
427	return ret;
428	}
429
430	static const char *qcom_pcie_vregs[NUM_SUPPLIES] = {
431	"vdda-supply",
432	"vddpe-3v3-supply",
433	};
434
435	static int qcom_pcie_parse_dt(struct udevice *dev)
436	{
437	struct qcom_pcie *priv = dev_get_priv(dev);
438	int vreg, ret;
439
440	priv->dw.dbi_base = dev_read_addr_name_ptr(dev, "dbi");
441	if (!priv->dw.dbi_base)
442	return -EINVAL;
443
444	dev_dbg(dev, "DBI address is 0x%p\n", priv->dw.dbi_base);
445
446	priv->dw.atu_base = dev_read_addr_name_ptr(dev, "atu");
447	if (!priv->dw.atu_base)
448	return -EINVAL;
449
450	dev_dbg(dev, "ATU address is 0x%p\n", priv->dw.atu_base);
451
452	priv->parf = dev_read_addr_name_ptr(dev, "parf");
453	if (!priv->parf)
454	return -EINVAL;
455
456	dev_dbg(dev, "PARF address is 0x%p\n", priv->parf);
457
458	ret = gpio_request_by_name(dev, "perst-gpios", 0,
459	&priv->rst_gpio, GPIOD_IS_OUT);
460	if (ret) {
461	dev_err(dev, "failed to find reset-gpios property\n");
462	return ret;
463	}
464
465	ret = reset_get_bulk(dev, &priv->rsts);
466	if (ret) {
467	dev_err(dev, "failed to get resets (%d)\n", ret);
468	return ret;
469	}
470
471	ret = clk_get_bulk(dev, &priv->clks);
472	if (ret) {
473	dev_err(dev, "failed to get clocks (%d)\n", ret);
474	return ret;
475	}
476
477	ret = generic_phy_get_by_index(dev, 0, &priv->phy);
478	if (ret) {
479	dev_err(dev, "failed to get pcie phy (%d)\n", ret);
480	return ret;
481	}
482
483	for (vreg = 0; vreg < NUM_SUPPLIES; ++vreg) {
484	ret = device_get_supply_regulator(dev, qcom_pcie_vregs[vreg], &priv->vregs[vreg]);
485	if (ret)
486	dev_warn(dev, "failed to get regulator %d (%d)\n", vreg, ret);
487	}
488
489	return 0;
490	}
491
492	/**
493	* qcom_pcie_probe() - Probe the PCIe bus for active link
494	*
495	* @dev: A pointer to the device being operated on
496	*
497	* Probe for an active link on the PCIe bus and configure the controller
498	* to enable this port.
499	*
500	* Return: 0 on success, else -ENODEV
501	*/
502	static int qcom_pcie_probe(struct udevice *dev)
503	{
504	struct qcom_pcie *priv = dev_get_priv(dev);
505	struct udevice *ctlr = pci_get_controller(dev);
506	struct pci_controller *hose = dev_get_uclass_priv(ctlr);
507	int ret = 0;
508
509	priv->dw.first_busno = dev_seq(dev);
510	priv->dw.dev = dev;
511
512	ret = qcom_pcie_parse_dt(dev);
513	if (ret)
514	return ret;
515
516	ret = qcom_pcie_init_port(dev);
517	if (ret) {
518	dm_gpio_free(dev, &priv->rst_gpio);
519	return ret;
520	}
521
522	if (qcom_pcie_wait_link_up(priv))
523	printf("PCIE-%d: Link up (Gen%d-x%d, Bus%d)\n",
524	dev_seq(dev), pcie_dw_get_link_speed(&priv->dw),
525	pcie_dw_get_link_width(&priv->dw),
526	hose->first_busno);
527	else
528	printf("PCIE-%d: Link up timeout\n", dev_seq(dev));
529
530	return pcie_dw_prog_outbound_atu_unroll(&priv->dw,
531	PCIE_ATU_REGION_INDEX0,
532	PCIE_ATU_TYPE_MEM,
533	priv->dw.mem.phys_start,
534	priv->dw.mem.bus_start,
535	priv->dw.mem.size);
536	}
537
538	static const struct dm_pci_ops qcom_pcie_ops = {
539	.read_config = pcie_dw_read_config,
540	.write_config = pcie_dw_write_config,
541	};
542
543	static const struct qcom_pcie_ops ops_1_9_0 = {
544	.config_sid = qcom_pcie_config_sid_1_9_0,
545	};
546
547	static const struct udevice_id qcom_pcie_ids[] = {
548	{ .compatible = "qcom,pcie-sa8540p", .data = (ulong)&ops_1_9_0 },
549	{ .compatible = "qcom,pcie-sc7280", .data = (ulong)&ops_1_9_0 },
550	{ .compatible = "qcom,pcie-sc8180x", .data = (ulong)&ops_1_9_0 },
551	{ .compatible = "qcom,pcie-sc8280xp", .data = (ulong)&ops_1_9_0 },
552	{ .compatible = "qcom,pcie-sdm845" },
553	{ .compatible = "qcom,pcie-sdx55", .data = (ulong)&ops_1_9_0 },
554	{ .compatible = "qcom,pcie-sm8150", .data = (ulong)&ops_1_9_0 },
555	{ .compatible = "qcom,pcie-sm8250", .data = (ulong)&ops_1_9_0 },
556	{ .compatible = "qcom,pcie-sm8350", .data = (ulong)&ops_1_9_0 },
557	{ .compatible = "qcom,pcie-sm8450-pcie0", .data = (ulong)&ops_1_9_0 },
558	{ .compatible = "qcom,pcie-sm8450-pcie1", .data = (ulong)&ops_1_9_0 },
559	{ .compatible = "qcom,pcie-sm8550", .data = (ulong)&ops_1_9_0 },
560	{ .compatible = "qcom,pcie-x1e80100", .data = (ulong)&ops_1_9_0 },
561	{ }
562	};
563
564	U_BOOT_DRIVER(qcom_dw_pcie) = {
565	.name = "pcie_dw_qcom",
566	.id = UCLASS_PCI,
567	.of_match = qcom_pcie_ids,
568	.ops = &qcom_pcie_ops,
569	.probe = qcom_pcie_probe,
570	.priv_auto = sizeof(struct qcom_pcie),
571	};