projects / J-u-boot.git / blame
| Commit | Line | Data |
|---|---|---|
| fe11aa0b KLL |
1 | /* SPDX-License-Identifier: GPL-2.0+ */ |
| 2 | /* | |
| 3 | * Copyright (C) 2016 Socionext Inc. | |
| 4 | * Author: Masahiro Yamada <[email protected]> | |
| 5 | */ | |
| 6 | ||
| 7 | #ifndef SDHCI_CADENCE_H_ | |
| 8 | #define SDHCI_CADENCE_H_ | |
| 9 | ||
| 10 | /* HRS - Host Register Set (specific to Cadence) */ | |
| 11 | /* PHY access port */ | |
| 12 | #define SDHCI_CDNS_HRS04 0x10 | |
| 13 | /* Cadence V4 HRS04 Description*/ | |
| 14 | #define SDHCI_CDNS_HRS04_ACK BIT(26) | |
| 15 | #define SDHCI_CDNS_HRS04_RD BIT(25) | |
| 16 | #define SDHCI_CDNS_HRS04_WR BIT(24) | |
| 17 | #define SDHCI_CDNS_HRS04_RDATA GENMASK(23, 16) | |
| 18 | #define SDHCI_CDNS_HRS04_WDATA GENMASK(15, 8) | |
| 19 | #define SDHCI_CDNS_HRS04_ADDR GENMASK(5, 0) | |
| 20 | ||
| 21 | #define SDHCI_CDNS_HRS05 0x14 | |
| 22 | ||
| 23 | /* eMMC control */ | |
| 24 | #define SDHCI_CDNS_HRS06 0x18 | |
| 25 | #define SDHCI_CDNS_HRS06_TUNE_UP BIT(15) | |
| 26 | #define SDHCI_CDNS_HRS06_TUNE GENMASK(13, 8) | |
| 27 | #define SDHCI_CDNS_HRS06_MODE GENMASK(2, 0) | |
| 28 | #define SDHCI_CDNS_HRS06_MODE_SD 0x0 | |
| 29 | #define SDHCI_CDNS_HRS06_MODE_MMC_SDR 0x2 | |
| 30 | #define SDHCI_CDNS_HRS06_MODE_MMC_DDR 0x3 | |
| 31 | #define SDHCI_CDNS_HRS06_MODE_MMC_HS200 0x4 | |
| 32 | #define SDHCI_CDNS_HRS06_MODE_MMC_HS400 0x5 | |
| 33 | #define SDHCI_CDNS_HRS06_MODE_MMC_HS400ES 0x6 | |
| 34 | ||
| 35 | /* SRS - Slot Register Set (SDHCI-compatible) */ | |
| 36 | #define SDHCI_CDNS_SRS_BASE 0x200 | |
| 37 | ||
| 38 | /* Cadence V4 PHY Setting*/ | |
| 39 | #define SDHCI_CDNS_PHY_DLY_SD_HS 0x00 | |
| 40 | #define SDHCI_CDNS_PHY_DLY_SD_DEFAULT 0x01 | |
| 41 | #define SDHCI_CDNS_PHY_DLY_UHS_SDR12 0x02 | |
| 42 | #define SDHCI_CDNS_PHY_DLY_UHS_SDR25 0x03 | |
| 43 | #define SDHCI_CDNS_PHY_DLY_UHS_SDR50 0x04 | |
| 44 | #define SDHCI_CDNS_PHY_DLY_UHS_DDR50 0x05 | |
| 45 | #define SDHCI_CDNS_PHY_DLY_EMMC_LEGACY 0x06 | |
| 46 | #define SDHCI_CDNS_PHY_DLY_EMMC_SDR 0x07 | |
| 47 | #define SDHCI_CDNS_PHY_DLY_EMMC_DDR 0x08 | |
| 48 | #define SDHCI_CDNS_PHY_DLY_SDCLK 0x0b | |
| 49 | #define SDHCI_CDNS_PHY_DLY_HSMMC 0x0c | |
| 50 | #define SDHCI_CDNS_PHY_DLY_STROBE 0x0d | |
| 51 | ||
| 52 | /* | |
| 53 | * The tuned val register is 6 bit-wide, but not the whole of the range is | |
| 54 | * available. The range 0-42 seems to be available (then 43 wraps around to 0) | |
| 55 | * but I am not quite sure if it is official. Use only 0 to 39 for safety. | |
| 56 | */ | |
| 57 | #define SDHCI_CDNS_MAX_TUNING_LOOP 40 | |
| 58 | ||
| 59 | struct sdhci_cdns_plat { | |
| 60 | struct mmc_config cfg; | |
| 61 | struct mmc mmc; | |
| 62 | void __iomem *hrs_addr; | |
| 63 | }; | |
| 64 | ||
| 65 | int sdhci_cdns6_phy_adj(struct udevice *dev, struct sdhci_cdns_plat *plat, u32 mode); | |
| 66 | int sdhci_cdns6_phy_init(struct udevice *dev, struct sdhci_cdns_plat *plat); | |
| 67 | int sdhci_cdns6_set_tune_val(struct sdhci_cdns_plat *plat, unsigned int val); | |
| 68 | ||
| 69 | #endif |