[J-u-boot.git] / drivers / clk / qcom / clock-qcom.h

/* SPDX-License-Identifier: GPL-2.0+ */
/*
 * (C) Copyright 2017 Jorge Ramirez-Ortiz <[email protected]>
 */
#ifndef _CLOCK_QCOM_H
#define _CLOCK_QCOM_H

#include <asm/io.h>
#include <linux/bitfield.h>

#define CFG_CLK_SRC_CXO   (0 << 8)
#define CFG_CLK_SRC_GPLL0 (1 << 8)
#define CFG_CLK_SRC_GPLL0_AUX2 (2 << 8)
#define CFG_CLK_SRC_GPLL9 (2 << 8)
#define CFG_CLK_SRC_GPLL0_ODD (3 << 8)
#define CFG_CLK_SRC_GPLL6 (4 << 8)
#define CFG_CLK_SRC_GPLL7 (3 << 8)
#define CFG_CLK_SRC_GPLL4 (5 << 8)
#define CFG_CLK_SRC_GPLL0_EVEN (6 << 8)
#define CFG_CLK_SRC_MASK  (7 << 8)

#define RCG_CFG_REG		0x4
#define RCG_M_REG		0x8
#define RCG_N_REG		0xc
#define RCG_D_REG		0x10

struct pll_vote_clk {
	uintptr_t status;
	int status_bit;
	uintptr_t ena_vote;
	int vote_bit;
};

struct vote_clk {
	uintptr_t cbcr_reg;
	uintptr_t ena_vote;
	int vote_bit;
};

struct freq_tbl {
	uint freq;
	uint src;
	u8 pre_div;
	u16 m;
	u16 n;
};

#define F(f, s, h, m, n) { (f), (s), (2 * (h) - 1), (m), (n) }

struct gate_clk {
	uintptr_t reg;
	u32 en_val;
	const char *name;
};

#ifdef DEBUG
#define GATE_CLK(clk, reg, val) [clk] = { reg, val, #clk }
#else
#define GATE_CLK(clk, reg, val) [clk] = { reg, val, NULL }
#endif

struct qcom_reset_map {
	unsigned int reg;
	u8 bit;
};

struct qcom_power_map {
	unsigned int reg;
};

struct clk;

struct msm_clk_data {
	const struct qcom_power_map	*power_domains;
	unsigned long			num_power_domains;
	const struct qcom_reset_map	*resets;
	unsigned long			num_resets;
	const struct gate_clk		*clks;
	unsigned long			num_clks;

	const phys_addr_t		*dbg_pll_addrs;
	unsigned long			num_plls;
	const phys_addr_t		*dbg_rcg_addrs;
	unsigned long			num_rcgs;
	const char * const		*dbg_rcg_names;

	int (*enable)(struct clk *clk);
	unsigned long (*set_rate)(struct clk *clk, unsigned long rate);
};

struct msm_clk_priv {
	phys_addr_t		base;
	struct msm_clk_data	*data;
};

int qcom_cc_bind(struct udevice *parent);
void clk_enable_gpll0(phys_addr_t base, const struct pll_vote_clk *gpll0);
void clk_bcr_update(phys_addr_t apps_cmd_rgcr);
void clk_enable_cbc(phys_addr_t cbcr);
void clk_enable_vote_clk(phys_addr_t base, const struct vote_clk *vclk);
const struct freq_tbl *qcom_find_freq(const struct freq_tbl *f, uint rate);
void clk_rcg_set_rate_mnd(phys_addr_t base, uint32_t cmd_rcgr,
			  int div, int m, int n, int source, u8 mnd_width);
void clk_rcg_set_rate(phys_addr_t base, uint32_t cmd_rcgr, int div,
		      int source);
void clk_phy_mux_enable(phys_addr_t base, uint32_t cmd_rcgr, bool enabled);

static inline void qcom_gate_clk_en(const struct msm_clk_priv *priv, unsigned long id)
{
	u32 val;
	if (id >= priv->data->num_clks || priv->data->clks[id].reg == 0)
		return;

	val = readl(priv->base + priv->data->clks[id].reg);
	writel(val | priv->data->clks[id].en_val, priv->base + priv->data->clks[id].reg);
}

#endif
Commit	Line	Data
83d290c5	1	/* SPDX-License-Identifier: GPL-2.0+ */
7c75f7f1	2	/*
7c75f7f1	3	* (C) Copyright 2017 Jorge Ramirez-Ortiz <[email protected]>
7c75f7f1	4	*/
3ead6616 KD	5	#ifndef _CLOCK_QCOM_H
3ead6616 KD	6	#define _CLOCK_QCOM_H
7c75f7f1	7
0e7fec02	8	#include <asm/io.h>
5b359312	9	#include <linux/bitfield.h>
0e7fec02	10
7c75f7f1 JRO	11	#define CFG_CLK_SRC_CXO (0 << 8)
7c75f7f1 JRO	12	#define CFG_CLK_SRC_GPLL0 (1 << 8)
c78210fc	13	#define CFG_CLK_SRC_GPLL0_AUX2 (2 << 8)
dcd68822	14	#define CFG_CLK_SRC_GPLL9 (2 << 8)
f50e7be6	15	#define CFG_CLK_SRC_GPLL0_ODD (3 << 8)
c78210fc CC	16	#define CFG_CLK_SRC_GPLL6 (4 << 8)
c78210fc CC	17	#define CFG_CLK_SRC_GPLL7 (3 << 8)
6a0b9d88	18	#define CFG_CLK_SRC_GPLL4 (5 << 8)
90496afc	19	#define CFG_CLK_SRC_GPLL0_EVEN (6 << 8)
7c75f7f1 JRO	20	#define CFG_CLK_SRC_MASK (7 << 8)
7c75f7f1 JRO	21
d33d4e0a CC	22	#define RCG_CFG_REG 0x4
	23	#define RCG_M_REG 0x8
	24	#define RCG_N_REG 0xc
	25	#define RCG_D_REG 0x10
	26
640dc349	27	struct pll_vote_clk {
7c75f7f1 JRO	28	uintptr_t status;
	29	int status_bit;
	30	uintptr_t ena_vote;
	31	int vote_bit;
	32	};
	33
640dc349 RF	34	struct vote_clk {
	35	uintptr_t cbcr_reg;
	36	uintptr_t ena_vote;
	37	int vote_bit;
	38	};
7c75f7f1	39
d5db46cf CC	40	struct freq_tbl {
	41	uint freq;
	42	uint src;
	43	u8 pre_div;
	44	u16 m;
	45	u16 n;
	46	};
	47
	48	#define F(f, s, h, m, n) { (f), (s), (2 * (h) - 1), (m), (n) }
	49
0e7fec02 CC	50	struct gate_clk {
	51	uintptr_t reg;
	52	u32 en_val;
	53	const char *name;
	54	};
	55
	56	#ifdef DEBUG
	57	#define GATE_CLK(clk, reg, val) [clk] = { reg, val, #clk }
	58	#else
	59	#define GATE_CLK(clk, reg, val) [clk] = { reg, val, NULL }
	60	#endif
	61
3ead6616 KD	62	struct qcom_reset_map {
	63	unsigned int reg;
	64	u8 bit;
	65	};
	66
b563e766 VB	67	struct qcom_power_map {
	68	unsigned int reg;
	69	};
	70
37ea1343 CC	71	struct clk;
37ea1343 CC	72
3ead6616	73	struct msm_clk_data {
b563e766 VB	74	const struct qcom_power_map *power_domains;
b563e766 VB	75	unsigned long num_power_domains;
3ead6616 KD	76	const struct qcom_reset_map *resets;
3ead6616 KD	77	unsigned long num_resets;
0e7fec02 CC	78	const struct gate_clk *clks;
0e7fec02 CC	79	unsigned long num_clks;
37ea1343	80
ba0598bd CC	81	const phys_addr_t *dbg_pll_addrs;
	82	unsigned long num_plls;
	83	const phys_addr_t *dbg_rcg_addrs;
	84	unsigned long num_rcgs;
	85	const char * const *dbg_rcg_names;
	86
37ea1343 CC	87	int (enable)(struct clk clk);
37ea1343 CC	88	unsigned long (set_rate)(struct clk clk, unsigned long rate);
3ead6616 KD	89	};
3ead6616 KD	90
7c75f7f1	91	struct msm_clk_priv {
3ead6616 KD	92	phys_addr_t base;
3ead6616 KD	93	struct msm_clk_data *data;
7c75f7f1 JRO	94	};
7c75f7f1 JRO	95
3ead6616	96	int qcom_cc_bind(struct udevice *parent);
640dc349	97	void clk_enable_gpll0(phys_addr_t base, const struct pll_vote_clk *gpll0);
7c75f7f1 JRO	98	void clk_bcr_update(phys_addr_t apps_cmd_rgcr);
7c75f7f1 JRO	99	void clk_enable_cbc(phys_addr_t cbcr);
640dc349	100	void clk_enable_vote_clk(phys_addr_t base, const struct vote_clk *vclk);
d5db46cf	101	const struct freq_tbl qcom_find_freq(const struct freq_tbl f, uint rate);
d33d4e0a	102	void clk_rcg_set_rate_mnd(phys_addr_t base, uint32_t cmd_rcgr,
6acc4431	103	int div, int m, int n, int source, u8 mnd_width);
d33d4e0a	104	void clk_rcg_set_rate(phys_addr_t base, uint32_t cmd_rcgr, int div,
22d3fcd3	105	int source);
5b359312	106	void clk_phy_mux_enable(phys_addr_t base, uint32_t cmd_rcgr, bool enabled);
7c75f7f1	107
0e7fec02 CC	108	static inline void qcom_gate_clk_en(const struct msm_clk_priv *priv, unsigned long id)
	109	{
	110	u32 val;
	111	if (id >= priv->data->num_clks \|\| priv->data->clks[id].reg == 0)
	112	return;
	113
	114	val = readl(priv->base + priv->data->clks[id].reg);
	115	writel(val \| priv->data->clks[id].en_val, priv->base + priv->data->clks[id].reg);
	116	}
	117
7c75f7f1	118	#endif