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Commit | Line | Data |
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81385818 MY |
1 | menu "Clock" |
2 | ||
f26c8a8e SG |
3 | config CLK |
4 | bool "Enable clock driver support" | |
5 | depends on DM | |
6 | help | |
7 | This allows drivers to be provided for clock generators, including | |
8 | oscillators and PLLs. Devices can use a common clock API to request | |
9 | a particular clock rate and check on available clocks. Clocks can | |
10 | feed into other clocks in a tree structure, with multiplexers to | |
11 | choose the source for each clock. | |
12 | ||
05435891 | 13 | config SPL_CLK |
f26c8a8e | 14 | bool "Enable clock support in SPL" |
0712b672 | 15 | depends on CLK && SPL && SPL_DM |
f26c8a8e SG |
16 | help |
17 | The clock subsystem adds a small amount of overhead to the image. | |
18 | If this is acceptable and you have a need to use clock drivers in | |
19 | SPL, enable this option. It might provide a cleaner interface to | |
20 | setting up clocks within SPL, and allows the same drivers to be | |
21 | used as U-Boot proper. | |
81385818 | 22 | |
7c819e7f PT |
23 | config TPL_CLK |
24 | bool "Enable clock support in TPL" | |
25 | depends on CLK && TPL_DM | |
26 | help | |
27 | The clock subsystem adds a small amount of overhead to the image. | |
28 | If this is acceptable and you have a need to use clock drivers in | |
29 | SPL, enable this option. It might provide a cleaner interface to | |
30 | setting up clocks within TPL, and allows the same drivers to be | |
31 | used as U-Boot proper. | |
32 | ||
747093dd SG |
33 | config VPL_CLK |
34 | bool "Enable clock support in VPL" | |
35 | depends on CLK && VPL_DM | |
36 | help | |
37 | The clock subsystem adds a small amount of overhead to the image. | |
38 | If this is acceptable and you have a need to use clock drivers in | |
39 | SPL, enable this option. It might provide a cleaner interface to | |
40 | setting up clocks within TPL, and allows the same drivers to be | |
41 | used as U-Boot proper. | |
42 | ||
43 | config CLK_BCM6345 | |
44 | bool "Clock controller driver for BCM6345" | |
45 | depends on CLK && ARCH_BMIPS | |
46 | default y | |
47 | help | |
48 | This clock driver adds support for enabling and disabling peripheral | |
49 | clocks on BCM6345 SoCs. HW has no rate changing capabilities. | |
50 | ||
51 | config CLK_BOSTON | |
52 | def_bool y if TARGET_BOSTON | |
53 | depends on CLK | |
54 | select REGMAP | |
55 | select SYSCON | |
56 | help | |
57 | Enable this to support the clocks | |
58 | ||
1d7993d1 | 59 | config SPL_CLK_CCF |
d20bcbaa | 60 | bool "SPL Common Clock Framework [CCF] support" |
a074667d | 61 | depends on SPL |
1d7993d1 LM |
62 | help |
63 | Enable this option if you want to (re-)use the Linux kernel's Common | |
64 | Clock Framework [CCF] code in U-Boot's SPL. | |
65 | ||
00097635 | 66 | config SPL_CLK_COMPOSITE_CCF |
d20bcbaa | 67 | bool "SPL Common Clock Framework [CCF] composite clk support" |
00097635 PF |
68 | depends on SPL_CLK_CCF |
69 | help | |
70 | Enable this option if you want to (re-)use the Linux kernel's Common | |
71 | Clock Framework [CCF] composite code in U-Boot's SPL. | |
72 | ||
1d7993d1 | 73 | config CLK_CCF |
d20bcbaa | 74 | bool "Common Clock Framework [CCF] support" |
1d7993d1 LM |
75 | help |
76 | Enable this option if you want to (re-)use the Linux kernel's Common | |
77 | Clock Framework [CCF] code in U-Boot's clock driver. | |
78 | ||
00097635 | 79 | config CLK_COMPOSITE_CCF |
d20bcbaa | 80 | bool "Common Clock Framework [CCF] composite clk support" |
00097635 PF |
81 | depends on CLK_CCF |
82 | help | |
83 | Enable this option if you want to (re-)use the Linux kernel's Common | |
84 | Clock Framework [CCF] composite code in U-Boot's clock driver. | |
85 | ||
92d5f996 MV |
86 | config CLK_GPIO |
87 | bool "GPIO-controlled clock gate driver" | |
88 | depends on CLK | |
89 | help | |
90 | Enable this option to add GPIO-controlled clock gate driver. | |
91 | ||
92 | config SPL_CLK_GPIO | |
93 | bool "GPIO-controlled clock gate driver in SPL" | |
94 | depends on SPL_CLK | |
95 | help | |
96 | Enable this option to add GPIO-controlled clock gate driver | |
97 | in U-Boot SPL. | |
98 | ||
7d4a7852 SA |
99 | config CLK_BCM6345 |
100 | bool "Clock controller driver for BCM6345" | |
101 | depends on CLK && ARCH_BMIPS | |
102 | default y | |
103 | help | |
104 | This clock driver adds support for enabling and disabling peripheral | |
105 | clocks on BCM6345 SoCs. HW has no rate changing capabilities. | |
106 | ||
107 | config CLK_BOSTON | |
108 | def_bool y if TARGET_BOSTON | |
109 | depends on CLK | |
110 | select REGMAP | |
111 | select SYSCON | |
112 | help | |
113 | Enable this to support the clocks | |
114 | ||
115 | config CLK_CDCE9XX | |
116 | bool "Enable CDCD9XX clock driver" | |
117 | depends on CLK | |
118 | help | |
119 | Enable the clock synthesizer driver for CDCE913/925/937/949 | |
120 | series of chips. | |
121 | ||
052bebe5 | 122 | config CLK_ICS8N3QV01 |
7d4a7852 SA |
123 | bool "Enable ICS8N3QV01 VCXO driver" |
124 | depends on CLK | |
125 | help | |
126 | Support for the ICS8N3QV01 Quad-Frequency VCXO (Voltage-Controlled | |
127 | Crystal Oscillator). The output frequency can be programmed via an | |
128 | I2C interface. | |
129 | ||
b4d00b25 SG |
130 | config CLK_INTEL |
131 | bool "Enable clock driver for Intel x86" | |
132 | depends on CLK && X86 | |
133 | help | |
134 | This provides very basic support for clocks on Intel SoCs. The driver | |
135 | is barely used at present but could be expanded as needs arise. | |
136 | Much clock configuration in U-Boot is either set up by the FSP, or | |
137 | set up by U-Boot itself but only statically. Thus the driver does not | |
138 | support changing clock rates, only querying them. | |
139 | ||
7d4a7852 SA |
140 | config CLK_K210 |
141 | bool "Clock support for Kendryte K210" | |
142 | depends on CLK | |
143 | help | |
144 | This enables support clock driver for Kendryte K210 platforms. | |
145 | ||
146 | config CLK_K210_SET_RATE | |
147 | bool "Enable setting the Kendryte K210 PLL rate" | |
148 | depends on CLK_K210 | |
149 | help | |
150 | Add functionality to calculate new rates for K210 PLLs. Enabling this | |
151 | feature adds around 1K to U-Boot's final size. | |
152 | ||
153 | config CLK_MPC83XX | |
154 | bool "Enable MPC83xx clock driver" | |
155 | depends on CLK | |
156 | help | |
157 | Support for the clock driver of the MPC83xx series of SoCs. | |
158 | ||
b113c9b5 SR |
159 | config CLK_OCTEON |
160 | bool "Clock controller driver for Marvell MIPS Octeon" | |
161 | depends on CLK && ARCH_OCTEON | |
162 | default y | |
163 | help | |
164 | Enable this to support the clocks on Octeon MIPS platforms. | |
165 | ||
7d4a7852 | 166 | config SANDBOX_CLK_CCF |
d20bcbaa | 167 | bool "Sandbox Common Clock Framework [CCF] support" |
7d4a7852 SA |
168 | depends on SANDBOX |
169 | select CLK_CCF | |
170 | help | |
171 | Enable this option if you want to test the Linux kernel's Common | |
172 | Clock Framework [CCF] code in U-Boot's Sandbox clock driver. | |
173 | ||
174 | config CLK_SCMI | |
175 | bool "Enable SCMI clock driver" | |
45a00529 | 176 | depends on CLK |
7d4a7852 SA |
177 | depends on SCMI_FIRMWARE |
178 | help | |
179 | Enable this option if you want to support clock devices exposed | |
180 | by a SCMI agent based on SCMI clock protocol communication | |
181 | with a SCMI server. | |
182 | ||
22297581 JK |
183 | config SPL_CLK_SCMI |
184 | bool "Enable SCMI clock driver in SPL" | |
185 | depends on SCMI_FIRMWARE && SPL_FIRMWARE | |
186 | help | |
187 | Enable this option if you want to support clock devices exposed | |
188 | by a SCMI agent based on SCMI clock protocol communication | |
189 | with a SCMI server in SPL. | |
190 | ||
e80dac0a | 191 | config CLK_HSDK |
80a7674e EP |
192 | bool "Enable cgu clock driver for HSDK boards" |
193 | depends on CLK && TARGET_HSDK | |
e80dac0a | 194 | help |
80a7674e EP |
195 | Enable this to support the cgu clocks on Synopsys ARC HSDK and |
196 | Synopsys ARC HSDK-4xD boards | |
e80dac0a | 197 | |
7d4a7852 SA |
198 | config CLK_VERSACLOCK |
199 | tristate "Enable VersaClock 5/6 devices" | |
200 | depends on CLK | |
201 | depends on CLK_CCF | |
202 | depends on OF_CONTROL | |
203 | help | |
204 | This driver supports the IDT VersaClock 5 and VersaClock 6 | |
205 | programmable clock generators. | |
206 | ||
95105089 SDPP |
207 | config CLK_VERSAL |
208 | bool "Enable clock driver support for Versal" | |
ff332278 | 209 | depends on (ARCH_VERSAL || ARCH_VERSAL_NET) |
6d87b157 | 210 | imply ZYNQMP_FIRMWARE |
95105089 SDPP |
211 | help |
212 | This clock driver adds support for clock realted settings for | |
213 | Versal platform. | |
214 | ||
a71e907c LD |
215 | config CLK_VEXPRESS_OSC |
216 | bool "Enable driver for Arm Versatile Express OSC clock generators" | |
217 | depends on CLK && VEXPRESS_CONFIG | |
218 | help | |
219 | This clock driver adds support for clock generators present on | |
220 | Arm Versatile Express platforms. | |
221 | ||
2b157d81 Z |
222 | config CLK_XLNX_CLKWZRD |
223 | bool "Xilinx Clocking Wizard" | |
224 | depends on CLK | |
225 | help | |
226 | Support for the Xilinx Clocking Wizard IP core clock generator. | |
227 | The wizard support for dynamically reconfiguring the clocking | |
228 | primitives for Multiply, Divide, Phase Shift/Offset, or Duty | |
229 | Cycle. Limited by U-Boot clk uclass without set_phase API and | |
230 | set_duty_cycle API, this driver only supports set_rate to modify | |
231 | the frequency. | |
232 | ||
7d4a7852 SA |
233 | config CLK_ZYNQ |
234 | bool "Enable clock driver support for Zynq" | |
235 | depends on CLK && ARCH_ZYNQ | |
236 | default y | |
237 | help | |
238 | This clock driver adds support for clock related settings for | |
239 | Zynq platform. | |
240 | ||
128ec1fe SDPP |
241 | config CLK_ZYNQMP |
242 | bool "Enable clock driver support for ZynqMP" | |
243 | depends on ARCH_ZYNQMP | |
6d87b157 | 244 | imply ZYNQMP_FIRMWARE |
128ec1fe SDPP |
245 | help |
246 | This clock driver adds support for clock realted settings for | |
247 | ZynqMP platform. | |
248 | ||
03de305e | 249 | source "drivers/clk/adi/Kconfig" |
d04c79d2 | 250 | source "drivers/clk/analogbits/Kconfig" |
9e5935c0 | 251 | source "drivers/clk/at91/Kconfig" |
cf682257 | 252 | source "drivers/clk/exynos/Kconfig" |
f77d4410 | 253 | source "drivers/clk/imx/Kconfig" |
f5abfed8 | 254 | source "drivers/clk/meson/Kconfig" |
2f27c921 | 255 | source "drivers/clk/microchip/Kconfig" |
82a248df | 256 | source "drivers/clk/mvebu/Kconfig" |
ae485b54 | 257 | source "drivers/clk/owl/Kconfig" |
a623c14f | 258 | source "drivers/clk/qcom/Kconfig" |
cf682257 | 259 | source "drivers/clk/renesas/Kconfig" |
5f364e07 | 260 | source "drivers/clk/sophgo/Kconfig" |
0d47bc70 | 261 | source "drivers/clk/sunxi/Kconfig" |
c40b6df8 | 262 | source "drivers/clk/sifive/Kconfig" |
c13fe7c0 | 263 | source "drivers/clk/starfive/Kconfig" |
b9929333 | 264 | source "drivers/clk/stm32/Kconfig" |
cf682257 | 265 | source "drivers/clk/tegra/Kconfig" |
d09f063a | 266 | source "drivers/clk/ti/Kconfig" |
cf682257 | 267 | source "drivers/clk/uniphier/Kconfig" |
48264d9b | 268 | |
81385818 | 269 | endmenu |