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83d290c5 | 1 | // SPDX-License-Identifier: GPL-2.0+ |
71ebb335 RS |
2 | /* |
3 | * (C) Copyright 2013 SAMSUNG Electronics | |
4 | * Rajeshwari Shinde <[email protected]> | |
71ebb335 RS |
5 | */ |
6 | ||
03de305e | 7 | #include <config.h> |
71ebb335 | 8 | #include <cros_ec.h> |
09140113 | 9 | #include <env.h> |
71ebb335 RS |
10 | #include <errno.h> |
11 | #include <fdtdec.h> | |
db41d65a | 12 | #include <hang.h> |
5255932f | 13 | #include <init.h> |
f7ae49fc | 14 | #include <log.h> |
90526e9f | 15 | #include <net.h> |
71ebb335 RS |
16 | #include <spi.h> |
17 | #include <tmu.h> | |
18 | #include <netdev.h> | |
401d1c4f | 19 | #include <asm/global_data.h> |
71ebb335 | 20 | #include <asm/io.h> |
903fd795 | 21 | #include <asm/gpio.h> |
71ebb335 RS |
22 | #include <asm/arch/board.h> |
23 | #include <asm/arch/cpu.h> | |
24 | #include <asm/arch/dwmmc.h> | |
71ebb335 RS |
25 | #include <asm/arch/mmc.h> |
26 | #include <asm/arch/pinmux.h> | |
27 | #include <asm/arch/power.h> | |
f0017175 | 28 | #include <asm/arch/system.h> |
622e5fee | 29 | #include <i2c.h> |
86c88711 MS |
30 | #include <mmc.h> |
31 | #include <stdio_dev.h> | |
28f393cd | 32 | #include <usb.h> |
302a7d00 | 33 | #include <dwc3-uboot.h> |
c05ed00a | 34 | #include <linux/delay.h> |
302a7d00 | 35 | #include <samsung/misc.h> |
6c15a2a9 TA |
36 | #include <dm/pinctrl.h> |
37 | #include <dm.h> | |
71ebb335 RS |
38 | |
39 | DECLARE_GLOBAL_DATA_PTR; | |
40 | ||
e7e60c13 | 41 | __weak int exynos_early_init_f(void) |
8e5e1e6a PW |
42 | { |
43 | return 0; | |
44 | } | |
8e5e1e6a | 45 | |
4f9c7a9f TR |
46 | __weak void exynos_init(void) |
47 | { | |
48 | } | |
49 | ||
e7e60c13 | 50 | __weak int exynos_power_init(void) |
8e5e1e6a PW |
51 | { |
52 | return 0; | |
53 | } | |
8e5e1e6a | 54 | |
86c88711 MS |
55 | /** |
56 | * get_boot_mmc_dev() - read boot MMC device id from XOM[7:5] pins. | |
57 | */ | |
58 | static int get_boot_mmc_dev(void) | |
59 | { | |
60 | u32 mode = readl(EXYNOS4_OP_MODE) & 0x1C; | |
61 | ||
62 | if (mode == 0x04) | |
63 | return 2; /* MMC2: SD */ | |
64 | ||
65 | /* MMC0: eMMC or unknown */ | |
66 | return 0; | |
67 | } | |
68 | ||
71ebb335 RS |
69 | #if defined CONFIG_EXYNOS_TMU |
70 | /* Boot Time Thermal Analysis for SoC temperature threshold breach */ | |
71 | static void boot_temp_check(void) | |
72 | { | |
73 | int temp; | |
74 | ||
75 | switch (tmu_monitor(&temp)) { | |
76 | case TMU_STATUS_NORMAL: | |
77 | break; | |
78 | case TMU_STATUS_TRIPPED: | |
79 | /* | |
80 | * Status TRIPPED ans WARNING means corresponding threshold | |
81 | * breach | |
82 | */ | |
83 | puts("EXYNOS_TMU: TRIPPING! Device power going down ...\n"); | |
84 | set_ps_hold_ctrl(); | |
85 | hang(); | |
86 | break; | |
87 | case TMU_STATUS_WARNING: | |
88 | puts("EXYNOS_TMU: WARNING! Temperature very high\n"); | |
89 | break; | |
90 | case TMU_STATUS_INIT: | |
91 | /* | |
92 | * TMU_STATUS_INIT means something is wrong with temperature | |
93 | * sensing and TMU status was changed back from NORMAL to INIT. | |
94 | */ | |
95 | puts("EXYNOS_TMU: WARNING! Temperature sensing not done\n"); | |
96 | break; | |
97 | default: | |
98 | debug("EXYNOS_TMU: Unknown TMU state\n"); | |
99 | } | |
100 | } | |
101 | #endif | |
102 | ||
103 | int board_init(void) | |
104 | { | |
105 | gd->bd->bi_boot_params = (PHYS_SDRAM_1 + 0x100UL); | |
106 | #if defined CONFIG_EXYNOS_TMU | |
107 | if (tmu_init(gd->fdt_blob) != TMU_STATUS_NORMAL) { | |
108 | debug("%s: Failed to init TMU\n", __func__); | |
109 | return -1; | |
110 | } | |
111 | boot_temp_check(); | |
112 | #endif | |
24c904f3 | 113 | #if CONFIG_VAL(SYS_MEM_TOP_HIDE) |
a0643e22 | 114 | /* The last few MB of memory can be reserved for secure firmware */ |
24c904f3 | 115 | ulong size = CONFIG_SYS_MEM_TOP_HIDE; |
71ebb335 | 116 | |
a0643e22 PM |
117 | gd->ram_size -= size; |
118 | gd->bd->bi_dram[CONFIG_NR_DRAM_BANKS - 1].size -= size; | |
119 | #endif | |
4f9c7a9f TR |
120 | exynos_init(); |
121 | ||
122 | return 0; | |
71ebb335 RS |
123 | } |
124 | ||
125 | int dram_init(void) | |
126 | { | |
c8b71a35 | 127 | unsigned int i; |
6c15a2a9 | 128 | unsigned long addr; |
71ebb335 RS |
129 | |
130 | for (i = 0; i < CONFIG_NR_DRAM_BANKS; i++) { | |
aa6e94de | 131 | addr = CFG_SYS_SDRAM_BASE + (i * SDRAM_BANK_SIZE); |
71ebb335 RS |
132 | gd->ram_size += get_ram_size((long *)addr, SDRAM_BANK_SIZE); |
133 | } | |
134 | return 0; | |
135 | } | |
136 | ||
76b00aca | 137 | int dram_init_banksize(void) |
71ebb335 | 138 | { |
c8b71a35 | 139 | unsigned int i; |
6c15a2a9 | 140 | unsigned long addr, size; |
71ebb335 RS |
141 | |
142 | for (i = 0; i < CONFIG_NR_DRAM_BANKS; i++) { | |
aa6e94de | 143 | addr = CFG_SYS_SDRAM_BASE + (i * SDRAM_BANK_SIZE); |
71ebb335 RS |
144 | size = get_ram_size((long *)addr, SDRAM_BANK_SIZE); |
145 | ||
146 | gd->bd->bi_dram[i].start = addr; | |
147 | gd->bd->bi_dram[i].size = size; | |
148 | } | |
76b00aca SG |
149 | |
150 | return 0; | |
71ebb335 RS |
151 | } |
152 | ||
153 | static int board_uart_init(void) | |
154 | { | |
6c15a2a9 | 155 | #ifndef CONFIG_PINCTRL_EXYNOS |
71ebb335 RS |
156 | int err, uart_id, ret = 0; |
157 | ||
158 | for (uart_id = PERIPH_ID_UART0; uart_id <= PERIPH_ID_UART3; uart_id++) { | |
159 | err = exynos_pinmux_config(uart_id, PINMUX_FLAG_NONE); | |
160 | if (err) { | |
161 | debug("UART%d not configured\n", | |
162 | (uart_id - PERIPH_ID_UART0)); | |
163 | ret |= err; | |
164 | } | |
165 | } | |
166 | return ret; | |
6c15a2a9 TA |
167 | #else |
168 | return 0; | |
169 | #endif | |
71ebb335 RS |
170 | } |
171 | ||
172 | #ifdef CONFIG_BOARD_EARLY_INIT_F | |
173 | int board_early_init_f(void) | |
174 | { | |
175 | int err; | |
d50c41ef PM |
176 | #ifdef CONFIG_BOARD_TYPES |
177 | set_board_type(); | |
178 | #endif | |
71ebb335 RS |
179 | err = board_uart_init(); |
180 | if (err) { | |
181 | debug("UART init failed\n"); | |
182 | return err; | |
183 | } | |
184 | ||
8e5e1e6a | 185 | return exynos_early_init_f(); |
71ebb335 RS |
186 | } |
187 | #endif | |
188 | ||
9d8665b7 | 189 | #if CONFIG_IS_ENABLED(POWER_LEGACY) || CONFIG_IS_ENABLED(DM_PMIC) |
71ebb335 RS |
190 | int power_init_board(void) |
191 | { | |
71ebb335 RS |
192 | set_ps_hold_ctrl(); |
193 | ||
8e5e1e6a | 194 | return exynos_power_init(); |
71ebb335 RS |
195 | } |
196 | #endif | |
197 | ||
345a5368 | 198 | #if defined(CONFIG_DISPLAY_BOARDINFO) || defined(CONFIG_DISPLAY_BOARDINFO_LATE) |
4c1dd998 PW |
199 | int checkboard(void) |
200 | { | |
a42ff927 | 201 | if (IS_ENABLED(CONFIG_BOARD_TYPES)) { |
e3ee4be3 KK |
202 | const char *board_info; |
203 | ||
204 | if (IS_ENABLED(CONFIG_DISPLAY_BOARDINFO_LATE)) { | |
205 | /* | |
206 | * Printing type requires having revision, although | |
207 | * this will succeed only if done late. | |
208 | * Otherwise revision will be set in misc_init_r(). | |
209 | */ | |
210 | set_board_revision(); | |
211 | } | |
212 | ||
213 | board_info = get_board_type(); | |
a42ff927 SG |
214 | |
215 | if (board_info) | |
216 | printf("Type: %s\n", board_info); | |
217 | } | |
4c1dd998 | 218 | |
4c1dd998 PW |
219 | return 0; |
220 | } | |
71ebb335 RS |
221 | #endif |
222 | ||
223 | #ifdef CONFIG_BOARD_LATE_INIT | |
224 | int board_late_init(void) | |
225 | { | |
a2a63a35 SG |
226 | struct udevice *dev; |
227 | int ret; | |
86c88711 MS |
228 | int mmcbootdev = get_boot_mmc_dev(); |
229 | char mmcbootdev_str[16]; | |
71ebb335 | 230 | |
a2a63a35 | 231 | ret = uclass_first_device_err(UCLASS_CROS_EC, &dev); |
c9901bd2 | 232 | if (ret && ret != -ENODEV && ret != -EPFNOSUPPORT) { |
71ebb335 RS |
233 | /* Force console on */ |
234 | gd->flags &= ~GD_FLG_SILENT; | |
235 | ||
a2a63a35 | 236 | printf("cros-ec communications failure %d\n", ret); |
71ebb335 RS |
237 | puts("\nPlease reset with Power+Refresh\n\n"); |
238 | panic("Cannot init cros-ec device"); | |
239 | return -1; | |
240 | } | |
86c88711 MS |
241 | |
242 | printf("Boot device: MMC(%u)\n", mmcbootdev); | |
243 | sprintf(mmcbootdev_str, "%u", mmcbootdev); | |
244 | env_set("mmcbootdev", mmcbootdev_str); | |
245 | ||
71ebb335 RS |
246 | return 0; |
247 | } | |
248 | #endif | |
249 | ||
431a1c56 PW |
250 | #ifdef CONFIG_MISC_INIT_R |
251 | int misc_init_r(void) | |
252 | { | |
e3ee4be3 KK |
253 | if (IS_ENABLED(CONFIG_BOARD_TYPES) && |
254 | !IS_ENABLED(CONFIG_DISPLAY_BOARDINFO_LATE)) { | |
255 | /* | |
256 | * If revision was not set by late display boardinfo, | |
257 | * set it here. At this point regulators should be already | |
258 | * available. | |
259 | */ | |
260 | set_board_revision(); | |
261 | } | |
262 | ||
431a1c56 PW |
263 | #ifdef CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG |
264 | set_board_info(); | |
265 | #endif | |
431a1c56 PW |
266 | #ifdef CONFIG_CMD_BMP |
267 | if (panel_info.logo_on) | |
268 | draw_logo(); | |
269 | #endif | |
270 | return 0; | |
271 | } | |
272 | #endif | |
aa8e00fa JS |
273 | |
274 | void reset_misc(void) | |
275 | { | |
276 | struct gpio_desc gpio = {}; | |
277 | int node; | |
278 | ||
279 | node = fdt_node_offset_by_compatible(gd->fdt_blob, 0, | |
280 | "samsung,emmc-reset"); | |
281 | if (node < 0) | |
282 | return; | |
283 | ||
150c5afe SG |
284 | gpio_request_by_name_nodev(offset_to_ofnode(node), "reset-gpio", 0, |
285 | &gpio, GPIOD_IS_OUT); | |
aa8e00fa JS |
286 | |
287 | if (dm_gpio_is_valid(&gpio)) { | |
288 | /* | |
289 | * Reset eMMC | |
290 | * | |
291 | * FIXME: Need to optimize delay time. Minimum 1usec pulse is | |
292 | * required by 'JEDEC Standard No.84-A441' (eMMC) | |
293 | * document but real delay time is expected to greater | |
294 | * than 1usec. | |
295 | */ | |
296 | dm_gpio_set_value(&gpio, 0); | |
297 | mdelay(10); | |
298 | dm_gpio_set_value(&gpio, 1); | |
299 | } | |
300 | } | |
28f393cd ŁM |
301 | |
302 | int board_usb_cleanup(int index, enum usb_init_type init) | |
303 | { | |
302a7d00 JS |
304 | #ifdef CONFIG_USB_DWC3 |
305 | dwc3_uboot_exit(index); | |
306 | #endif | |
28f393cd ŁM |
307 | return 0; |
308 | } | |
86c88711 MS |
309 | |
310 | int mmc_get_env_dev(void) | |
311 | { | |
312 | return get_boot_mmc_dev(); | |
313 | } |