projects / J-u-boot.git / blame
| Commit | Line | Data |
|---|---|---|
| 83d290c5 | 1 | /* SPDX-License-Identifier: GPL-2.0+ */ |
| 980db8ca SL |
2 | /* |
| 3 | * LPC32xx DMA Controller Interface | |
| 4 | * | |
| 5 | * Copyright (C) 2008 by NXP Semiconductors | |
| 6 | * @Author: Kevin Wells | |
| 7 | * @Descr: Definitions for LPC3250 chip | |
| 8 | * @References: NXP LPC3250 User's Guide | |
| 980db8ca SL |
9 | */ |
| 10 | ||
| 11 | #ifndef _LPC32XX_DMA_H | |
| 12 | #define _LPC32XX_DMA_H | |
| 13 | ||
| 980db8ca SL |
14 | /* |
| 15 | * DMA linked list structure used with a channel's LLI register; | |
| 16 | * refer to UM10326, "LPC32x0 and LPC32x0/01 User manual" - Rev. 3 | |
| 17 | * tables 84, 85, 86 & 87 for details. | |
| 18 | */ | |
| 19 | struct lpc32xx_dmac_ll { | |
| 20 | u32 dma_src; | |
| 21 | u32 dma_dest; | |
| 22 | u32 next_lli; | |
| 23 | u32 next_ctrl; | |
| 24 | }; | |
| 25 | ||
| 26 | /* control register definitions */ | |
| 27 | #define DMAC_CHAN_INT_TC_EN (1 << 31) /* channel terminal count interrupt */ | |
| 28 | #define DMAC_CHAN_DEST_AUTOINC (1 << 27) /* automatic destination increment */ | |
| 29 | #define DMAC_CHAN_SRC_AUTOINC (1 << 26) /* automatic source increment */ | |
| 30 | #define DMAC_CHAN_DEST_AHB1 (1 << 25) /* AHB1 master for dest. transfer */ | |
| 31 | #define DMAC_CHAN_DEST_WIDTH_32 (1 << 22) /* Destination data width selection */ | |
| 32 | #define DMAC_CHAN_SRC_WIDTH_32 (1 << 19) /* Source data width selection */ | |
| 33 | #define DMAC_CHAN_DEST_BURST_1 0 | |
| 34 | #define DMAC_CHAN_DEST_BURST_4 (1 << 15) /* Destination data burst size */ | |
| 35 | #define DMAC_CHAN_SRC_BURST_1 0 | |
| 36 | #define DMAC_CHAN_SRC_BURST_4 (1 << 12) /* Source data burst size */ | |
| 37 | ||
| 38 | /* | |
| 39 | * config_ch register definitions | |
| 40 | * DMAC_CHAN_FLOW_D_xxx: flow control with DMA as the controller | |
| 41 | * DMAC_DEST_PERIP: Macro for loading destination peripheral | |
| 42 | * DMAC_SRC_PERIP: Macro for loading source peripheral | |
| 43 | */ | |
| 44 | #define DMAC_CHAN_FLOW_D_M2P (0x1 << 11) | |
| 45 | #define DMAC_CHAN_FLOW_D_P2M (0x2 << 11) | |
| 46 | #define DMAC_DEST_PERIP(n) (((n) & 0x1F) << 6) | |
| 47 | #define DMAC_SRC_PERIP(n) (((n) & 0x1F) << 1) | |
| 48 | ||
| 49 | /* | |
| 50 | * config_ch register definitions | |
| 51 | * (source and destination peripheral ID numbers). | |
| 52 | * These can be used with the DMAC_DEST_PERIP and DMAC_SRC_PERIP macros. | |
| 53 | */ | |
| 54 | #define DMA_PERID_NAND1 1 | |
| 55 | ||
| 56 | /* Channel enable bit */ | |
| 57 | #define DMAC_CHAN_ENABLE (1 << 0) | |
| 58 | ||
| 59 | int lpc32xx_dma_get_channel(void); | |
| 60 | int lpc32xx_dma_start_xfer(unsigned int channel, | |
| 61 | const struct lpc32xx_dmac_ll *desc, u32 config); | |
| 62 | int lpc32xx_dma_wait_status(unsigned int channel); | |
| 63 | ||
| 64 | #endif /* _LPC32XX_DMA_H */ |