[J-u-boot.git] / arch / arm / dts / uniphier-ld20-ref.dts

// SPDX-License-Identifier: GPL-2.0+ OR MIT
//
// Device Tree Source for UniPhier LD20 Reference Board
//
// Copyright (C) 2015-2016 Socionext Inc.
//   Author: Masahiro Yamada <[email protected]>

/dts-v1/;
#include "uniphier-ld20.dtsi"
#include "uniphier-ref-daughter.dtsi"
#include "uniphier-support-card.dtsi"

/ {
	model = "UniPhier LD20 Reference Board";
	compatible = "socionext,uniphier-ld20-ref", "socionext,uniphier-ld20";

	chosen {
		stdout-path = "serial0:115200n8";
	};

	aliases {
		serial0 = &serial0;
		serial1 = &serialsc;
		serial2 = &serial2;
		serial3 = &serial3;
		i2c0 = &i2c0;
		i2c1 = &i2c1;
		i2c2 = &i2c2;
		i2c3 = &i2c3;
		i2c4 = &i2c4;
		i2c5 = &i2c5;
		ethernet0 = &eth;
	};

	memory@80000000 {
		device_type = "memory";
		reg = <0 0x80000000 0 0xc0000000>;
	};
};

&ethsc {
	interrupts = <0 8>;
};

&serialsc {
	interrupts = <0 8>;
};

&serial0 {
	status = "okay";
};

&gpio {
	xirq0 {
		gpio-hog;
		gpios = <UNIPHIER_GPIO_IRQ(0) 0>;
		input;
	};
};

&i2c0 {
	status = "okay";
};

&eth {
	status = "okay";
	phy-handle = <&ethphy>;
};

&mdio {
	ethphy: ethernet-phy@0 {
		reg = <0>;
	};
};

&pinctrl_ether_rgmii {
	tx {
		pins = "RGMII_TXCLK", "RGMII_TXD0", "RGMII_TXD1",
		       "RGMII_TXD2", "RGMII_TXD3", "RGMII_TXCTL";
		drive-strength = <9>;
	};
};

&usb {
	status = "okay";
};
Commit	Line	Data
3e98fc12 MY	1	// SPDX-License-Identifier: GPL-2.0+ OR MIT
	2	//
	3	// Device Tree Source for UniPhier LD20 Reference Board
	4	//
	5	// Copyright (C) 2015-2016 Socionext Inc.
	6	// Author: Masahiro Yamada <[email protected]>
7bdd1554 MY	7
7bdd1554 MY	8	/dts-v1/;
6c9e46ef MY	9	#include "uniphier-ld20.dtsi"
	10	#include "uniphier-ref-daughter.dtsi"
	11	#include "uniphier-support-card.dtsi"
7bdd1554 MY	12
7bdd1554 MY	13	/ {
52159d27 MY	14	model = "UniPhier LD20 Reference Board";
52159d27 MY	15	compatible = "socionext,uniphier-ld20-ref", "socionext,uniphier-ld20";
7bdd1554	16
7ad79c12 MY	17	chosen {
	18	stdout-path = "serial0:115200n8";
	19	};
	20
7bdd1554 MY	21	aliases {
7bdd1554 MY	22	serial0 = &serial0;
65282edb	23	serial1 = &serialsc;
7bdd1554 MY	24	serial2 = &serial2;
	25	serial3 = &serial3;
	26	i2c0 = &i2c0;
	27	i2c1 = &i2c1;
	28	i2c2 = &i2c2;
	29	i2c3 = &i2c3;
	30	i2c4 = &i2c4;
	31	i2c5 = &i2c5;
08520333	32	ethernet0 = ð
7bdd1554	33	};
6c64d50e	34
7ad79c12	35	memory@80000000 {
6c64d50e MY	36	device_type = "memory";
	37	reg = <0 0x80000000 0 0xc0000000>;
	38	};
7bdd1554 MY	39	};
	40
	41	&ethsc {
b443fb42	42	interrupts = <0 8>;
7bdd1554 MY	43	};
7bdd1554 MY	44
65282edb MY	45	&serialsc {
	46	interrupts = <0 8>;
	47	};
	48
7bdd1554 MY	49	&serial0 {
	50	status = "okay";
	51	};
	52
b443fb42 MY	53	&gpio {
	54	xirq0 {
	55	gpio-hog;
	56	gpios = <UNIPHIER_GPIO_IRQ(0) 0>;
	57	input;
	58	};
	59	};
	60
7bdd1554 MY	61	&i2c0 {
	62	status = "okay";
	63	};
3e98fc12 MY	64
	65	&eth {
	66	status = "okay";
	67	phy-handle = <&ethphy>;
	68	};
	69
	70	&mdio {
65282edb	71	ethphy: ethernet-phy@0 {
3e98fc12 MY	72	reg = <0>;
	73	};
	74	};
c3d3e2a1 MY	75
	76	&pinctrl_ether_rgmii {
	77	tx {
	78	pins = "RGMII_TXCLK", "RGMII_TXD0", "RGMII_TXD1",
	79	"RGMII_TXD2", "RGMII_TXD3", "RGMII_TXCTL";
	80	drive-strength = <9>;
	81	};
	82	};
2001a81c MY	83
	84	&usb {
	85	status = "okay";
	86	};