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Commit | Line | Data |
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623a8c81 SR |
1 | // SPDX-License-Identifier: GPL-2.0 |
2 | /dts-v1/; | |
3 | ||
4 | #include "tegra30-lg-x3.dtsi" | |
5 | ||
6 | / { | |
7 | model = "LG Optimus 4X HD"; | |
8 | compatible = "lge,p880", "nvidia,tegra30"; | |
9 | ||
10 | aliases { | |
11 | mmc1 = &sdmmc3; /* uSD slot */ | |
12 | }; | |
13 | ||
fd211f85 SR |
14 | pinmux@70000868 { |
15 | state_default: pinmux { | |
16 | /* WLAN SDIO pinmux */ | |
17 | host_wlan_wake { | |
18 | nvidia,pins = "pu4"; | |
19 | nvidia,function = "pwm1"; | |
20 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; | |
21 | nvidia,tristate = <TEGRA_PIN_ENABLE>; | |
22 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; | |
23 | }; | |
24 | ||
25 | /* GNSS UART-B pinmux */ | |
26 | uartb_rxd { | |
27 | nvidia,pins = "uart2_rxd_pc3"; | |
28 | nvidia,function = "uartb"; | |
29 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; | |
30 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | |
31 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; | |
32 | }; | |
33 | uartb_txd { | |
34 | nvidia,pins = "uart2_txd_pc2"; | |
35 | nvidia,function = "uartb"; | |
36 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; | |
37 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | |
38 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; | |
39 | }; | |
40 | gps_reset { | |
41 | nvidia,pins = "kb_row7_pr7"; | |
42 | nvidia,function = "kbc"; | |
43 | nvidia,pull = <TEGRA_PIN_PULL_UP>; | |
44 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | |
45 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; | |
46 | }; | |
47 | ||
48 | /* MicroSD pinmux */ | |
49 | sdmmc3_clk { | |
50 | nvidia,pins = "sdmmc3_clk_pa6"; | |
51 | nvidia,function = "sdmmc3"; | |
52 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; | |
53 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | |
54 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; | |
55 | }; | |
56 | sdmmc3_data { | |
57 | nvidia,pins = "sdmmc3_cmd_pa7", | |
58 | "sdmmc3_dat0_pb7", | |
59 | "sdmmc3_dat1_pb6", | |
60 | "sdmmc3_dat2_pb5", | |
61 | "sdmmc3_dat3_pb4"; | |
62 | nvidia,function = "sdmmc3"; | |
63 | nvidia,pull = <TEGRA_PIN_PULL_UP>; | |
64 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | |
65 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; | |
66 | }; | |
67 | microsd_detect { | |
68 | nvidia,pins = "clk2_out_pw5"; | |
69 | nvidia,function = "rsvd2"; | |
70 | nvidia,pull = <TEGRA_PIN_PULL_UP>; | |
71 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | |
72 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; | |
73 | }; | |
74 | ||
75 | /* GPIO keys pinmux */ | |
76 | volume_up { | |
77 | nvidia,pins = "ulpi_data6_po7"; | |
78 | nvidia,function = "spi2"; | |
79 | nvidia,pull = <TEGRA_PIN_PULL_UP>; | |
80 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | |
81 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; | |
82 | }; | |
83 | ||
84 | /* Sensors pinmux */ | |
85 | current_alert_irq { | |
86 | nvidia,pins = "uart2_rts_n_pj6"; | |
87 | nvidia,function = "uartb"; | |
88 | nvidia,pull = <TEGRA_PIN_PULL_UP>; | |
89 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | |
90 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; | |
91 | }; | |
92 | ||
93 | /* AUDIO pinmux */ | |
94 | sub_mic_ldo { | |
95 | nvidia,pins = "gmi_cs7_n_pi6"; | |
96 | nvidia,function = "gmi"; | |
97 | nvidia,pull = <TEGRA_PIN_PULL_DOWN>; | |
98 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | |
99 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; | |
100 | }; | |
101 | }; | |
102 | }; | |
103 | ||
623a8c81 SR |
104 | sdmmc3: sdhci@78000400 { |
105 | status = "okay"; | |
106 | bus-width = <4>; | |
107 | ||
108 | cd-gpios = <&gpio TEGRA_GPIO(W, 5) GPIO_ACTIVE_LOW>; | |
109 | ||
110 | vmmc-supply = <&vdd_usd>; | |
111 | vqmmc-supply = <&vdd_1v8_vio>; | |
112 | }; | |
113 | ||
114 | gpio-keys { | |
115 | key-volume-up { | |
116 | label = "Volume Up"; | |
117 | gpios = <&gpio TEGRA_GPIO(O, 7) GPIO_ACTIVE_LOW>; | |
118 | linux,code = <KEY_UP>; | |
119 | }; | |
120 | }; | |
121 | ||
122 | panel: panel { | |
123 | compatible = "jdi,dx12d100vm0eaa"; | |
124 | ||
125 | enable-gpios = <&gpio TEGRA_GPIO(Y, 0) GPIO_ACTIVE_HIGH>; | |
126 | reset-gpios = <&gpio TEGRA_GPIO(W, 0) GPIO_ACTIVE_HIGH>; | |
127 | ||
128 | backlight = <&backlight>; | |
129 | }; | |
130 | }; |