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Merge tag 'u-boot-imx-master-20250127' of https://gitlab.denx.de/u-boot/custodians...
[J-u-boot.git] / arch / arm / dts / sun50i-h6.dtsi
CommitLineData
750cabc8
JS		 1// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
2// Copyright (C) 2017 Icenowy Zheng <[email protected]>
6f796a9b
IZ		 3
4#include <dt-bindings/interrupt-controller/arm-gic.h>
5#include <dt-bindings/clock/sun50i-h6-ccu.h>
6#include <dt-bindings/clock/sun50i-h6-r-ccu.h>
7f53f509 7#include <dt-bindings/clock/sun6i-rtc.h>
a93a5504
JT		 8#include <dt-bindings/clock/sun8i-de2.h>
9#include <dt-bindings/clock/sun8i-tcon-top.h>
6f796a9b
IZ		 10#include <dt-bindings/reset/sun50i-h6-ccu.h>
11#include <dt-bindings/reset/sun50i-h6-r-ccu.h>
a93a5504 12#include <dt-bindings/reset/sun8i-de2.h>
750cabc8 13#include <dt-bindings/thermal/thermal.h>
6f796a9b
IZ		 14
15/ {
16 interrupt-parent = <&gic>;
17 #address-cells = <1>;
18 #size-cells = <1>;
19
20 cpus {
21 #address-cells = <1>;
22 #size-cells = <0>;
23
24 cpu0: cpu@0 {
a93a5504 25 compatible = "arm,cortex-a53";
6f796a9b
IZ		 26 device_type = "cpu";
27 reg = <0>;
28 enable-method = "psci";
750cabc8
JS		 29 clocks = <&ccu CLK_CPUX>;
30 clock-latency-ns = <244144>; /* 8 32k periods */
31 #cooling-cells = <2>;
6f796a9b
IZ		 32 };
33
34 cpu1: cpu@1 {
a93a5504 35 compatible = "arm,cortex-a53";
6f796a9b
IZ		 36 device_type = "cpu";
37 reg = <1>;
38 enable-method = "psci";
750cabc8
JS		 39 clocks = <&ccu CLK_CPUX>;
40 clock-latency-ns = <244144>; /* 8 32k periods */
41 #cooling-cells = <2>;
6f796a9b
IZ		 42 };
43
44 cpu2: cpu@2 {
a93a5504 45 compatible = "arm,cortex-a53";
6f796a9b
IZ		 46 device_type = "cpu";
47 reg = <2>;
48 enable-method = "psci";
750cabc8
JS		 49 clocks = <&ccu CLK_CPUX>;
50 clock-latency-ns = <244144>; /* 8 32k periods */
51 #cooling-cells = <2>;
6f796a9b
IZ		 52 };
53
54 cpu3: cpu@3 {
a93a5504 55 compatible = "arm,cortex-a53";
6f796a9b
IZ		 56 device_type = "cpu";
57 reg = <3>;
58 enable-method = "psci";
750cabc8
JS		 59 clocks = <&ccu CLK_CPUX>;
60 clock-latency-ns = <244144>; /* 8 32k periods */
61 #cooling-cells = <2>;
6f796a9b
IZ		 62 };
63 };
64
a93a5504
JT		 65 de: display-engine {
66 compatible = "allwinner,sun50i-h6-display-engine";
67 allwinner,pipelines = <&mixer0>;
68 status = "disabled";
69 };
70
70fc8449 71 osc24M: osc24M-clk {
6f796a9b
IZ		 72 #clock-cells = <0>;
73 compatible = "fixed-clock";
74 clock-frequency = <24000000>;
75 clock-output-names = "osc24M";
76 };
77
750cabc8
JS		 78 pmu {
79 compatible = "arm,cortex-a53-pmu";
80 interrupts = <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>,
81 <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>,
82 <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>,
83 <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>;
84 interrupt-affinity = <&cpu0>, <&cpu1>, <&cpu2>, <&cpu3>;
6f796a9b
IZ		 85 };
86
87 psci {
88 compatible = "arm,psci-0.2";
89 method = "smc";
90 };
91
92 timer {
93 compatible = "arm,armv8-timer";
750cabc8 94 arm,no-tick-in-suspend;
6f796a9b
IZ		 95 interrupts = <GIC_PPI 13
96 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>,
97 <GIC_PPI 14
98 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>,
99 <GIC_PPI 11
100 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>,
101 <GIC_PPI 10
102 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
103 };
104
105 soc {
106 compatible = "simple-bus";
107 #address-cells = <1>;
108 #size-cells = <1>;
109 ranges;
110
cf05b4b8 111 bus@1000000 {
a93a5504
JT		 112 compatible = "allwinner,sun50i-h6-de3",
113 "allwinner,sun50i-a64-de2";
114 reg = <0x1000000 0x400000>;
115 allwinner,sram = <&de2_sram 1>;
116 #address-cells = <1>;
117 #size-cells = <1>;
118 ranges = <0 0x1000000 0x400000>;
119
120 display_clocks: clock@0 {
121 compatible = "allwinner,sun50i-h6-de3-clk";
122 reg = <0x0 0x10000>;
ce00370b
SH		 123 clocks = <&ccu CLK_BUS_DE>,
124 <&ccu CLK_DE>;
125 clock-names = "bus",
126 "mod";
a93a5504
JT		 127 resets = <&ccu RST_BUS_DE>;
128 #clock-cells = <1>;
129 #reset-cells = <1>;
130 };
131
132 mixer0: mixer@100000 {
133 compatible = "allwinner,sun50i-h6-de3-mixer-0";
134 reg = <0x100000 0x100000>;
135 clocks = <&display_clocks CLK_BUS_MIXER0>,
136 <&display_clocks CLK_MIXER0>;
137 clock-names = "bus",
138 "mod";
139 resets = <&display_clocks RST_MIXER0>;
750cabc8 140 iommus = <&iommu 0>;
a93a5504
JT		 141
142 ports {
143 #address-cells = <1>;
144 #size-cells = <0>;
145
146 mixer0_out: port@1 {
147 reg = <1>;
148
149 mixer0_out_tcon_top_mixer0: endpoint {
150 remote-endpoint = <&tcon_top_mixer0_in_mixer0>;
151 };
152 };
153 };
154 };
155 };
156
ce00370b
SH		 157 video-codec-g2@1c00000 {
158 compatible = "allwinner,sun50i-h6-vpu-g2";
159 reg = <0x01c00000 0x1000>;
160 interrupts = <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>;
161 clocks = <&ccu CLK_BUS_VP9>, <&ccu CLK_VP9>;
162 clock-names = "bus", "mod";
163 resets = <&ccu RST_BUS_VP9>;
8e2c0ee3 164 iommus = <&iommu 5>;
ce00370b
SH		 165 };
166
a93a5504
JT		 167 video-codec@1c0e000 {
168 compatible = "allwinner,sun50i-h6-video-engine";
169 reg = <0x01c0e000 0x2000>;
170 clocks = <&ccu CLK_BUS_VE>, <&ccu CLK_VE>,
171 <&ccu CLK_MBUS_VE>;
172 clock-names = "ahb", "mod", "ram";
173 resets = <&ccu RST_BUS_VE>;
174 interrupts = <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>;
175 allwinner,sram = <&ve_sram 1>;
750cabc8
JS		 176 iommus = <&iommu 3>;
177 };
178
179 gpu: gpu@1800000 {
180 compatible = "allwinner,sun50i-h6-mali",
181 "arm,mali-t720";
182 reg = <0x01800000 0x4000>;
183 interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>,
184 <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>,
185 <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
186 interrupt-names = "job", "mmu", "gpu";
187 clocks = <&ccu CLK_GPU>, <&ccu CLK_BUS_GPU>;
188 clock-names = "core", "bus";
189 resets = <&ccu RST_BUS_GPU>;
8e2c0ee3 190 #cooling-cells = <2>;
750cabc8
JS		 191 status = "disabled";
192 };
193
194 crypto: crypto@1904000 {
195 compatible = "allwinner,sun50i-h6-crypto";
196 reg = <0x01904000 0x1000>;
197 interrupts = <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>;
198 clocks = <&ccu CLK_BUS_CE>, <&ccu CLK_CE>, <&ccu CLK_MBUS_CE>;
199 clock-names = "bus", "mod", "ram";
200 resets = <&ccu RST_BUS_CE>;
a93a5504
JT		 201 };
202
203 syscon: syscon@3000000 {
204 compatible = "allwinner,sun50i-h6-system-control",
205 "allwinner,sun50i-a64-system-control";
206 reg = <0x03000000 0x1000>;
207 #address-cells = <1>;
208 #size-cells = <1>;
209 ranges;
210
211 sram_c: sram@28000 {
212 compatible = "mmio-sram";
213 reg = <0x00028000 0x1e000>;
214 #address-cells = <1>;
215 #size-cells = <1>;
216 ranges = <0 0x00028000 0x1e000>;
217
218 de2_sram: sram-section@0 {
219 compatible = "allwinner,sun50i-h6-sram-c",
220 "allwinner,sun50i-a64-sram-c";
221 reg = <0x0000 0x1e000>;
222 };
223 };
224
225 sram_c1: sram@1a00000 {
226 compatible = "mmio-sram";
227 reg = <0x01a00000 0x200000>;
228 #address-cells = <1>;
229 #size-cells = <1>;
230 ranges = <0 0x01a00000 0x200000>;
231
232 ve_sram: sram-section@0 {
233 compatible = "allwinner,sun50i-h6-sram-c1",
234 "allwinner,sun4i-a10-sram-c1";
235 reg = <0x000000 0x200000>;
236 };
237 };
238 };
239
6f796a9b
IZ		 240 ccu: clock@3001000 {
241 compatible = "allwinner,sun50i-h6-ccu";
242 reg = <0x03001000 0x1000>;
7f53f509 243 clocks = <&osc24M>, <&rtc CLK_OSC32K>, <&rtc CLK_IOSC>;
6f796a9b
IZ		 244 clock-names = "hosc", "losc", "iosc";
245 #clock-cells = <1>;
246 #reset-cells = <1>;
247 };
248
cf05b4b8
CP		 249 dma: dma-controller@3002000 {
250 compatible = "allwinner,sun50i-h6-dma";
251 reg = <0x03002000 0x1000>;
252 interrupts = <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>;
253 clocks = <&ccu CLK_BUS_DMA>, <&ccu CLK_MBUS_DMA>;
254 clock-names = "bus", "mbus";
255 dma-channels = <16>;
256 dma-requests = <46>;
257 resets = <&ccu RST_BUS_DMA>;
258 #dma-cells = <1>;
259 };
260
750cabc8
JS		 261 msgbox: mailbox@3003000 {
262 compatible = "allwinner,sun50i-h6-msgbox",
263 "allwinner,sun6i-a31-msgbox";
264 reg = <0x03003000 0x1000>;
265 clocks = <&ccu CLK_BUS_MSGBOX>;
266 resets = <&ccu RST_BUS_MSGBOX>;
267 interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>;
268 #mbox-cells = <1>;
269 };
270
271 sid: efuse@3006000 {
a93a5504
JT		 272 compatible = "allwinner,sun50i-h6-sid";
273 reg = <0x03006000 0x400>;
750cabc8
JS		 274 #address-cells = <1>;
275 #size-cells = <1>;
276
277 ths_calibration: thermal-sensor-calibration@14 {
278 reg = <0x14 0x8>;
279 };
280
281 cpu_speed_grade: cpu-speed-grade@1c {
282 reg = <0x1c 0x4>;
283 };
6f796a9b
IZ		 284 };
285
ce00370b
SH		 286 timer@3009000 {
287 compatible = "allwinner,sun50i-h6-timer",
288 "allwinner,sun8i-a23-timer";
289 reg = <0x03009000 0xa0>;
290 interrupts = <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>,
291 <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>;
292 clocks = <&osc24M>;
293 };
294
cf05b4b8
CP		 295 watchdog: watchdog@30090a0 {
296 compatible = "allwinner,sun50i-h6-wdt",
297 "allwinner,sun6i-a31-wdt";
298 reg = <0x030090a0 0x20>;
299 interrupts = <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>;
750cabc8 300 clocks = <&osc24M>;
cf05b4b8
CP		 301 /* Broken on some H6 boards */
302 status = "disabled";
303 };
304
750cabc8
JS		 305 pwm: pwm@300a000 {
306 compatible = "allwinner,sun50i-h6-pwm";
307 reg = <0x0300a000 0x400>;
308 clocks = <&osc24M>, <&ccu CLK_BUS_PWM>;
309 clock-names = "mod", "bus";
310 resets = <&ccu RST_BUS_PWM>;
311 #pwm-cells = <3>;
312 status = "disabled";
313 };
314
6f796a9b
IZ		 315 pio: pinctrl@300b000 {
316 compatible = "allwinner,sun50i-h6-pinctrl";
317 reg = <0x0300b000 0x400>;
318 interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>,
319 <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>,
320 <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>,
321 <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>;
7f53f509 322 clocks = <&ccu CLK_APB1>, <&osc24M>, <&rtc CLK_OSC32K>;
6f796a9b
IZ		 323 clock-names = "apb", "hosc", "losc";
324 gpio-controller;
325 #gpio-cells = <3>;
326 interrupt-controller;
327 #interrupt-cells = <3>;
328
a93a5504
JT		 329 ext_rgmii_pins: rgmii-pins {
330 pins = "PD0", "PD1", "PD2", "PD3", "PD4",
331 "PD5", "PD7", "PD8", "PD9", "PD10",
332 "PD11", "PD12", "PD13", "PD19", "PD20";
333 function = "emac";
334 drive-strength = <40>;
335 };
336
337 hdmi_pins: hdmi-pins {
338 pins = "PH8", "PH9", "PH10";
339 function = "hdmi";
340 };
341
750cabc8
JS		 342 i2c0_pins: i2c0-pins {
343 pins = "PD25", "PD26";
344 function = "i2c0";
345 };
346
347 i2c1_pins: i2c1-pins {
348 pins = "PH5", "PH6";
349 function = "i2c1";
350 };
351
352 i2c2_pins: i2c2-pins {
353 pins = "PD23", "PD24";
354 function = "i2c2";
355 };
356
6f796a9b
IZ		 357 mmc0_pins: mmc0-pins {
358 pins = "PF0", "PF1", "PF2", "PF3",
359 "PF4", "PF5";
360 function = "mmc0";
361 drive-strength = <30>;
362 bias-pull-up;
363 };
364
750cabc8 365 /omit-if-no-ref/
cf05b4b8
CP		 366 mmc1_pins: mmc1-pins {
367 pins = "PG0", "PG1", "PG2", "PG3",
368 "PG4", "PG5";
369 function = "mmc1";
370 drive-strength = <30>;
371 bias-pull-up;
372 };
373
6f796a9b
IZ		 374 mmc2_pins: mmc2-pins {
375 pins = "PC1", "PC4", "PC5", "PC6",
376 "PC7", "PC8", "PC9", "PC10",
377 "PC11", "PC12", "PC13", "PC14";
378 function = "mmc2";
379 drive-strength = <30>;
380 bias-pull-up;
381 };
382
750cabc8
JS		 383 /omit-if-no-ref/
384 spi0_pins: spi0-pins {
385 pins = "PC0", "PC2", "PC3";
386 function = "spi0";
387 };
388
389 /* pin shared with MMC2-CMD (eMMC) */
390 /omit-if-no-ref/
391 spi0_cs_pin: spi0-cs-pin {
392 pins = "PC5";
393 function = "spi0";
394 };
395
396 /omit-if-no-ref/
397 spi1_pins: spi1-pins {
398 pins = "PH4", "PH5", "PH6";
399 function = "spi1";
400 };
401
402 /omit-if-no-ref/
403 spi1_cs_pin: spi1-cs-pin {
404 pins = "PH3";
405 function = "spi1";
406 };
407
cee40d66 408 /omit-if-no-ref/
750cabc8
JS		 409 spdif_tx_pin: spdif-tx-pin {
410 pins = "PH7";
411 function = "spdif";
412 };
413
a93a5504 414 uart0_ph_pins: uart0-ph-pins {
6f796a9b
IZ		 415 pins = "PH0", "PH1";
416 function = "uart0";
417 };
750cabc8
JS		 418
419 uart1_pins: uart1-pins {
420 pins = "PG6", "PG7";
421 function = "uart1";
422 };
423
424 uart1_rts_cts_pins: uart1-rts-cts-pins {
425 pins = "PG8", "PG9";
426 function = "uart1";
427 };
6f796a9b
IZ		 428 };
429
a93a5504
JT		 430 gic: interrupt-controller@3021000 {
431 compatible = "arm,gic-400";
432 reg = <0x03021000 0x1000>,
433 <0x03022000 0x2000>,
434 <0x03024000 0x2000>,
435 <0x03026000 0x2000>;
436 interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
437 interrupt-controller;
438 #interrupt-cells = <3>;
439 };
440
750cabc8
JS		 441 iommu: iommu@30f0000 {
442 compatible = "allwinner,sun50i-h6-iommu";
443 reg = <0x030f0000 0x10000>;
444 interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>;
445 clocks = <&ccu CLK_BUS_IOMMU>;
446 resets = <&ccu RST_BUS_IOMMU>;
447 #iommu-cells = <1>;
448 };
449
6f796a9b
IZ		 450 mmc0: mmc@4020000 {
451 compatible = "allwinner,sun50i-h6-mmc",
452 "allwinner,sun50i-a64-mmc";
453 reg = <0x04020000 0x1000>;
454 clocks = <&ccu CLK_BUS_MMC0>, <&ccu CLK_MMC0>;
455 clock-names = "ahb", "mmc";
456 resets = <&ccu RST_BUS_MMC0>;
457 reset-names = "ahb";
458 interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
a93a5504
JT		 459 pinctrl-names = "default";
460 pinctrl-0 = <&mmc0_pins>;
127e57c6 461 max-frequency = <150000000>;
6f796a9b
IZ		 462 status = "disabled";
463 #address-cells = <1>;
464 #size-cells = <0>;
465 };
466
467 mmc1: mmc@4021000 {
468 compatible = "allwinner,sun50i-h6-mmc",
469 "allwinner,sun50i-a64-mmc";
470 reg = <0x04021000 0x1000>;
471 clocks = <&ccu CLK_BUS_MMC1>, <&ccu CLK_MMC1>;
472 clock-names = "ahb", "mmc";
473 resets = <&ccu RST_BUS_MMC1>;
474 reset-names = "ahb";
475 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
cf05b4b8
CP		 476 pinctrl-names = "default";
477 pinctrl-0 = <&mmc1_pins>;
127e57c6 478 max-frequency = <150000000>;
6f796a9b
IZ		 479 status = "disabled";
480 #address-cells = <1>;
481 #size-cells = <0>;
482 };
483
484 mmc2: mmc@4022000 {
485 compatible = "allwinner,sun50i-h6-emmc",
486 "allwinner,sun50i-a64-emmc";
487 reg = <0x04022000 0x1000>;
488 clocks = <&ccu CLK_BUS_MMC2>, <&ccu CLK_MMC2>;
489 clock-names = "ahb", "mmc";
490 resets = <&ccu RST_BUS_MMC2>;
491 reset-names = "ahb";
492 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
a93a5504
JT		 493 pinctrl-names = "default";
494 pinctrl-0 = <&mmc2_pins>;
127e57c6 495 max-frequency = <150000000>;
6f796a9b
IZ		 496 status = "disabled";
497 #address-cells = <1>;
498 #size-cells = <0>;
499 };
500
501 uart0: serial@5000000 {
502 compatible = "snps,dw-apb-uart";
503 reg = <0x05000000 0x400>;
504 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>;
505 reg-shift = <2>;
506 reg-io-width = <4>;
507 clocks = <&ccu CLK_BUS_UART0>;
508 resets = <&ccu RST_BUS_UART0>;
509 status = "disabled";
510 };
511
512 uart1: serial@5000400 {
513 compatible = "snps,dw-apb-uart";
514 reg = <0x05000400 0x400>;
515 interrupts = <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>;
516 reg-shift = <2>;
517 reg-io-width = <4>;
518 clocks = <&ccu CLK_BUS_UART1>;
519 resets = <&ccu RST_BUS_UART1>;
520 status = "disabled";
521 };
522
523 uart2: serial@5000800 {
524 compatible = "snps,dw-apb-uart";
525 reg = <0x05000800 0x400>;
526 interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>;
527 reg-shift = <2>;
528 reg-io-width = <4>;
529 clocks = <&ccu CLK_BUS_UART2>;
530 resets = <&ccu RST_BUS_UART2>;
531 status = "disabled";
532 };
533
534 uart3: serial@5000c00 {
535 compatible = "snps,dw-apb-uart";
536 reg = <0x05000c00 0x400>;
537 interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>;
538 reg-shift = <2>;
539 reg-io-width = <4>;
540 clocks = <&ccu CLK_BUS_UART3>;
541 resets = <&ccu RST_BUS_UART3>;
542 status = "disabled";
543 };
544
750cabc8
JS		 545 i2c0: i2c@5002000 {
546 compatible = "allwinner,sun50i-h6-i2c",
547 "allwinner,sun6i-a31-i2c";
548 reg = <0x05002000 0x400>;
549 interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>;
550 clocks = <&ccu CLK_BUS_I2C0>;
551 resets = <&ccu RST_BUS_I2C0>;
552 pinctrl-names = "default";
553 pinctrl-0 = <&i2c0_pins>;
554 status = "disabled";
555 #address-cells = <1>;
556 #size-cells = <0>;
557 };
558
559 i2c1: i2c@5002400 {
560 compatible = "allwinner,sun50i-h6-i2c",
561 "allwinner,sun6i-a31-i2c";
562 reg = <0x05002400 0x400>;
563 interrupts = <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>;
564 clocks = <&ccu CLK_BUS_I2C1>;
565 resets = <&ccu RST_BUS_I2C1>;
566 pinctrl-names = "default";
567 pinctrl-0 = <&i2c1_pins>;
568 status = "disabled";
569 #address-cells = <1>;
570 #size-cells = <0>;
571 };
572
573 i2c2: i2c@5002800 {
574 compatible = "allwinner,sun50i-h6-i2c",
575 "allwinner,sun6i-a31-i2c";
576 reg = <0x05002800 0x400>;
577 interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>;
578 clocks = <&ccu CLK_BUS_I2C2>;
579 resets = <&ccu RST_BUS_I2C2>;
580 pinctrl-names = "default";
581 pinctrl-0 = <&i2c2_pins>;
582 status = "disabled";
583 #address-cells = <1>;
584 #size-cells = <0>;
585 };
586
587 spi0: spi@5010000 {
588 compatible = "allwinner,sun50i-h6-spi",
589 "allwinner,sun8i-h3-spi";
590 reg = <0x05010000 0x1000>;
591 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
592 clocks = <&ccu CLK_BUS_SPI0>, <&ccu CLK_SPI0>;
593 clock-names = "ahb", "mod";
594 dmas = <&dma 22>, <&dma 22>;
595 dma-names = "rx", "tx";
596 resets = <&ccu RST_BUS_SPI0>;
597 status = "disabled";
598 #address-cells = <1>;
599 #size-cells = <0>;
600 };
601
602 spi1: spi@5011000 {
603 compatible = "allwinner,sun50i-h6-spi",
604 "allwinner,sun8i-h3-spi";
605 reg = <0x05011000 0x1000>;
606 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
607 clocks = <&ccu CLK_BUS_SPI1>, <&ccu CLK_SPI1>;
608 clock-names = "ahb", "mod";
609 dmas = <&dma 23>, <&dma 23>;
610 dma-names = "rx", "tx";
611 resets = <&ccu RST_BUS_SPI1>;
612 status = "disabled";
613 #address-cells = <1>;
614 #size-cells = <0>;
615 };
616
a93a5504
JT		 617 emac: ethernet@5020000 {
618 compatible = "allwinner,sun50i-h6-emac",
619 "allwinner,sun50i-a64-emac";
620 syscon = <&syscon>;
621 reg = <0x05020000 0x10000>;
622 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
623 interrupt-names = "macirq";
624 resets = <&ccu RST_BUS_EMAC>;
625 reset-names = "stmmaceth";
626 clocks = <&ccu CLK_BUS_EMAC>;
627 clock-names = "stmmaceth";
628 status = "disabled";
629
630 mdio: mdio {
631 compatible = "snps,dwmac-mdio";
632 #address-cells = <1>;
633 #size-cells = <0>;
634 };
635 };
636
750cabc8
JS		 637 i2s1: i2s@5091000 {
638 #sound-dai-cells = <0>;
639 compatible = "allwinner,sun50i-h6-i2s";
640 reg = <0x05091000 0x1000>;
641 interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>;
642 clocks = <&ccu CLK_BUS_I2S1>, <&ccu CLK_I2S1>;
643 clock-names = "apb", "mod";
644 dmas = <&dma 4>, <&dma 4>;
645 resets = <&ccu RST_BUS_I2S1>;
646 dma-names = "rx", "tx";
647 status = "disabled";
648 };
649
650 spdif: spdif@5093000 {
651 #sound-dai-cells = <0>;
652 compatible = "allwinner,sun50i-h6-spdif";
653 reg = <0x05093000 0x400>;
654 interrupts = <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>;
655 clocks = <&ccu CLK_BUS_SPDIF>, <&ccu CLK_SPDIF>;
656 clock-names = "apb", "spdif";
657 resets = <&ccu RST_BUS_SPDIF>;
cee40d66
AP		 658 dmas = <&dma 2>, <&dma 2>;
659 dma-names = "rx", "tx";
750cabc8
JS		 660 status = "disabled";
661 };
662
a93a5504
JT		 663 usb2otg: usb@5100000 {
664 compatible = "allwinner,sun50i-h6-musb",
665 "allwinner,sun8i-a33-musb";
666 reg = <0x05100000 0x0400>;
667 clocks = <&ccu CLK_BUS_OTG>;
668 resets = <&ccu RST_BUS_OTG>;
669 interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
670 interrupt-names = "mc";
671 phys = <&usb2phy 0>;
672 phy-names = "usb";
673 extcon = <&usb2phy 0>;
674 status = "disabled";
675 };
676
677 usb2phy: phy@5100400 {
678 compatible = "allwinner,sun50i-h6-usb-phy";
679 reg = <0x05100400 0x24>,
680 <0x05101800 0x4>,
681 <0x05311800 0x4>;
682 reg-names = "phy_ctrl",
683 "pmu0",
684 "pmu3";
685 clocks = <&ccu CLK_USB_PHY0>,
686 <&ccu CLK_USB_PHY3>;
687 clock-names = "usb0_phy",
688 "usb3_phy";
689 resets = <&ccu RST_USB_PHY0>,
690 <&ccu RST_USB_PHY3>;
691 reset-names = "usb0_reset",
692 "usb3_reset";
693 status = "disabled";
694 #phy-cells = <1>;
695 };
696
697 ehci0: usb@5101000 {
698 compatible = "allwinner,sun50i-h6-ehci", "generic-ehci";
699 reg = <0x05101000 0x100>;
700 interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>;
701 clocks = <&ccu CLK_BUS_OHCI0>,
702 <&ccu CLK_BUS_EHCI0>,
703 <&ccu CLK_USB_OHCI0>;
704 resets = <&ccu RST_BUS_OHCI0>,
705 <&ccu RST_BUS_EHCI0>;
127e57c6
AP		 706 phys = <&usb2phy 0>;
707 phy-names = "usb";
a93a5504
JT		 708 status = "disabled";
709 };
710
711 ohci0: usb@5101400 {
712 compatible = "allwinner,sun50i-h6-ohci", "generic-ohci";
713 reg = <0x05101400 0x100>;
714 interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>;
715 clocks = <&ccu CLK_BUS_OHCI0>,
716 <&ccu CLK_USB_OHCI0>;
717 resets = <&ccu RST_BUS_OHCI0>;
127e57c6
AP		 718 phys = <&usb2phy 0>;
719 phy-names = "usb";
a93a5504
JT		 720 status = "disabled";
721 };
722
750cabc8
JS		 723 dwc3: usb@5200000 {
724 compatible = "snps,dwc3";
725 reg = <0x05200000 0x10000>;
726 interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>;
727 clocks = <&ccu CLK_BUS_XHCI>,
728 <&ccu CLK_BUS_XHCI>,
7f53f509 729 <&rtc CLK_OSC32K>;
750cabc8
JS		 730 clock-names = "ref", "bus_early", "suspend";
731 resets = <&ccu RST_BUS_XHCI>;
732 /*
733 * The datasheet of the chip doesn't declare the
734 * peripheral function, and there's no boards known
735 * to have a USB Type-B port routed to the port.
736 * In addition, no one has tested the peripheral
737 * function yet.
738 * So set the dr_mode to "host" in the DTSI file.
739 */
740 dr_mode = "host";
741 phys = <&usb3phy>;
742 phy-names = "usb3-phy";
743 status = "disabled";
744 };
745
746 usb3phy: phy@5210000 {
747 compatible = "allwinner,sun50i-h6-usb3-phy";
748 reg = <0x5210000 0x10000>;
749 clocks = <&ccu CLK_USB_PHY1>;
750 resets = <&ccu RST_USB_PHY1>;
751 #phy-cells = <0>;
752 status = "disabled";
753 };
754
a93a5504
JT		 755 ehci3: usb@5311000 {
756 compatible = "allwinner,sun50i-h6-ehci", "generic-ehci";
757 reg = <0x05311000 0x100>;
758 interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>;
759 clocks = <&ccu CLK_BUS_OHCI3>,
760 <&ccu CLK_BUS_EHCI3>,
761 <&ccu CLK_USB_OHCI3>;
762 resets = <&ccu RST_BUS_OHCI3>,
763 <&ccu RST_BUS_EHCI3>;
764 phys = <&usb2phy 3>;
750cabc8 765 phy-names = "usb";
a93a5504
JT		 766 status = "disabled";
767 };
768
769 ohci3: usb@5311400 {
770 compatible = "allwinner,sun50i-h6-ohci", "generic-ohci";
771 reg = <0x05311400 0x100>;
772 interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>;
773 clocks = <&ccu CLK_BUS_OHCI3>,
774 <&ccu CLK_USB_OHCI3>;
775 resets = <&ccu RST_BUS_OHCI3>;
776 phys = <&usb2phy 3>;
750cabc8 777 phy-names = "usb";
a93a5504
JT		 778 status = "disabled";
779 };
780
781 hdmi: hdmi@6000000 {
782 compatible = "allwinner,sun50i-h6-dw-hdmi";
783 reg = <0x06000000 0x10000>;
784 reg-io-width = <1>;
785 interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>;
786 clocks = <&ccu CLK_BUS_HDMI>, <&ccu CLK_HDMI_SLOW>,
787 <&ccu CLK_HDMI>, <&ccu CLK_HDMI_CEC>,
788 <&ccu CLK_HDCP>, <&ccu CLK_BUS_HDCP>;
789 clock-names = "iahb", "isfr", "tmds", "cec", "hdcp",
790 "hdcp-bus";
791 resets = <&ccu RST_BUS_HDMI_SUB>, <&ccu RST_BUS_HDCP>;
792 reset-names = "ctrl", "hdcp";
793 phys = <&hdmi_phy>;
750cabc8 794 phy-names = "phy";
a93a5504
JT		 795 pinctrl-names = "default";
796 pinctrl-0 = <&hdmi_pins>;
797 status = "disabled";
798
799 ports {
800 #address-cells = <1>;
801 #size-cells = <0>;
802
803 hdmi_in: port@0 {
804 reg = <0>;
805
806 hdmi_in_tcon_top: endpoint {
807 remote-endpoint = <&tcon_top_hdmi_out_hdmi>;
808 };
809 };
810
811 hdmi_out: port@1 {
812 reg = <1>;
813 };
814 };
815 };
816
817 hdmi_phy: hdmi-phy@6010000 {
818 compatible = "allwinner,sun50i-h6-hdmi-phy";
819 reg = <0x06010000 0x10000>;
820 clocks = <&ccu CLK_BUS_HDMI>, <&ccu CLK_HDMI_SLOW>;
821 clock-names = "bus", "mod";
822 resets = <&ccu RST_BUS_HDMI>;
823 reset-names = "phy";
824 #phy-cells = <0>;
825 };
826
827 tcon_top: tcon-top@6510000 {
828 compatible = "allwinner,sun50i-h6-tcon-top";
829 reg = <0x06510000 0x1000>;
830 clocks = <&ccu CLK_BUS_TCON_TOP>,
831 <&ccu CLK_TCON_TV0>;
832 clock-names = "bus",
833 "tcon-tv0";
834 clock-output-names = "tcon-top-tv0";
835 resets = <&ccu RST_BUS_TCON_TOP>;
a93a5504
JT		 836 #clock-cells = <1>;
837
838 ports {
839 #address-cells = <1>;
840 #size-cells = <0>;
841
842 tcon_top_mixer0_in: port@0 {
843 #address-cells = <1>;
844 #size-cells = <0>;
845 reg = <0>;
846
847 tcon_top_mixer0_in_mixer0: endpoint@0 {
848 reg = <0>;
849 remote-endpoint = <&mixer0_out_tcon_top_mixer0>;
850 };
851 };
852
853 tcon_top_mixer0_out: port@1 {
854 #address-cells = <1>;
855 #size-cells = <0>;
856 reg = <1>;
857
858 tcon_top_mixer0_out_tcon_tv: endpoint@2 {
859 reg = <2>;
860 remote-endpoint = <&tcon_tv_in_tcon_top_mixer0>;
861 };
862 };
863
864 tcon_top_hdmi_in: port@4 {
865 #address-cells = <1>;
866 #size-cells = <0>;
867 reg = <4>;
868
869 tcon_top_hdmi_in_tcon_tv: endpoint@0 {
870 reg = <0>;
871 remote-endpoint = <&tcon_tv_out_tcon_top>;
872 };
873 };
874
875 tcon_top_hdmi_out: port@5 {
876 reg = <5>;
877
878 tcon_top_hdmi_out_hdmi: endpoint {
879 remote-endpoint = <&hdmi_in_tcon_top>;
880 };
881 };
882 };
883 };
884
885 tcon_tv: lcd-controller@6515000 {
886 compatible = "allwinner,sun50i-h6-tcon-tv",
887 "allwinner,sun8i-r40-tcon-tv";
888 reg = <0x06515000 0x1000>;
889 interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>;
890 clocks = <&ccu CLK_BUS_TCON_TV0>,
891 <&tcon_top CLK_TCON_TOP_TV0>;
892 clock-names = "ahb",
893 "tcon-ch1";
894 resets = <&ccu RST_BUS_TCON_TV0>;
895 reset-names = "lcd";
896
897 ports {
898 #address-cells = <1>;
899 #size-cells = <0>;
900
901 tcon_tv_in: port@0 {
902 reg = <0>;
903
904 tcon_tv_in_tcon_top_mixer0: endpoint {
905 remote-endpoint = <&tcon_top_mixer0_out_tcon_tv>;
906 };
907 };
908
909 tcon_tv_out: port@1 {
910 #address-cells = <1>;
911 #size-cells = <0>;
912 reg = <1>;
913
914 tcon_tv_out_tcon_top: endpoint@1 {
915 reg = <1>;
916 remote-endpoint = <&tcon_top_hdmi_in_tcon_tv>;
917 };
918 };
919 };
920 };
921
750cabc8
JS		 922 rtc: rtc@7000000 {
923 compatible = "allwinner,sun50i-h6-rtc";
924 reg = <0x07000000 0x400>;
925 interrupts = <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>,
926 <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>;
927 clock-output-names = "osc32k", "osc32k-out", "iosc";
928 #clock-cells = <1>;
929 };
930
6f796a9b
IZ		 931 r_ccu: clock@7010000 {
932 compatible = "allwinner,sun50i-h6-r-ccu";
933 reg = <0x07010000 0x400>;
7f53f509 934 clocks = <&osc24M>, <&rtc CLK_OSC32K>, <&rtc CLK_IOSC>,
6f796a9b
IZ		 935 <&ccu CLK_PLL_PERIPH0>;
936 clock-names = "hosc", "losc", "iosc", "pll-periph";
937 #clock-cells = <1>;
938 #reset-cells = <1>;
939 };
940
cf05b4b8
CP		 941 r_watchdog: watchdog@7020400 {
942 compatible = "allwinner,sun50i-h6-wdt",
943 "allwinner,sun6i-a31-wdt";
944 reg = <0x07020400 0x20>;
945 interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>;
750cabc8 946 clocks = <&osc24M>;
cf05b4b8
CP		 947 };
948
6f796a9b
IZ		 949 r_intc: interrupt-controller@7021000 {
950 compatible = "allwinner,sun50i-h6-r-intc",
951 "allwinner,sun6i-a31-r-intc";
952 interrupt-controller;
953 #interrupt-cells = <2>;
954 reg = <0x07021000 0x400>;
955 interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;
956 };
957
958 r_pio: pinctrl@7022000 {
959 compatible = "allwinner,sun50i-h6-r-pinctrl";
960 reg = <0x07022000 0x400>;
961 interrupts = <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>,
962 <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>;
7f53f509
AP		 963 clocks = <&r_ccu CLK_R_APB1>, <&osc24M>,
964 <&rtc CLK_OSC32K>;
6f796a9b
IZ		 965 clock-names = "apb", "hosc", "losc";
966 gpio-controller;
967 #gpio-cells = <3>;
968 interrupt-controller;
969 #interrupt-cells = <3>;
970
a93a5504 971 r_i2c_pins: r-i2c-pins {
6f796a9b
IZ		 972 pins = "PL0", "PL1";
973 function = "s_i2c";
974 };
750cabc8
JS		 975
976 r_ir_rx_pin: r-ir-rx-pin {
977 pins = "PL9";
978 function = "s_cir_rx";
979 };
127e57c6
AP		 980
981 r_rsb_pins: r-rsb-pins {
982 pins = "PL0", "PL1";
983 function = "s_rsb";
984 };
750cabc8
JS		 985 };
986
987 r_ir: ir@7040000 {
988 compatible = "allwinner,sun50i-h6-ir",
989 "allwinner,sun6i-a31-ir";
990 reg = <0x07040000 0x400>;
991 interrupts = <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>;
992 clocks = <&r_ccu CLK_R_APB1_IR>,
993 <&r_ccu CLK_IR>;
994 clock-names = "apb", "ir";
995 resets = <&r_ccu RST_R_APB1_IR>;
996 pinctrl-names = "default";
997 pinctrl-0 = <&r_ir_rx_pin>;
998 status = "disabled";
6f796a9b
IZ		 999 };
1000
1001 r_i2c: i2c@7081400 {
750cabc8
JS		 1002 compatible = "allwinner,sun50i-h6-i2c",
1003 "allwinner,sun6i-a31-i2c";
6f796a9b
IZ		 1004 reg = <0x07081400 0x400>;
1005 interrupts = <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>;
1006 clocks = <&r_ccu CLK_R_APB2_I2C>;
1007 resets = <&r_ccu RST_R_APB2_I2C>;
1008 pinctrl-names = "default";
1009 pinctrl-0 = <&r_i2c_pins>;
1010 status = "disabled";
1011 #address-cells = <1>;
1012 #size-cells = <0>;
1013 };
750cabc8 1014
127e57c6
AP		 1015 r_rsb: rsb@7083000 {
1016 compatible = "allwinner,sun8i-a23-rsb";
1017 reg = <0x07083000 0x400>;
1018 interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>;
1019 clocks = <&r_ccu CLK_R_APB2_RSB>;
1020 clock-frequency = <3000000>;
1021 resets = <&r_ccu RST_R_APB2_RSB>;
1022 pinctrl-names = "default";
1023 pinctrl-0 = <&r_rsb_pins>;
1024 status = "disabled";
1025 #address-cells = <1>;
1026 #size-cells = <0>;
1027 };
1028
750cabc8
JS		 1029 ths: thermal-sensor@5070400 {
1030 compatible = "allwinner,sun50i-h6-ths";
1031 reg = <0x05070400 0x100>;
1032 interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
1033 clocks = <&ccu CLK_BUS_THS>;
1034 clock-names = "bus";
1035 resets = <&ccu RST_BUS_THS>;
1036 nvmem-cells = <&ths_calibration>;
1037 nvmem-cell-names = "calibration";
1038 #thermal-sensor-cells = <1>;
1039 };
1040 };
1041
1042 thermal-zones {
1043 cpu-thermal {
1044 polling-delay-passive = <0>;
1045 polling-delay = <0>;
1046 thermal-sensors = <&ths 0>;
1047
1048 trips {
1049 cpu_alert: cpu-alert {
1050 temperature = <85000>;
1051 hysteresis = <2000>;
1052 type = "passive";
1053 };
1054
1055 cpu-crit {
1056 temperature = <100000>;
1057 hysteresis = <0>;
1058 type = "critical";
1059 };
1060 };
1061
1062 cooling-maps {
1063 map0 {
1064 trip = <&cpu_alert>;
1065 cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
1066 <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
1067 <&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
1068 <&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
1069 };
1070 };
1071 };
1072
1073 gpu-thermal {
8e2c0ee3
AP		 1074 polling-delay-passive = <1000>;
1075 polling-delay = <2000>;
750cabc8 1076 thermal-sensors = <&ths 1>;
8e2c0ee3
AP		 1077
1078 trips {
1079 gpu_alert0: gpu-alert-0 {
1080 temperature = <95000>;
1081 hysteresis = <2000>;
1082 type = "passive";
1083 };
1084
1085 gpu_alert1: gpu-alert-1 {
1086 temperature = <100000>;
1087 hysteresis = <2000>;
1088 type = "passive";
1089 };
1090
1091 gpu_alert2: gpu-alert-2 {
1092 temperature = <105000>;
1093 hysteresis = <2000>;
1094 type = "passive";
1095 };
1096
1097 gpu-crit {
1098 temperature = <115000>;
1099 hysteresis = <0>;
1100 type = "critical";
1101 };
1102 };
1103
1104 cooling-maps {
1105 // Forbid the GPU to go over 756MHz
1106 map0 {
1107 trip = <&gpu_alert0>;
1108 cooling-device = <&gpu 1 THERMAL_NO_LIMIT>;
1109 };
1110
1111 // Forbid the GPU to go over 624MHz
1112 map1 {
1113 trip = <&gpu_alert1>;
1114 cooling-device = <&gpu 2 THERMAL_NO_LIMIT>;
1115 };
1116
1117 // Forbid the GPU to go over 576MHz
1118 map2 {
1119 trip = <&gpu_alert2>;
1120 cooling-device = <&gpu 3 THERMAL_NO_LIMIT>;
1121 };
1122 };
750cabc8 1123 };
6f796a9b
IZ		 1124 };
1125};
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