projects / J-u-boot.git / blame
| Commit | Line | Data |
|---|---|---|
| a674313c PD |
1 | // SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause) |
| 2 | /* | |
| 3 | * Copyright (C) STMicroelectronics 2017 - All Rights Reserved | |
| 4 | * Author: Ludovic Barre <[email protected]> for STMicroelectronics. | |
| 5 | */ | |
| 6 | #include <dt-bindings/interrupt-controller/arm-gic.h> | |
| 7 | #include <dt-bindings/clock/stm32mp1-clks.h> | |
| 8 | #include <dt-bindings/reset/stm32mp1-resets.h> | |
| 9 | ||
| 10 | / { | |
| 11 | #address-cells = <1>; | |
| 12 | #size-cells = <1>; | |
| 13 | ||
| 14 | cpus { | |
| 15 | #address-cells = <1>; | |
| 16 | #size-cells = <0>; | |
| 17 | ||
| 18 | cpu0: cpu@0 { | |
| 19 | compatible = "arm,cortex-a7"; | |
| 1b28a5e2 | 20 | clock-frequency = <650000000>; |
| a674313c PD |
21 | device_type = "cpu"; |
| 22 | reg = <0>; | |
| 6f2e0ad1 PD |
23 | operating-points-v2 = <&cpu0_opp_table>; |
| 24 | nvmem-cells = <&part_number_otp>; | |
| 25 | nvmem-cell-names = "part_number"; | |
| 26 | }; | |
| 27 | }; | |
| 28 | ||
| 29 | cpu0_opp_table: cpu0-opp-table { | |
| 30 | compatible = "operating-points-v2"; | |
| 31 | opp-shared; | |
| 32 | opp-650000000 { | |
| 33 | opp-hz = /bits/ 64 <650000000>; | |
| 34 | opp-microvolt = <1200000>; | |
| 35 | opp-supported-hw = <0x1>; | |
| 36 | }; | |
| 37 | opp-800000000 { | |
| 38 | opp-hz = /bits/ 64 <800000000>; | |
| 39 | opp-microvolt = <1350000>; | |
| 40 | opp-supported-hw = <0x2>; | |
| a674313c | 41 | }; |
| a674313c PD |
42 | }; |
| 43 | ||
| f050e3fe PD |
44 | arm-pmu { |
| 45 | compatible = "arm,cortex-a7-pmu"; | |
| 46 | interrupts = <GIC_SPI 200 IRQ_TYPE_LEVEL_HIGH>; | |
| 47 | interrupt-affinity = <&cpu0>; | |
| 48 | interrupt-parent = <&intc>; | |
| 49 | }; | |
| 50 | ||
| a674313c | 51 | psci { |
| c8a6668c | 52 | compatible = "arm,psci-1.0"; |
| a674313c | 53 | method = "smc"; |
| a674313c PD |
54 | }; |
| 55 | ||
| a674313c PD |
56 | intc: interrupt-controller@a0021000 { |
| 57 | compatible = "arm,cortex-a7-gic"; | |
| 58 | #interrupt-cells = <3>; | |
| 59 | interrupt-controller; | |
| 60 | reg = <0xa0021000 0x1000>, | |
| 61 | <0xa0022000 0x2000>; | |
| 62 | }; | |
| 63 | ||
| 64 | timer { | |
| 65 | compatible = "arm,armv7-timer"; | |
| 189ec2fe PD |
66 | interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>, |
| 67 | <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>, | |
| 68 | <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>, | |
| 69 | <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>; | |
| a674313c PD |
70 | interrupt-parent = <&intc>; |
| 71 | }; | |
| 72 | ||
| 73 | clocks { | |
| 74 | clk_hse: clk-hse { | |
| 75 | #clock-cells = <0>; | |
| 76 | compatible = "fixed-clock"; | |
| 77 | clock-frequency = <24000000>; | |
| 78 | }; | |
| 79 | ||
| 80 | clk_hsi: clk-hsi { | |
| 81 | #clock-cells = <0>; | |
| 82 | compatible = "fixed-clock"; | |
| 83 | clock-frequency = <64000000>; | |
| 84 | }; | |
| 85 | ||
| 86 | clk_lse: clk-lse { | |
| 87 | #clock-cells = <0>; | |
| 88 | compatible = "fixed-clock"; | |
| 89 | clock-frequency = <32768>; | |
| 90 | }; | |
| 91 | ||
| 92 | clk_lsi: clk-lsi { | |
| 93 | #clock-cells = <0>; | |
| 94 | compatible = "fixed-clock"; | |
| 95 | clock-frequency = <32000>; | |
| 96 | }; | |
| 97 | ||
| 98 | clk_csi: clk-csi { | |
| 99 | #clock-cells = <0>; | |
| 100 | compatible = "fixed-clock"; | |
| 101 | clock-frequency = <4000000>; | |
| 102 | }; | |
| 103 | }; | |
| 104 | ||
| 35a54d41 PD |
105 | thermal-zones { |
| 106 | cpu_thermal: cpu-thermal { | |
| 107 | polling-delay-passive = <0>; | |
| 108 | polling-delay = <0>; | |
| 109 | thermal-sensors = <&dts>; | |
| 110 | ||
| 111 | trips { | |
| 112 | cpu_alert1: cpu-alert1 { | |
| 113 | temperature = <85000>; | |
| 114 | hysteresis = <0>; | |
| 115 | type = "passive"; | |
| 116 | }; | |
| 117 | ||
| 118 | cpu-crit { | |
| 119 | temperature = <120000>; | |
| 120 | hysteresis = <0>; | |
| 121 | type = "critical"; | |
| 122 | }; | |
| 123 | }; | |
| 124 | ||
| 125 | cooling-maps { | |
| 126 | }; | |
| 127 | }; | |
| 128 | }; | |
| 129 | ||
| 62d620c2 PD |
130 | booster: regulator-booster { |
| 131 | compatible = "st,stm32mp1-booster"; | |
| 132 | st,syscfg = <&syscfg>; | |
| 133 | status = "disabled"; | |
| 134 | }; | |
| 135 | ||
| a674313c PD |
136 | soc { |
| 137 | compatible = "simple-bus"; | |
| 138 | #address-cells = <1>; | |
| 139 | #size-cells = <1>; | |
| 140 | interrupt-parent = <&intc>; | |
| 141 | ranges; | |
| 142 | ||
| 143 | timers2: timer@40000000 { | |
| 144 | #address-cells = <1>; | |
| 145 | #size-cells = <0>; | |
| 146 | compatible = "st,stm32-timers"; | |
| 147 | reg = <0x40000000 0x400>; | |
| 6e391c7d PD |
148 | interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>; |
| 149 | interrupt-names = "global"; | |
| a674313c PD |
150 | clocks = <&rcc TIM2_K>; |
| 151 | clock-names = "int"; | |
| 35a54d41 PD |
152 | dmas = <&dmamux1 18 0x400 0x1>, |
| 153 | <&dmamux1 19 0x400 0x1>, | |
| 154 | <&dmamux1 20 0x400 0x1>, | |
| 155 | <&dmamux1 21 0x400 0x1>, | |
| 156 | <&dmamux1 22 0x400 0x1>; | |
| 157 | dma-names = "ch1", "ch2", "ch3", "ch4", "up"; | |
| a674313c PD |
158 | status = "disabled"; |
| 159 | ||
| 160 | pwm { | |
| 161 | compatible = "st,stm32-pwm"; | |
| 62d620c2 | 162 | #pwm-cells = <3>; |
| a674313c PD |
163 | status = "disabled"; |
| 164 | }; | |
| 165 | ||
| 166 | timer@1 { | |
| 167 | compatible = "st,stm32h7-timer-trigger"; | |
| 168 | reg = <1>; | |
| 169 | status = "disabled"; | |
| 170 | }; | |
| 1a4f57c8 PD |
171 | |
| 172 | counter { | |
| 173 | compatible = "st,stm32-timer-counter"; | |
| 174 | status = "disabled"; | |
| 175 | }; | |
| a674313c PD |
176 | }; |
| 177 | ||
| 178 | timers3: timer@40001000 { | |
| 179 | #address-cells = <1>; | |
| 180 | #size-cells = <0>; | |
| 181 | compatible = "st,stm32-timers"; | |
| 182 | reg = <0x40001000 0x400>; | |
| 6e391c7d PD |
183 | interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>; |
| 184 | interrupt-names = "global"; | |
| a674313c PD |
185 | clocks = <&rcc TIM3_K>; |
| 186 | clock-names = "int"; | |
| 35a54d41 PD |
187 | dmas = <&dmamux1 23 0x400 0x1>, |
| 188 | <&dmamux1 24 0x400 0x1>, | |
| 189 | <&dmamux1 25 0x400 0x1>, | |
| 190 | <&dmamux1 26 0x400 0x1>, | |
| 191 | <&dmamux1 27 0x400 0x1>, | |
| 192 | <&dmamux1 28 0x400 0x1>; | |
| 193 | dma-names = "ch1", "ch2", "ch3", "ch4", "up", "trig"; | |
| a674313c PD |
194 | status = "disabled"; |
| 195 | ||
| 196 | pwm { | |
| 197 | compatible = "st,stm32-pwm"; | |
| 62d620c2 | 198 | #pwm-cells = <3>; |
| a674313c PD |
199 | status = "disabled"; |
| 200 | }; | |
| 201 | ||
| 202 | timer@2 { | |
| 203 | compatible = "st,stm32h7-timer-trigger"; | |
| 204 | reg = <2>; | |
| 205 | status = "disabled"; | |
| 206 | }; | |
| 1a4f57c8 PD |
207 | |
| 208 | counter { | |
| 209 | compatible = "st,stm32-timer-counter"; | |
| 210 | status = "disabled"; | |
| 211 | }; | |
| a674313c PD |
212 | }; |
| 213 | ||
| 214 | timers4: timer@40002000 { | |
| 215 | #address-cells = <1>; | |
| 216 | #size-cells = <0>; | |
| 217 | compatible = "st,stm32-timers"; | |
| 218 | reg = <0x40002000 0x400>; | |
| 6e391c7d PD |
219 | interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>; |
| 220 | interrupt-names = "global"; | |
| a674313c PD |
221 | clocks = <&rcc TIM4_K>; |
| 222 | clock-names = "int"; | |
| 35a54d41 PD |
223 | dmas = <&dmamux1 29 0x400 0x1>, |
| 224 | <&dmamux1 30 0x400 0x1>, | |
| 225 | <&dmamux1 31 0x400 0x1>, | |
| 226 | <&dmamux1 32 0x400 0x1>; | |
| 227 | dma-names = "ch1", "ch2", "ch3", "ch4"; | |
| a674313c PD |
228 | status = "disabled"; |
| 229 | ||
| 230 | pwm { | |
| 231 | compatible = "st,stm32-pwm"; | |
| 62d620c2 | 232 | #pwm-cells = <3>; |
| a674313c PD |
233 | status = "disabled"; |
| 234 | }; | |
| 235 | ||
| 236 | timer@3 { | |
| 237 | compatible = "st,stm32h7-timer-trigger"; | |
| 238 | reg = <3>; | |
| 239 | status = "disabled"; | |
| 240 | }; | |
| 1a4f57c8 PD |
241 | |
| 242 | counter { | |
| 243 | compatible = "st,stm32-timer-counter"; | |
| 244 | status = "disabled"; | |
| 245 | }; | |
| a674313c PD |
246 | }; |
| 247 | ||
| 248 | timers5: timer@40003000 { | |
| 249 | #address-cells = <1>; | |
| 250 | #size-cells = <0>; | |
| 251 | compatible = "st,stm32-timers"; | |
| 252 | reg = <0x40003000 0x400>; | |
| 6e391c7d PD |
253 | interrupts = <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>; |
| 254 | interrupt-names = "global"; | |
| a674313c PD |
255 | clocks = <&rcc TIM5_K>; |
| 256 | clock-names = "int"; | |
| 35a54d41 PD |
257 | dmas = <&dmamux1 55 0x400 0x1>, |
| 258 | <&dmamux1 56 0x400 0x1>, | |
| 259 | <&dmamux1 57 0x400 0x1>, | |
| 260 | <&dmamux1 58 0x400 0x1>, | |
| 261 | <&dmamux1 59 0x400 0x1>, | |
| 262 | <&dmamux1 60 0x400 0x1>; | |
| 263 | dma-names = "ch1", "ch2", "ch3", "ch4", "up", "trig"; | |
| a674313c PD |
264 | status = "disabled"; |
| 265 | ||
| 266 | pwm { | |
| 267 | compatible = "st,stm32-pwm"; | |
| 62d620c2 | 268 | #pwm-cells = <3>; |
| a674313c PD |
269 | status = "disabled"; |
| 270 | }; | |
| 271 | ||
| 272 | timer@4 { | |
| 273 | compatible = "st,stm32h7-timer-trigger"; | |
| 274 | reg = <4>; | |
| 275 | status = "disabled"; | |
| 276 | }; | |
| 1a4f57c8 PD |
277 | |
| 278 | counter { | |
| 279 | compatible = "st,stm32-timer-counter"; | |
| 280 | status = "disabled"; | |
| 281 | }; | |
| a674313c PD |
282 | }; |
| 283 | ||
| 284 | timers6: timer@40004000 { | |
| 285 | #address-cells = <1>; | |
| 286 | #size-cells = <0>; | |
| 287 | compatible = "st,stm32-timers"; | |
| 288 | reg = <0x40004000 0x400>; | |
| 6e391c7d PD |
289 | interrupts = <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>; |
| 290 | interrupt-names = "global"; | |
| a674313c PD |
291 | clocks = <&rcc TIM6_K>; |
| 292 | clock-names = "int"; | |
| 35a54d41 PD |
293 | dmas = <&dmamux1 69 0x400 0x1>; |
| 294 | dma-names = "up"; | |
| a674313c PD |
295 | status = "disabled"; |
| 296 | ||
| 297 | timer@5 { | |
| 298 | compatible = "st,stm32h7-timer-trigger"; | |
| 299 | reg = <5>; | |
| 300 | status = "disabled"; | |
| 301 | }; | |
| 302 | }; | |
| 303 | ||
| 304 | timers7: timer@40005000 { | |
| 305 | #address-cells = <1>; | |
| 306 | #size-cells = <0>; | |
| 307 | compatible = "st,stm32-timers"; | |
| 308 | reg = <0x40005000 0x400>; | |
| 6e391c7d PD |
309 | interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>; |
| 310 | interrupt-names = "global"; | |
| a674313c PD |
311 | clocks = <&rcc TIM7_K>; |
| 312 | clock-names = "int"; | |
| 35a54d41 PD |
313 | dmas = <&dmamux1 70 0x400 0x1>; |
| 314 | dma-names = "up"; | |
| a674313c PD |
315 | status = "disabled"; |
| 316 | ||
| 317 | timer@6 { | |
| 318 | compatible = "st,stm32h7-timer-trigger"; | |
| 319 | reg = <6>; | |
| 320 | status = "disabled"; | |
| 321 | }; | |
| 322 | }; | |
| 323 | ||
| 324 | timers12: timer@40006000 { | |
| 325 | #address-cells = <1>; | |
| 326 | #size-cells = <0>; | |
| 327 | compatible = "st,stm32-timers"; | |
| 328 | reg = <0x40006000 0x400>; | |
| 6e391c7d PD |
329 | interrupts = <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>; |
| 330 | interrupt-names = "global"; | |
| a674313c PD |
331 | clocks = <&rcc TIM12_K>; |
| 332 | clock-names = "int"; | |
| 333 | status = "disabled"; | |
| 334 | ||
| 335 | pwm { | |
| 336 | compatible = "st,stm32-pwm"; | |
| 62d620c2 | 337 | #pwm-cells = <3>; |
| a674313c PD |
338 | status = "disabled"; |
| 339 | }; | |
| 340 | ||
| 341 | timer@11 { | |
| 342 | compatible = "st,stm32h7-timer-trigger"; | |
| 343 | reg = <11>; | |
| 344 | status = "disabled"; | |
| 345 | }; | |
| 346 | }; | |
| 347 | ||
| 348 | timers13: timer@40007000 { | |
| 349 | #address-cells = <1>; | |
| 350 | #size-cells = <0>; | |
| 351 | compatible = "st,stm32-timers"; | |
| 352 | reg = <0x40007000 0x400>; | |
| 6e391c7d PD |
353 | interrupts = <GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>; |
| 354 | interrupt-names = "global"; | |
| a674313c PD |
355 | clocks = <&rcc TIM13_K>; |
| 356 | clock-names = "int"; | |
| 357 | status = "disabled"; | |
| 358 | ||
| 359 | pwm { | |
| 360 | compatible = "st,stm32-pwm"; | |
| 62d620c2 | 361 | #pwm-cells = <3>; |
| a674313c PD |
362 | status = "disabled"; |
| 363 | }; | |
| 364 | ||
| 365 | timer@12 { | |
| 366 | compatible = "st,stm32h7-timer-trigger"; | |
| 367 | reg = <12>; | |
| 368 | status = "disabled"; | |
| 369 | }; | |
| 370 | }; | |
| 371 | ||
| 372 | timers14: timer@40008000 { | |
| 373 | #address-cells = <1>; | |
| 374 | #size-cells = <0>; | |
| 375 | compatible = "st,stm32-timers"; | |
| 376 | reg = <0x40008000 0x400>; | |
| 6e391c7d PD |
377 | interrupts = <GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>; |
| 378 | interrupt-names = "global"; | |
| a674313c PD |
379 | clocks = <&rcc TIM14_K>; |
| 380 | clock-names = "int"; | |
| 381 | status = "disabled"; | |
| 382 | ||
| 383 | pwm { | |
| 384 | compatible = "st,stm32-pwm"; | |
| 62d620c2 | 385 | #pwm-cells = <3>; |
| a674313c PD |
386 | status = "disabled"; |
| 387 | }; | |
| 388 | ||
| 389 | timer@13 { | |
| 390 | compatible = "st,stm32h7-timer-trigger"; | |
| 391 | reg = <13>; | |
| 392 | status = "disabled"; | |
| 393 | }; | |
| 394 | }; | |
| 395 | ||
| 396 | lptimer1: timer@40009000 { | |
| 397 | #address-cells = <1>; | |
| 398 | #size-cells = <0>; | |
| 399 | compatible = "st,stm32-lptimer"; | |
| 400 | reg = <0x40009000 0x400>; | |
| f050e3fe | 401 | interrupts-extended = <&exti 47 IRQ_TYPE_LEVEL_HIGH>; |
| a674313c PD |
402 | clocks = <&rcc LPTIM1_K>; |
| 403 | clock-names = "mux"; | |
| f050e3fe | 404 | wakeup-source; |
| a674313c PD |
405 | status = "disabled"; |
| 406 | ||
| 407 | pwm { | |
| 408 | compatible = "st,stm32-pwm-lp"; | |
| 409 | #pwm-cells = <3>; | |
| 410 | status = "disabled"; | |
| 411 | }; | |
| 412 | ||
| 413 | trigger@0 { | |
| 414 | compatible = "st,stm32-lptimer-trigger"; | |
| 415 | reg = <0>; | |
| 416 | status = "disabled"; | |
| 417 | }; | |
| 418 | ||
| 419 | counter { | |
| 420 | compatible = "st,stm32-lptimer-counter"; | |
| 421 | status = "disabled"; | |
| 422 | }; | |
| 423 | }; | |
| 424 | ||
| 2366160e PC |
425 | spi2: spi@4000b000 { |
| 426 | #address-cells = <1>; | |
| 427 | #size-cells = <0>; | |
| 428 | compatible = "st,stm32h7-spi"; | |
| 429 | reg = <0x4000b000 0x400>; | |
| 430 | interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>; | |
| 431 | clocks = <&rcc SPI2_K>; | |
| 432 | resets = <&rcc SPI2_R>; | |
| 433 | dmas = <&dmamux1 39 0x400 0x05>, | |
| 434 | <&dmamux1 40 0x400 0x05>; | |
| 435 | dma-names = "rx", "tx"; | |
| 436 | status = "disabled"; | |
| 437 | }; | |
| 438 | ||
| fe915336 PD |
439 | i2s2: audio-controller@4000b000 { |
| 440 | compatible = "st,stm32h7-i2s"; | |
| 441 | #sound-dai-cells = <0>; | |
| 442 | reg = <0x4000b000 0x400>; | |
| 443 | interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>; | |
| 444 | dmas = <&dmamux1 39 0x400 0x01>, | |
| 445 | <&dmamux1 40 0x400 0x01>; | |
| 446 | dma-names = "rx", "tx"; | |
| 447 | status = "disabled"; | |
| 448 | }; | |
| 449 | ||
| 2366160e PC |
450 | spi3: spi@4000c000 { |
| 451 | #address-cells = <1>; | |
| 452 | #size-cells = <0>; | |
| 453 | compatible = "st,stm32h7-spi"; | |
| 454 | reg = <0x4000c000 0x400>; | |
| 455 | interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>; | |
| 456 | clocks = <&rcc SPI3_K>; | |
| 457 | resets = <&rcc SPI3_R>; | |
| 458 | dmas = <&dmamux1 61 0x400 0x05>, | |
| 459 | <&dmamux1 62 0x400 0x05>; | |
| 460 | dma-names = "rx", "tx"; | |
| 461 | status = "disabled"; | |
| 462 | }; | |
| 463 | ||
| fe915336 PD |
464 | i2s3: audio-controller@4000c000 { |
| 465 | compatible = "st,stm32h7-i2s"; | |
| 466 | #sound-dai-cells = <0>; | |
| 467 | reg = <0x4000c000 0x400>; | |
| 468 | interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>; | |
| 469 | dmas = <&dmamux1 61 0x400 0x01>, | |
| 470 | <&dmamux1 62 0x400 0x01>; | |
| 471 | dma-names = "rx", "tx"; | |
| 472 | status = "disabled"; | |
| 473 | }; | |
| 474 | ||
| 35a54d41 PD |
475 | spdifrx: audio-controller@4000d000 { |
| 476 | compatible = "st,stm32h7-spdifrx"; | |
| 477 | #sound-dai-cells = <0>; | |
| 478 | reg = <0x4000d000 0x400>; | |
| 479 | clocks = <&rcc SPDIF_K>; | |
| 480 | clock-names = "kclk"; | |
| 481 | interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>; | |
| 482 | dmas = <&dmamux1 93 0x400 0x01>, | |
| 483 | <&dmamux1 94 0x400 0x01>; | |
| 484 | dma-names = "rx", "rx-ctrl"; | |
| 485 | status = "disabled"; | |
| 486 | }; | |
| 487 | ||
| a674313c PD |
488 | usart2: serial@4000e000 { |
| 489 | compatible = "st,stm32h7-uart"; | |
| 490 | reg = <0x4000e000 0x400>; | |
| 7e549345 | 491 | interrupts-extended = <&exti 27 IRQ_TYPE_LEVEL_HIGH>; |
| a674313c | 492 | clocks = <&rcc USART2_K>; |
| 7e549345 | 493 | wakeup-source; |
| 189ec2fe PD |
494 | dmas = <&dmamux1 43 0x400 0x15>, |
| 495 | <&dmamux1 44 0x400 0x11>; | |
| 496 | dma-names = "rx", "tx"; | |
| a674313c PD |
497 | status = "disabled"; |
| 498 | }; | |
| 499 | ||
| 500 | usart3: serial@4000f000 { | |
| 501 | compatible = "st,stm32h7-uart"; | |
| 502 | reg = <0x4000f000 0x400>; | |
| 7e549345 | 503 | interrupts-extended = <&exti 28 IRQ_TYPE_LEVEL_HIGH>; |
| a674313c | 504 | clocks = <&rcc USART3_K>; |
| 7e549345 | 505 | wakeup-source; |
| 189ec2fe PD |
506 | dmas = <&dmamux1 45 0x400 0x15>, |
| 507 | <&dmamux1 46 0x400 0x11>; | |
| 508 | dma-names = "rx", "tx"; | |
| a674313c PD |
509 | status = "disabled"; |
| 510 | }; | |
| 511 | ||
| 512 | uart4: serial@40010000 { | |
| 513 | compatible = "st,stm32h7-uart"; | |
| 514 | reg = <0x40010000 0x400>; | |
| 7e549345 | 515 | interrupts-extended = <&exti 30 IRQ_TYPE_LEVEL_HIGH>; |
| a674313c | 516 | clocks = <&rcc UART4_K>; |
| 7e549345 | 517 | wakeup-source; |
| 189ec2fe PD |
518 | dmas = <&dmamux1 63 0x400 0x15>, |
| 519 | <&dmamux1 64 0x400 0x11>; | |
| 520 | dma-names = "rx", "tx"; | |
| a674313c PD |
521 | status = "disabled"; |
| 522 | }; | |
| 523 | ||
| 524 | uart5: serial@40011000 { | |
| 525 | compatible = "st,stm32h7-uart"; | |
| 526 | reg = <0x40011000 0x400>; | |
| 7e549345 | 527 | interrupts-extended = <&exti 31 IRQ_TYPE_LEVEL_HIGH>; |
| a674313c | 528 | clocks = <&rcc UART5_K>; |
| 7e549345 | 529 | wakeup-source; |
| 189ec2fe PD |
530 | dmas = <&dmamux1 65 0x400 0x15>, |
| 531 | <&dmamux1 66 0x400 0x11>; | |
| 532 | dma-names = "rx", "tx"; | |
| a674313c PD |
533 | status = "disabled"; |
| 534 | }; | |
| 535 | ||
| 536 | i2c1: i2c@40012000 { | |
| 500327e2 | 537 | compatible = "st,stm32mp15-i2c"; |
| a674313c PD |
538 | reg = <0x40012000 0x400>; |
| 539 | interrupt-names = "event", "error"; | |
| 540 | interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>, | |
| 541 | <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>; | |
| 542 | clocks = <&rcc I2C1_K>; | |
| 543 | resets = <&rcc I2C1_R>; | |
| 544 | #address-cells = <1>; | |
| 545 | #size-cells = <0>; | |
| 500327e2 | 546 | st,syscfg-fmp = <&syscfg 0x4 0x1>; |
| 1b28a5e2 | 547 | wakeup-source; |
| 7e549345 | 548 | i2c-analog-filter; |
| a674313c PD |
549 | status = "disabled"; |
| 550 | }; | |
| 551 | ||
| 552 | i2c2: i2c@40013000 { | |
| 500327e2 | 553 | compatible = "st,stm32mp15-i2c"; |
| a674313c PD |
554 | reg = <0x40013000 0x400>; |
| 555 | interrupt-names = "event", "error"; | |
| 556 | interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>, | |
| 557 | <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>; | |
| 558 | clocks = <&rcc I2C2_K>; | |
| 559 | resets = <&rcc I2C2_R>; | |
| 560 | #address-cells = <1>; | |
| 561 | #size-cells = <0>; | |
| 500327e2 | 562 | st,syscfg-fmp = <&syscfg 0x4 0x2>; |
| 1b28a5e2 | 563 | wakeup-source; |
| 7e549345 | 564 | i2c-analog-filter; |
| a674313c PD |
565 | status = "disabled"; |
| 566 | }; | |
| 567 | ||
| 568 | i2c3: i2c@40014000 { | |
| 500327e2 | 569 | compatible = "st,stm32mp15-i2c"; |
| a674313c PD |
570 | reg = <0x40014000 0x400>; |
| 571 | interrupt-names = "event", "error"; | |
| 572 | interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>, | |
| 573 | <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>; | |
| 574 | clocks = <&rcc I2C3_K>; | |
| 575 | resets = <&rcc I2C3_R>; | |
| 576 | #address-cells = <1>; | |
| 577 | #size-cells = <0>; | |
| 500327e2 | 578 | st,syscfg-fmp = <&syscfg 0x4 0x4>; |
| 1b28a5e2 | 579 | wakeup-source; |
| 7e549345 | 580 | i2c-analog-filter; |
| a674313c PD |
581 | status = "disabled"; |
| 582 | }; | |
| 583 | ||
| 584 | i2c5: i2c@40015000 { | |
| 500327e2 | 585 | compatible = "st,stm32mp15-i2c"; |
| a674313c PD |
586 | reg = <0x40015000 0x400>; |
| 587 | interrupt-names = "event", "error"; | |
| 588 | interrupts = <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>, | |
| 589 | <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>; | |
| 590 | clocks = <&rcc I2C5_K>; | |
| 591 | resets = <&rcc I2C5_R>; | |
| 592 | #address-cells = <1>; | |
| 593 | #size-cells = <0>; | |
| 500327e2 | 594 | st,syscfg-fmp = <&syscfg 0x4 0x10>; |
| 1b28a5e2 | 595 | wakeup-source; |
| 7e549345 | 596 | i2c-analog-filter; |
| a674313c PD |
597 | status = "disabled"; |
| 598 | }; | |
| 599 | ||
| 600 | cec: cec@40016000 { | |
| 601 | compatible = "st,stm32-cec"; | |
| 602 | reg = <0x40016000 0x400>; | |
| 603 | interrupts = <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>; | |
| 69ef98b2 | 604 | clocks = <&rcc CEC_K>, <&rcc CEC>; |
| a674313c PD |
605 | clock-names = "cec", "hdmi-cec"; |
| 606 | status = "disabled"; | |
| 607 | }; | |
| 608 | ||
| 609 | dac: dac@40017000 { | |
| 610 | compatible = "st,stm32h7-dac-core"; | |
| 611 | reg = <0x40017000 0x400>; | |
| 612 | clocks = <&rcc DAC12>; | |
| 613 | clock-names = "pclk"; | |
| 614 | #address-cells = <1>; | |
| 615 | #size-cells = <0>; | |
| 616 | status = "disabled"; | |
| 617 | ||
| 618 | dac1: dac@1 { | |
| 619 | compatible = "st,stm32-dac"; | |
| 500327e2 | 620 | #io-channel-cells = <1>; |
| a674313c PD |
621 | reg = <1>; |
| 622 | status = "disabled"; | |
| 623 | }; | |
| 624 | ||
| 625 | dac2: dac@2 { | |
| 626 | compatible = "st,stm32-dac"; | |
| 500327e2 | 627 | #io-channel-cells = <1>; |
| a674313c PD |
628 | reg = <2>; |
| 629 | status = "disabled"; | |
| 630 | }; | |
| 631 | }; | |
| 632 | ||
| 633 | uart7: serial@40018000 { | |
| 634 | compatible = "st,stm32h7-uart"; | |
| 635 | reg = <0x40018000 0x400>; | |
| 7e549345 | 636 | interrupts-extended = <&exti 32 IRQ_TYPE_LEVEL_HIGH>; |
| a674313c | 637 | clocks = <&rcc UART7_K>; |
| 7e549345 | 638 | wakeup-source; |
| 189ec2fe PD |
639 | dmas = <&dmamux1 79 0x400 0x15>, |
| 640 | <&dmamux1 80 0x400 0x11>; | |
| 641 | dma-names = "rx", "tx"; | |
| a674313c PD |
642 | status = "disabled"; |
| 643 | }; | |
| 644 | ||
| 645 | uart8: serial@40019000 { | |
| 646 | compatible = "st,stm32h7-uart"; | |
| 647 | reg = <0x40019000 0x400>; | |
| 7e549345 | 648 | interrupts-extended = <&exti 33 IRQ_TYPE_LEVEL_HIGH>; |
| a674313c | 649 | clocks = <&rcc UART8_K>; |
| 7e549345 | 650 | wakeup-source; |
| 189ec2fe PD |
651 | dmas = <&dmamux1 81 0x400 0x15>, |
| 652 | <&dmamux1 82 0x400 0x11>; | |
| 653 | dma-names = "rx", "tx"; | |
| a674313c PD |
654 | status = "disabled"; |
| 655 | }; | |
| 656 | ||
| 657 | timers1: timer@44000000 { | |
| 658 | #address-cells = <1>; | |
| 659 | #size-cells = <0>; | |
| 660 | compatible = "st,stm32-timers"; | |
| 661 | reg = <0x44000000 0x400>; | |
| 6e391c7d PD |
662 | interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>, |
| 663 | <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>, | |
| 664 | <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>, | |
| 665 | <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>; | |
| 666 | interrupt-names = "brk", "up", "trg-com", "cc"; | |
| a674313c PD |
667 | clocks = <&rcc TIM1_K>; |
| 668 | clock-names = "int"; | |
| 35a54d41 PD |
669 | dmas = <&dmamux1 11 0x400 0x1>, |
| 670 | <&dmamux1 12 0x400 0x1>, | |
| 671 | <&dmamux1 13 0x400 0x1>, | |
| 672 | <&dmamux1 14 0x400 0x1>, | |
| 673 | <&dmamux1 15 0x400 0x1>, | |
| 674 | <&dmamux1 16 0x400 0x1>, | |
| 675 | <&dmamux1 17 0x400 0x1>; | |
| 676 | dma-names = "ch1", "ch2", "ch3", "ch4", | |
| 677 | "up", "trig", "com"; | |
| a674313c PD |
678 | status = "disabled"; |
| 679 | ||
| 680 | pwm { | |
| 681 | compatible = "st,stm32-pwm"; | |
| 62d620c2 | 682 | #pwm-cells = <3>; |
| a674313c PD |
683 | status = "disabled"; |
| 684 | }; | |
| 685 | ||
| 686 | timer@0 { | |
| 687 | compatible = "st,stm32h7-timer-trigger"; | |
| 688 | reg = <0>; | |
| 689 | status = "disabled"; | |
| 690 | }; | |
| 1a4f57c8 PD |
691 | |
| 692 | counter { | |
| 693 | compatible = "st,stm32-timer-counter"; | |
| 694 | status = "disabled"; | |
| 695 | }; | |
| a674313c PD |
696 | }; |
| 697 | ||
| 698 | timers8: timer@44001000 { | |
| 699 | #address-cells = <1>; | |
| 700 | #size-cells = <0>; | |
| 701 | compatible = "st,stm32-timers"; | |
| 702 | reg = <0x44001000 0x400>; | |
| 6e391c7d PD |
703 | interrupts = <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>, |
| 704 | <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>, | |
| 705 | <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>, | |
| 706 | <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>; | |
| 707 | interrupt-names = "brk", "up", "trg-com", "cc"; | |
| a674313c PD |
708 | clocks = <&rcc TIM8_K>; |
| 709 | clock-names = "int"; | |
| 35a54d41 PD |
710 | dmas = <&dmamux1 47 0x400 0x1>, |
| 711 | <&dmamux1 48 0x400 0x1>, | |
| 712 | <&dmamux1 49 0x400 0x1>, | |
| 713 | <&dmamux1 50 0x400 0x1>, | |
| 714 | <&dmamux1 51 0x400 0x1>, | |
| 715 | <&dmamux1 52 0x400 0x1>, | |
| 716 | <&dmamux1 53 0x400 0x1>; | |
| 717 | dma-names = "ch1", "ch2", "ch3", "ch4", | |
| 718 | "up", "trig", "com"; | |
| a674313c PD |
719 | status = "disabled"; |
| 720 | ||
| 721 | pwm { | |
| 722 | compatible = "st,stm32-pwm"; | |
| 62d620c2 | 723 | #pwm-cells = <3>; |
| a674313c PD |
724 | status = "disabled"; |
| 725 | }; | |
| 726 | ||
| 727 | timer@7 { | |
| 728 | compatible = "st,stm32h7-timer-trigger"; | |
| 729 | reg = <7>; | |
| 730 | status = "disabled"; | |
| 731 | }; | |
| 1a4f57c8 PD |
732 | |
| 733 | counter { | |
| 734 | compatible = "st,stm32-timer-counter"; | |
| 735 | status = "disabled"; | |
| 736 | }; | |
| a674313c PD |
737 | }; |
| 738 | ||
| 739 | usart6: serial@44003000 { | |
| 740 | compatible = "st,stm32h7-uart"; | |
| 741 | reg = <0x44003000 0x400>; | |
| 7e549345 | 742 | interrupts-extended = <&exti 29 IRQ_TYPE_LEVEL_HIGH>; |
| a674313c | 743 | clocks = <&rcc USART6_K>; |
| 7e549345 | 744 | wakeup-source; |
| 189ec2fe PD |
745 | dmas = <&dmamux1 71 0x400 0x15>, |
| 746 | <&dmamux1 72 0x400 0x11>; | |
| 747 | dma-names = "rx", "tx"; | |
| a674313c PD |
748 | status = "disabled"; |
| 749 | }; | |
| 750 | ||
| 2366160e PC |
751 | spi1: spi@44004000 { |
| 752 | #address-cells = <1>; | |
| 753 | #size-cells = <0>; | |
| 754 | compatible = "st,stm32h7-spi"; | |
| 755 | reg = <0x44004000 0x400>; | |
| 756 | interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>; | |
| 757 | clocks = <&rcc SPI1_K>; | |
| 758 | resets = <&rcc SPI1_R>; | |
| 759 | dmas = <&dmamux1 37 0x400 0x05>, | |
| 760 | <&dmamux1 38 0x400 0x05>; | |
| 761 | dma-names = "rx", "tx"; | |
| 762 | status = "disabled"; | |
| 763 | }; | |
| 764 | ||
| fe915336 PD |
765 | i2s1: audio-controller@44004000 { |
| 766 | compatible = "st,stm32h7-i2s"; | |
| 767 | #sound-dai-cells = <0>; | |
| 768 | reg = <0x44004000 0x400>; | |
| 769 | interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>; | |
| 770 | dmas = <&dmamux1 37 0x400 0x01>, | |
| 771 | <&dmamux1 38 0x400 0x01>; | |
| 772 | dma-names = "rx", "tx"; | |
| 773 | status = "disabled"; | |
| 774 | }; | |
| 775 | ||
| 2366160e PC |
776 | spi4: spi@44005000 { |
| 777 | #address-cells = <1>; | |
| 778 | #size-cells = <0>; | |
| 779 | compatible = "st,stm32h7-spi"; | |
| 780 | reg = <0x44005000 0x400>; | |
| 781 | interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>; | |
| 782 | clocks = <&rcc SPI4_K>; | |
| 783 | resets = <&rcc SPI4_R>; | |
| 784 | dmas = <&dmamux1 83 0x400 0x05>, | |
| 785 | <&dmamux1 84 0x400 0x05>; | |
| 786 | dma-names = "rx", "tx"; | |
| 787 | status = "disabled"; | |
| 788 | }; | |
| 789 | ||
| a674313c PD |
790 | timers15: timer@44006000 { |
| 791 | #address-cells = <1>; | |
| 792 | #size-cells = <0>; | |
| 793 | compatible = "st,stm32-timers"; | |
| 794 | reg = <0x44006000 0x400>; | |
| 6e391c7d PD |
795 | interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>; |
| 796 | interrupt-names = "global"; | |
| a674313c PD |
797 | clocks = <&rcc TIM15_K>; |
| 798 | clock-names = "int"; | |
| 35a54d41 PD |
799 | dmas = <&dmamux1 105 0x400 0x1>, |
| 800 | <&dmamux1 106 0x400 0x1>, | |
| 801 | <&dmamux1 107 0x400 0x1>, | |
| 802 | <&dmamux1 108 0x400 0x1>; | |
| 803 | dma-names = "ch1", "up", "trig", "com"; | |
| a674313c PD |
804 | status = "disabled"; |
| 805 | ||
| 806 | pwm { | |
| 807 | compatible = "st,stm32-pwm"; | |
| 62d620c2 | 808 | #pwm-cells = <3>; |
| a674313c PD |
809 | status = "disabled"; |
| 810 | }; | |
| 811 | ||
| 812 | timer@14 { | |
| 813 | compatible = "st,stm32h7-timer-trigger"; | |
| 814 | reg = <14>; | |
| 815 | status = "disabled"; | |
| 816 | }; | |
| 817 | }; | |
| 818 | ||
| 819 | timers16: timer@44007000 { | |
| 820 | #address-cells = <1>; | |
| 821 | #size-cells = <0>; | |
| 822 | compatible = "st,stm32-timers"; | |
| 823 | reg = <0x44007000 0x400>; | |
| 6e391c7d PD |
824 | interrupts = <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>; |
| 825 | interrupt-names = "global"; | |
| a674313c PD |
826 | clocks = <&rcc TIM16_K>; |
| 827 | clock-names = "int"; | |
| 35a54d41 PD |
828 | dmas = <&dmamux1 109 0x400 0x1>, |
| 829 | <&dmamux1 110 0x400 0x1>; | |
| 830 | dma-names = "ch1", "up"; | |
| a674313c PD |
831 | status = "disabled"; |
| 832 | ||
| 833 | pwm { | |
| 834 | compatible = "st,stm32-pwm"; | |
| 62d620c2 | 835 | #pwm-cells = <3>; |
| a674313c PD |
836 | status = "disabled"; |
| 837 | }; | |
| 838 | timer@15 { | |
| 839 | compatible = "st,stm32h7-timer-trigger"; | |
| 840 | reg = <15>; | |
| 841 | status = "disabled"; | |
| 842 | }; | |
| 843 | }; | |
| 844 | ||
| 845 | timers17: timer@44008000 { | |
| 846 | #address-cells = <1>; | |
| 847 | #size-cells = <0>; | |
| 848 | compatible = "st,stm32-timers"; | |
| 849 | reg = <0x44008000 0x400>; | |
| 6e391c7d PD |
850 | interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>; |
| 851 | interrupt-names = "global"; | |
| a674313c PD |
852 | clocks = <&rcc TIM17_K>; |
| 853 | clock-names = "int"; | |
| 35a54d41 PD |
854 | dmas = <&dmamux1 111 0x400 0x1>, |
| 855 | <&dmamux1 112 0x400 0x1>; | |
| 856 | dma-names = "ch1", "up"; | |
| a674313c PD |
857 | status = "disabled"; |
| 858 | ||
| 859 | pwm { | |
| 860 | compatible = "st,stm32-pwm"; | |
| 62d620c2 | 861 | #pwm-cells = <3>; |
| a674313c PD |
862 | status = "disabled"; |
| 863 | }; | |
| 864 | ||
| 865 | timer@16 { | |
| 866 | compatible = "st,stm32h7-timer-trigger"; | |
| 867 | reg = <16>; | |
| 868 | status = "disabled"; | |
| 869 | }; | |
| 870 | }; | |
| 871 | ||
| 2366160e PC |
872 | spi5: spi@44009000 { |
| 873 | #address-cells = <1>; | |
| 874 | #size-cells = <0>; | |
| 875 | compatible = "st,stm32h7-spi"; | |
| 876 | reg = <0x44009000 0x400>; | |
| 877 | interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>; | |
| 878 | clocks = <&rcc SPI5_K>; | |
| 879 | resets = <&rcc SPI5_R>; | |
| 880 | dmas = <&dmamux1 85 0x400 0x05>, | |
| 881 | <&dmamux1 86 0x400 0x05>; | |
| 882 | dma-names = "rx", "tx"; | |
| 883 | status = "disabled"; | |
| 884 | }; | |
| 885 | ||
| fe915336 PD |
886 | sai1: sai@4400a000 { |
| 887 | compatible = "st,stm32h7-sai"; | |
| 888 | #address-cells = <1>; | |
| 889 | #size-cells = <1>; | |
| 890 | ranges = <0 0x4400a000 0x400>; | |
| 891 | reg = <0x4400a000 0x4>, <0x4400a3f0 0x10>; | |
| 892 | interrupts = <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>; | |
| 893 | resets = <&rcc SAI1_R>; | |
| 894 | status = "disabled"; | |
| 895 | ||
| 896 | sai1a: audio-controller@4400a004 { | |
| 897 | #sound-dai-cells = <0>; | |
| 898 | ||
| 899 | compatible = "st,stm32-sai-sub-a"; | |
| bd485f9b | 900 | reg = <0x4 0x20>; |
| fe915336 PD |
901 | clocks = <&rcc SAI1_K>; |
| 902 | clock-names = "sai_ck"; | |
| 903 | dmas = <&dmamux1 87 0x400 0x01>; | |
| 904 | status = "disabled"; | |
| 905 | }; | |
| 906 | ||
| 907 | sai1b: audio-controller@4400a024 { | |
| 908 | #sound-dai-cells = <0>; | |
| 909 | compatible = "st,stm32-sai-sub-b"; | |
| bd485f9b | 910 | reg = <0x24 0x20>; |
| fe915336 PD |
911 | clocks = <&rcc SAI1_K>; |
| 912 | clock-names = "sai_ck"; | |
| 913 | dmas = <&dmamux1 88 0x400 0x01>; | |
| 914 | status = "disabled"; | |
| 915 | }; | |
| 916 | }; | |
| 917 | ||
| 918 | sai2: sai@4400b000 { | |
| 919 | compatible = "st,stm32h7-sai"; | |
| 920 | #address-cells = <1>; | |
| 921 | #size-cells = <1>; | |
| 922 | ranges = <0 0x4400b000 0x400>; | |
| 923 | reg = <0x4400b000 0x4>, <0x4400b3f0 0x10>; | |
| 924 | interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>; | |
| 925 | resets = <&rcc SAI2_R>; | |
| 926 | status = "disabled"; | |
| 927 | ||
| 928 | sai2a: audio-controller@4400b004 { | |
| 929 | #sound-dai-cells = <0>; | |
| 930 | compatible = "st,stm32-sai-sub-a"; | |
| bd485f9b | 931 | reg = <0x4 0x20>; |
| fe915336 PD |
932 | clocks = <&rcc SAI2_K>; |
| 933 | clock-names = "sai_ck"; | |
| 934 | dmas = <&dmamux1 89 0x400 0x01>; | |
| 935 | status = "disabled"; | |
| 936 | }; | |
| 937 | ||
| 938 | sai2b: audio-controller@4400b024 { | |
| 939 | #sound-dai-cells = <0>; | |
| 940 | compatible = "st,stm32-sai-sub-b"; | |
| bd485f9b | 941 | reg = <0x24 0x20>; |
| fe915336 PD |
942 | clocks = <&rcc SAI2_K>; |
| 943 | clock-names = "sai_ck"; | |
| 944 | dmas = <&dmamux1 90 0x400 0x01>; | |
| 945 | status = "disabled"; | |
| 946 | }; | |
| 947 | }; | |
| 948 | ||
| 949 | sai3: sai@4400c000 { | |
| 950 | compatible = "st,stm32h7-sai"; | |
| 951 | #address-cells = <1>; | |
| 952 | #size-cells = <1>; | |
| 953 | ranges = <0 0x4400c000 0x400>; | |
| 954 | reg = <0x4400c000 0x4>, <0x4400c3f0 0x10>; | |
| 955 | interrupts = <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>; | |
| 956 | resets = <&rcc SAI3_R>; | |
| 957 | status = "disabled"; | |
| 958 | ||
| 959 | sai3a: audio-controller@4400c004 { | |
| 960 | #sound-dai-cells = <0>; | |
| 961 | compatible = "st,stm32-sai-sub-a"; | |
| bd485f9b | 962 | reg = <0x04 0x20>; |
| fe915336 PD |
963 | clocks = <&rcc SAI3_K>; |
| 964 | clock-names = "sai_ck"; | |
| 965 | dmas = <&dmamux1 113 0x400 0x01>; | |
| 966 | status = "disabled"; | |
| 967 | }; | |
| 968 | ||
| 969 | sai3b: audio-controller@4400c024 { | |
| 970 | #sound-dai-cells = <0>; | |
| 971 | compatible = "st,stm32-sai-sub-b"; | |
| bd485f9b | 972 | reg = <0x24 0x20>; |
| fe915336 PD |
973 | clocks = <&rcc SAI3_K>; |
| 974 | clock-names = "sai_ck"; | |
| 975 | dmas = <&dmamux1 114 0x400 0x01>; | |
| 976 | status = "disabled"; | |
| 977 | }; | |
| 978 | }; | |
| 979 | ||
| 2366160e PC |
980 | dfsdm: dfsdm@4400d000 { |
| 981 | compatible = "st,stm32mp1-dfsdm"; | |
| 982 | reg = <0x4400d000 0x800>; | |
| 983 | clocks = <&rcc DFSDM_K>; | |
| 984 | clock-names = "dfsdm"; | |
| 985 | #address-cells = <1>; | |
| 986 | #size-cells = <0>; | |
| 987 | status = "disabled"; | |
| 988 | ||
| 989 | dfsdm0: filter@0 { | |
| 990 | compatible = "st,stm32-dfsdm-adc"; | |
| 991 | #io-channel-cells = <1>; | |
| 992 | reg = <0>; | |
| 993 | interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>; | |
| 994 | dmas = <&dmamux1 101 0x400 0x01>; | |
| 995 | dma-names = "rx"; | |
| 996 | status = "disabled"; | |
| 997 | }; | |
| 998 | ||
| 999 | dfsdm1: filter@1 { | |
| 1000 | compatible = "st,stm32-dfsdm-adc"; | |
| 1001 | #io-channel-cells = <1>; | |
| 1002 | reg = <1>; | |
| 1003 | interrupts = <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>; | |
| 1004 | dmas = <&dmamux1 102 0x400 0x01>; | |
| 1005 | dma-names = "rx"; | |
| 1006 | status = "disabled"; | |
| 1007 | }; | |
| 1008 | ||
| 1009 | dfsdm2: filter@2 { | |
| 1010 | compatible = "st,stm32-dfsdm-adc"; | |
| 1011 | #io-channel-cells = <1>; | |
| 1012 | reg = <2>; | |
| 1013 | interrupts = <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>; | |
| 1014 | dmas = <&dmamux1 103 0x400 0x01>; | |
| 1015 | dma-names = "rx"; | |
| 1016 | status = "disabled"; | |
| 1017 | }; | |
| 1018 | ||
| 1019 | dfsdm3: filter@3 { | |
| 1020 | compatible = "st,stm32-dfsdm-adc"; | |
| 1021 | #io-channel-cells = <1>; | |
| 1022 | reg = <3>; | |
| 1023 | interrupts = <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>; | |
| 1024 | dmas = <&dmamux1 104 0x400 0x01>; | |
| 1025 | dma-names = "rx"; | |
| 1026 | status = "disabled"; | |
| 1027 | }; | |
| 1028 | ||
| 1029 | dfsdm4: filter@4 { | |
| 1030 | compatible = "st,stm32-dfsdm-adc"; | |
| 1031 | #io-channel-cells = <1>; | |
| 1032 | reg = <4>; | |
| 1033 | interrupts = <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>; | |
| 1034 | dmas = <&dmamux1 91 0x400 0x01>; | |
| 1035 | dma-names = "rx"; | |
| 1036 | status = "disabled"; | |
| 1037 | }; | |
| 1038 | ||
| 1039 | dfsdm5: filter@5 { | |
| 1040 | compatible = "st,stm32-dfsdm-adc"; | |
| 1041 | #io-channel-cells = <1>; | |
| 1042 | reg = <5>; | |
| 1043 | interrupts = <GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>; | |
| 1044 | dmas = <&dmamux1 92 0x400 0x01>; | |
| 1045 | dma-names = "rx"; | |
| 1046 | status = "disabled"; | |
| 1047 | }; | |
| 1048 | }; | |
| 1049 | ||
| 1a4f57c8 | 1050 | dma1: dma-controller@48000000 { |
| a674313c PD |
1051 | compatible = "st,stm32-dma"; |
| 1052 | reg = <0x48000000 0x400>; | |
| 1053 | interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>, | |
| 1054 | <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>, | |
| 1055 | <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>, | |
| 1056 | <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>, | |
| 1057 | <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>, | |
| 1058 | <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>, | |
| 1059 | <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>, | |
| 1060 | <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>; | |
| 1061 | clocks = <&rcc DMA1>; | |
| 1b28a5e2 | 1062 | resets = <&rcc DMA1_R>; |
| a674313c PD |
1063 | #dma-cells = <4>; |
| 1064 | st,mem2mem; | |
| 1065 | dma-requests = <8>; | |
| 1066 | }; | |
| 1067 | ||
| 1a4f57c8 | 1068 | dma2: dma-controller@48001000 { |
| a674313c PD |
1069 | compatible = "st,stm32-dma"; |
| 1070 | reg = <0x48001000 0x400>; | |
| 1071 | interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>, | |
| 1072 | <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>, | |
| 1073 | <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>, | |
| 1074 | <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>, | |
| 1075 | <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>, | |
| 1076 | <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>, | |
| 1077 | <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>, | |
| 1078 | <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>; | |
| 1079 | clocks = <&rcc DMA2>; | |
| 1b28a5e2 | 1080 | resets = <&rcc DMA2_R>; |
| a674313c PD |
1081 | #dma-cells = <4>; |
| 1082 | st,mem2mem; | |
| 1083 | dma-requests = <8>; | |
| 1084 | }; | |
| 1085 | ||
| 1086 | dmamux1: dma-router@48002000 { | |
| 1087 | compatible = "st,stm32h7-dmamux"; | |
| f050e3fe | 1088 | reg = <0x48002000 0x40>; |
| a674313c PD |
1089 | #dma-cells = <3>; |
| 1090 | dma-requests = <128>; | |
| 1091 | dma-masters = <&dma1 &dma2>; | |
| 1092 | dma-channels = <16>; | |
| 1093 | clocks = <&rcc DMAMUX>; | |
| 1b28a5e2 | 1094 | resets = <&rcc DMAMUX_R>; |
| a674313c PD |
1095 | }; |
| 1096 | ||
| 638ee5af PC |
1097 | adc: adc@48003000 { |
| 1098 | compatible = "st,stm32mp1-adc-core"; | |
| 1099 | reg = <0x48003000 0x400>; | |
| 1100 | interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>, | |
| 1101 | <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>; | |
| 1102 | clocks = <&rcc ADC12>, <&rcc ADC12_K>; | |
| 1103 | clock-names = "bus", "adc"; | |
| 1104 | interrupt-controller; | |
| 62d620c2 | 1105 | st,syscfg = <&syscfg>; |
| 638ee5af PC |
1106 | #interrupt-cells = <1>; |
| 1107 | #address-cells = <1>; | |
| 1108 | #size-cells = <0>; | |
| 1109 | status = "disabled"; | |
| 1110 | ||
| 1111 | adc1: adc@0 { | |
| 1112 | compatible = "st,stm32mp1-adc"; | |
| 1113 | #io-channel-cells = <1>; | |
| f959118b PC |
1114 | #address-cells = <1>; |
| 1115 | #size-cells = <0>; | |
| 638ee5af PC |
1116 | reg = <0x0>; |
| 1117 | interrupt-parent = <&adc>; | |
| 1118 | interrupts = <0>; | |
| 2366160e PC |
1119 | dmas = <&dmamux1 9 0x400 0x01>; |
| 1120 | dma-names = "rx"; | |
| 638ee5af PC |
1121 | status = "disabled"; |
| 1122 | }; | |
| 1123 | ||
| 1124 | adc2: adc@100 { | |
| 1125 | compatible = "st,stm32mp1-adc"; | |
| 1126 | #io-channel-cells = <1>; | |
| f959118b PC |
1127 | #address-cells = <1>; |
| 1128 | #size-cells = <0>; | |
| 638ee5af PC |
1129 | reg = <0x100>; |
| 1130 | interrupt-parent = <&adc>; | |
| 1131 | interrupts = <1>; | |
| 2366160e PC |
1132 | dmas = <&dmamux1 10 0x400 0x01>; |
| 1133 | dma-names = "rx"; | |
| f959118b PC |
1134 | nvmem-cells = <&vrefint>; |
| 1135 | nvmem-cell-names = "vrefint"; | |
| 638ee5af | 1136 | status = "disabled"; |
| f959118b PC |
1137 | channel@13 { |
| 1138 | reg = <13>; | |
| 1139 | label = "vrefint"; | |
| 1140 | }; | |
| 1141 | channel@14 { | |
| 1142 | reg = <14>; | |
| 1143 | label = "vddcore"; | |
| 1144 | }; | |
| 638ee5af PC |
1145 | }; |
| 1146 | }; | |
| 1147 | ||
| 7e549345 | 1148 | sdmmc3: mmc@48004000 { |
| 189ec2fe | 1149 | compatible = "st,stm32-sdmmc2", "arm,pl18x", "arm,primecell"; |
| f050e3fe | 1150 | arm,primecell-periphid = <0x00253180>; |
| 35a54d41 | 1151 | reg = <0x48004000 0x400>; |
| 1a4f57c8 | 1152 | interrupts = <GIC_SPI 137 IRQ_TYPE_LEVEL_HIGH>; |
| a674313c | 1153 | clocks = <&rcc SDMMC3_K>; |
| 35a54d41 | 1154 | clock-names = "apb_pclk"; |
| a674313c | 1155 | resets = <&rcc SDMMC3_R>; |
| a674313c PD |
1156 | cap-sd-highspeed; |
| 1157 | cap-mmc-highspeed; | |
| 1158 | max-frequency = <120000000>; | |
| 1159 | status = "disabled"; | |
| 1160 | }; | |
| 1161 | ||
| 8e9c94d7 | 1162 | usbotg_hs: usb-otg@49000000 { |
| 1b28a5e2 | 1163 | compatible = "st,stm32mp15-hsotg", "snps,dwc2"; |
| 8e9c94d7 | 1164 | reg = <0x49000000 0x10000>; |
| 61ad1a52 PD |
1165 | clocks = <&rcc USBO_K>, <&usbphyc>; |
| 1166 | clock-names = "otg", "utmi"; | |
| 8e9c94d7 PC |
1167 | resets = <&rcc USBO_R>; |
| 1168 | reset-names = "dwc2"; | |
| 1169 | interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>; | |
| f050e3fe | 1170 | g-rx-fifo-size = <512>; |
| 8e9c94d7 | 1171 | g-np-tx-fifo-size = <32>; |
| f050e3fe | 1172 | g-tx-fifo-size = <256 16 16 16 16 16 16 16>; |
| 8e9c94d7 | 1173 | dr_mode = "otg"; |
| bd485f9b | 1174 | otg-rev = <0x200>; |
| c50151d4 | 1175 | usb33d-supply = <&usb33>; |
| 8e9c94d7 PC |
1176 | status = "disabled"; |
| 1177 | }; | |
| 1178 | ||
| 1958dae4 FD |
1179 | ipcc: mailbox@4c001000 { |
| 1180 | compatible = "st,stm32mp1-ipcc"; | |
| 1181 | #mbox-cells = <1>; | |
| 1182 | reg = <0x4c001000 0x400>; | |
| 1183 | st,proc-id = <0>; | |
| 1184 | interrupts-extended = | |
| 152498d5 PD |
1185 | <&exti 61 1>, |
| 1186 | <&intc GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>; | |
| 1187 | interrupt-names = "rx", "tx"; | |
| 1958dae4 | 1188 | clocks = <&rcc IPCC>; |
| 35a54d41 | 1189 | wakeup-source; |
| 1958dae4 FD |
1190 | status = "disabled"; |
| 1191 | }; | |
| 1192 | ||
| fe915336 PD |
1193 | dcmi: dcmi@4c006000 { |
| 1194 | compatible = "st,stm32-dcmi"; | |
| 1195 | reg = <0x4c006000 0x400>; | |
| 1196 | interrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>; | |
| 1197 | resets = <&rcc CAMITF_R>; | |
| 1198 | clocks = <&rcc DCMI>; | |
| 1199 | clock-names = "mclk"; | |
| f050e3fe | 1200 | dmas = <&dmamux1 75 0x400 0x01>; |
| fe915336 PD |
1201 | dma-names = "tx"; |
| 1202 | status = "disabled"; | |
| 1203 | }; | |
| 1204 | ||
| a674313c PD |
1205 | rcc: rcc@50000000 { |
| 1206 | compatible = "st,stm32mp1-rcc", "syscon"; | |
| 1207 | reg = <0x50000000 0x1000>; | |
| 1208 | #clock-cells = <1>; | |
| 1209 | #reset-cells = <1>; | |
| 3d152455 EC |
1210 | |
| 1211 | clock-names = "hse", "hsi", "csi", "lse", "lsi"; | |
| 1212 | clocks = <&clk_hse>, <&clk_hsi>, <&clk_csi>, | |
| 1213 | <&clk_lse>, <&clk_lsi>; | |
| a674313c PD |
1214 | }; |
| 1215 | ||
| 7915b991 PD |
1216 | pwr_regulators: pwr@50001000 { |
| 1217 | compatible = "st,stm32mp1,pwr-reg"; | |
| 1218 | reg = <0x50001000 0x10>; | |
| 1219 | ||
| 1220 | reg11: reg11 { | |
| 1221 | regulator-name = "reg11"; | |
| 1222 | regulator-min-microvolt = <1100000>; | |
| 1223 | regulator-max-microvolt = <1100000>; | |
| 1224 | }; | |
| a674313c | 1225 | |
| 7915b991 PD |
1226 | reg18: reg18 { |
| 1227 | regulator-name = "reg18"; | |
| 1228 | regulator-min-microvolt = <1800000>; | |
| 1229 | regulator-max-microvolt = <1800000>; | |
| 1230 | }; | |
| a674313c | 1231 | |
| 7915b991 PD |
1232 | usb33: usb33 { |
| 1233 | regulator-name = "usb33"; | |
| 1234 | regulator-min-microvolt = <3300000>; | |
| 1235 | regulator-max-microvolt = <3300000>; | |
| a674313c PD |
1236 | }; |
| 1237 | }; | |
| 1238 | ||
| 500327e2 | 1239 | pwr_mcu: pwr_mcu@50001014 { |
| 62f95af9 | 1240 | compatible = "st,stm32mp151-pwr-mcu", "syscon"; |
| 500327e2 PD |
1241 | reg = <0x50001014 0x4>; |
| 1242 | }; | |
| 1243 | ||
| a674313c PD |
1244 | exti: interrupt-controller@5000d000 { |
| 1245 | compatible = "st,stm32mp1-exti", "syscon"; | |
| 1246 | interrupt-controller; | |
| 1247 | #interrupt-cells = <2>; | |
| 1248 | reg = <0x5000d000 0x400>; | |
| 1249 | }; | |
| 1250 | ||
| 2366160e | 1251 | syscfg: syscon@50020000 { |
| 6c09eb9e | 1252 | compatible = "st,stm32mp157-syscfg", "syscon"; |
| a674313c | 1253 | reg = <0x50020000 0x400>; |
| 35a54d41 | 1254 | clocks = <&rcc SYSCFG>; |
| a674313c PD |
1255 | }; |
| 1256 | ||
| 1257 | lptimer2: timer@50021000 { | |
| 1258 | #address-cells = <1>; | |
| 1259 | #size-cells = <0>; | |
| 1260 | compatible = "st,stm32-lptimer"; | |
| 1261 | reg = <0x50021000 0x400>; | |
| f050e3fe | 1262 | interrupts-extended = <&exti 48 IRQ_TYPE_LEVEL_HIGH>; |
| a674313c PD |
1263 | clocks = <&rcc LPTIM2_K>; |
| 1264 | clock-names = "mux"; | |
| f050e3fe | 1265 | wakeup-source; |
| a674313c PD |
1266 | status = "disabled"; |
| 1267 | ||
| 1268 | pwm { | |
| 1269 | compatible = "st,stm32-pwm-lp"; | |
| 1270 | #pwm-cells = <3>; | |
| 1271 | status = "disabled"; | |
| 1272 | }; | |
| 1273 | ||
| 1274 | trigger@1 { | |
| 1275 | compatible = "st,stm32-lptimer-trigger"; | |
| 1276 | reg = <1>; | |
| 1277 | status = "disabled"; | |
| 1278 | }; | |
| 1279 | ||
| 1280 | counter { | |
| 1281 | compatible = "st,stm32-lptimer-counter"; | |
| 1282 | status = "disabled"; | |
| 1283 | }; | |
| 1284 | }; | |
| 1285 | ||
| 1286 | lptimer3: timer@50022000 { | |
| 1287 | #address-cells = <1>; | |
| 1288 | #size-cells = <0>; | |
| 1289 | compatible = "st,stm32-lptimer"; | |
| 1290 | reg = <0x50022000 0x400>; | |
| f050e3fe | 1291 | interrupts-extended = <&exti 50 IRQ_TYPE_LEVEL_HIGH>; |
| a674313c PD |
1292 | clocks = <&rcc LPTIM3_K>; |
| 1293 | clock-names = "mux"; | |
| f050e3fe | 1294 | wakeup-source; |
| a674313c PD |
1295 | status = "disabled"; |
| 1296 | ||
| 1297 | pwm { | |
| 1298 | compatible = "st,stm32-pwm-lp"; | |
| 1299 | #pwm-cells = <3>; | |
| 1300 | status = "disabled"; | |
| 1301 | }; | |
| 1302 | ||
| 1303 | trigger@2 { | |
| 1304 | compatible = "st,stm32-lptimer-trigger"; | |
| 1305 | reg = <2>; | |
| 1306 | status = "disabled"; | |
| 1307 | }; | |
| 1308 | }; | |
| 1309 | ||
| 1310 | lptimer4: timer@50023000 { | |
| 1311 | compatible = "st,stm32-lptimer"; | |
| 1312 | reg = <0x50023000 0x400>; | |
| f050e3fe | 1313 | interrupts-extended = <&exti 52 IRQ_TYPE_LEVEL_HIGH>; |
| a674313c PD |
1314 | clocks = <&rcc LPTIM4_K>; |
| 1315 | clock-names = "mux"; | |
| f050e3fe | 1316 | wakeup-source; |
| a674313c PD |
1317 | status = "disabled"; |
| 1318 | ||
| 1319 | pwm { | |
| 1320 | compatible = "st,stm32-pwm-lp"; | |
| 1321 | #pwm-cells = <3>; | |
| 1322 | status = "disabled"; | |
| 1323 | }; | |
| 1324 | }; | |
| 1325 | ||
| 1326 | lptimer5: timer@50024000 { | |
| 1327 | compatible = "st,stm32-lptimer"; | |
| 1328 | reg = <0x50024000 0x400>; | |
| f050e3fe | 1329 | interrupts-extended = <&exti 53 IRQ_TYPE_LEVEL_HIGH>; |
| a674313c PD |
1330 | clocks = <&rcc LPTIM5_K>; |
| 1331 | clock-names = "mux"; | |
| f050e3fe | 1332 | wakeup-source; |
| a674313c PD |
1333 | status = "disabled"; |
| 1334 | ||
| 1335 | pwm { | |
| 1336 | compatible = "st,stm32-pwm-lp"; | |
| 1337 | #pwm-cells = <3>; | |
| 1338 | status = "disabled"; | |
| 1339 | }; | |
| 1340 | }; | |
| 1341 | ||
| 1342 | vrefbuf: vrefbuf@50025000 { | |
| 1343 | compatible = "st,stm32-vrefbuf"; | |
| 1344 | reg = <0x50025000 0x8>; | |
| 1345 | regulator-min-microvolt = <1500000>; | |
| 1346 | regulator-max-microvolt = <2500000>; | |
| 1347 | clocks = <&rcc VREF>; | |
| 1348 | status = "disabled"; | |
| 1349 | }; | |
| 1350 | ||
| fe915336 PD |
1351 | sai4: sai@50027000 { |
| 1352 | compatible = "st,stm32h7-sai"; | |
| 1353 | #address-cells = <1>; | |
| 1354 | #size-cells = <1>; | |
| 1355 | ranges = <0 0x50027000 0x400>; | |
| 1356 | reg = <0x50027000 0x4>, <0x500273f0 0x10>; | |
| 1357 | interrupts = <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>; | |
| 1358 | resets = <&rcc SAI4_R>; | |
| 1359 | status = "disabled"; | |
| 1360 | ||
| 1361 | sai4a: audio-controller@50027004 { | |
| 1362 | #sound-dai-cells = <0>; | |
| 1363 | compatible = "st,stm32-sai-sub-a"; | |
| bd485f9b | 1364 | reg = <0x04 0x20>; |
| fe915336 PD |
1365 | clocks = <&rcc SAI4_K>; |
| 1366 | clock-names = "sai_ck"; | |
| 1367 | dmas = <&dmamux1 99 0x400 0x01>; | |
| 1368 | status = "disabled"; | |
| 1369 | }; | |
| 1370 | ||
| 1371 | sai4b: audio-controller@50027024 { | |
| 1372 | #sound-dai-cells = <0>; | |
| 1373 | compatible = "st,stm32-sai-sub-b"; | |
| bd485f9b | 1374 | reg = <0x24 0x20>; |
| fe915336 PD |
1375 | clocks = <&rcc SAI4_K>; |
| 1376 | clock-names = "sai_ck"; | |
| 1377 | dmas = <&dmamux1 100 0x400 0x01>; | |
| 1378 | status = "disabled"; | |
| 1379 | }; | |
| 1380 | }; | |
| 1381 | ||
| 35a54d41 PD |
1382 | dts: thermal@50028000 { |
| 1383 | compatible = "st,stm32-thermal"; | |
| 1384 | reg = <0x50028000 0x100>; | |
| 1385 | interrupts = <GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>; | |
| 1386 | clocks = <&rcc TMPSENS>; | |
| 1387 | clock-names = "pclk"; | |
| 1388 | #thermal-sensor-cells = <0>; | |
| 1389 | status = "disabled"; | |
| 1390 | }; | |
| 1391 | ||
| 2366160e PC |
1392 | hash1: hash@54002000 { |
| 1393 | compatible = "st,stm32f756-hash"; | |
| 1394 | reg = <0x54002000 0x400>; | |
| 1395 | interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>; | |
| 1396 | clocks = <&rcc HASH1>; | |
| 1397 | resets = <&rcc HASH1_R>; | |
| f050e3fe | 1398 | dmas = <&mdma1 31 0x2 0x1000A02 0x0 0x0>; |
| 2366160e PC |
1399 | dma-names = "in"; |
| 1400 | dma-maxburst = <2>; | |
| 1401 | status = "disabled"; | |
| 1402 | }; | |
| 1403 | ||
| a674313c PD |
1404 | rng1: rng@54003000 { |
| 1405 | compatible = "st,stm32-rng"; | |
| 1406 | reg = <0x54003000 0x400>; | |
| 1407 | clocks = <&rcc RNG1_K>; | |
| 1408 | resets = <&rcc RNG1_R>; | |
| 1409 | status = "disabled"; | |
| 1410 | }; | |
| 1411 | ||
| 1a4f57c8 | 1412 | mdma1: dma-controller@58000000 { |
| a674313c PD |
1413 | compatible = "st,stm32h7-mdma"; |
| 1414 | reg = <0x58000000 0x1000>; | |
| 1415 | interrupts = <GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>; | |
| 1416 | clocks = <&rcc MDMA>; | |
| 1b28a5e2 | 1417 | resets = <&rcc MDMA_R>; |
| a674313c PD |
1418 | #dma-cells = <5>; |
| 1419 | dma-channels = <32>; | |
| 1420 | dma-requests = <48>; | |
| 1421 | }; | |
| 1422 | ||
| acdaae63 CK |
1423 | fmc: memory-controller@58002000 { |
| 1424 | #address-cells = <2>; | |
| 1425 | #size-cells = <1>; | |
| 1426 | compatible = "st,stm32mp1-fmc2-ebi"; | |
| 1427 | reg = <0x58002000 0x1000>; | |
| c4a739ad PD |
1428 | clocks = <&rcc FMC_K>; |
| 1429 | resets = <&rcc FMC_R>; | |
| 1430 | status = "disabled"; | |
| acdaae63 CK |
1431 | |
| 1432 | ranges = <0 0 0x60000000 0x04000000>, /* EBI CS 1 */ | |
| 1433 | <1 0 0x64000000 0x04000000>, /* EBI CS 2 */ | |
| 1434 | <2 0 0x68000000 0x04000000>, /* EBI CS 3 */ | |
| 1435 | <3 0 0x6c000000 0x04000000>, /* EBI CS 4 */ | |
| 1436 | <4 0 0x80000000 0x10000000>; /* NAND */ | |
| 1437 | ||
| 1438 | nand-controller@4,0 { | |
| 1439 | #address-cells = <1>; | |
| 1440 | #size-cells = <0>; | |
| 1441 | compatible = "st,stm32mp1-fmc2-nfc"; | |
| 1442 | reg = <4 0x00000000 0x1000>, | |
| 1443 | <4 0x08010000 0x1000>, | |
| 1444 | <4 0x08020000 0x1000>, | |
| 1445 | <4 0x01000000 0x1000>, | |
| 1446 | <4 0x09010000 0x1000>, | |
| 1447 | <4 0x09020000 0x1000>; | |
| 1448 | interrupts = <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>; | |
| 1449 | dmas = <&mdma1 20 0x2 0x12000a02 0x0 0x0>, | |
| 1450 | <&mdma1 20 0x2 0x12000a08 0x0 0x0>, | |
| 1451 | <&mdma1 21 0x2 0x12000a0a 0x0 0x0>; | |
| 1452 | dma-names = "tx", "rx", "ecc"; | |
| 1453 | status = "disabled"; | |
| 1454 | }; | |
| c4a739ad PD |
1455 | }; |
| 1456 | ||
| 2366160e | 1457 | qspi: spi@58003000 { |
| a674313c PD |
1458 | compatible = "st,stm32f469-qspi"; |
| 1459 | reg = <0x58003000 0x1000>, <0x70000000 0x10000000>; | |
| 1460 | reg-names = "qspi", "qspi_mm"; | |
| 1461 | interrupts = <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>; | |
| 2d4180b1 PD |
1462 | dmas = <&mdma1 22 0x2 0x10100002 0x0 0x0>, |
| 1463 | <&mdma1 22 0x2 0x10100008 0x0 0x0>; | |
| 62d620c2 | 1464 | dma-names = "tx", "rx"; |
| a674313c PD |
1465 | clocks = <&rcc QSPI_K>; |
| 1466 | resets = <&rcc QSPI_R>; | |
| 62f95af9 PD |
1467 | #address-cells = <1>; |
| 1468 | #size-cells = <0>; | |
| a674313c PD |
1469 | status = "disabled"; |
| 1470 | }; | |
| 1471 | ||
| 7e549345 | 1472 | sdmmc1: mmc@58005000 { |
| 189ec2fe | 1473 | compatible = "st,stm32-sdmmc2", "arm,pl18x", "arm,primecell"; |
| f050e3fe | 1474 | arm,primecell-periphid = <0x00253180>; |
| 35a54d41 PD |
1475 | reg = <0x58005000 0x1000>; |
| 1476 | interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>; | |
| a674313c | 1477 | clocks = <&rcc SDMMC1_K>; |
| 35a54d41 | 1478 | clock-names = "apb_pclk"; |
| a674313c | 1479 | resets = <&rcc SDMMC1_R>; |
| a674313c PD |
1480 | cap-sd-highspeed; |
| 1481 | cap-mmc-highspeed; | |
| 1482 | max-frequency = <120000000>; | |
| 1a4f57c8 | 1483 | status = "disabled"; |
| a674313c PD |
1484 | }; |
| 1485 | ||
| 7e549345 | 1486 | sdmmc2: mmc@58007000 { |
| 189ec2fe | 1487 | compatible = "st,stm32-sdmmc2", "arm,pl18x", "arm,primecell"; |
| f050e3fe | 1488 | arm,primecell-periphid = <0x00253180>; |
| 35a54d41 | 1489 | reg = <0x58007000 0x1000>; |
| 1a4f57c8 | 1490 | interrupts = <GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>; |
| a674313c | 1491 | clocks = <&rcc SDMMC2_K>; |
| 35a54d41 | 1492 | clock-names = "apb_pclk"; |
| a674313c | 1493 | resets = <&rcc SDMMC2_R>; |
| a674313c PD |
1494 | cap-sd-highspeed; |
| 1495 | cap-mmc-highspeed; | |
| 1496 | max-frequency = <120000000>; | |
| 1497 | status = "disabled"; | |
| 1498 | }; | |
| 1499 | ||
| 1500 | crc1: crc@58009000 { | |
| 1501 | compatible = "st,stm32f7-crc"; | |
| 1502 | reg = <0x58009000 0x400>; | |
| 1503 | clocks = <&rcc CRC1>; | |
| 1504 | status = "disabled"; | |
| 1505 | }; | |
| 1506 | ||
| 2366160e PC |
1507 | ethernet0: ethernet@5800a000 { |
| 1508 | compatible = "st,stm32mp1-dwmac", "snps,dwmac-4.20a"; | |
| 1509 | reg = <0x5800a000 0x2000>; | |
| 1510 | reg-names = "stmmaceth"; | |
| 35a54d41 PD |
1511 | interrupts-extended = <&intc GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>; |
| 1512 | interrupt-names = "macirq"; | |
| 2366160e PC |
1513 | clock-names = "stmmaceth", |
| 1514 | "mac-clk-tx", | |
| 1515 | "mac-clk-rx", | |
| db48e11b | 1516 | "eth-ck", |
| 7e549345 | 1517 | "ptp_ref", |
| 500327e2 | 1518 | "ethstp"; |
| 2366160e PC |
1519 | clocks = <&rcc ETHMAC>, |
| 1520 | <&rcc ETHTX>, | |
| 1521 | <&rcc ETHRX>, | |
| db48e11b | 1522 | <&rcc ETHCK_K>, |
| 7e549345 | 1523 | <&rcc ETHPTP_K>, |
| 500327e2 | 1524 | <&rcc ETHSTP>; |
| 2366160e PC |
1525 | st,syscon = <&syscfg 0x4>; |
| 1526 | snps,mixed-burst; | |
| 1527 | snps,pbl = <2>; | |
| 1a4f57c8 | 1528 | snps,en-tx-lpi-clockgating; |
| 2366160e PC |
1529 | snps,axi-config = <&stmmac_axi_config_0>; |
| 1530 | snps,tso; | |
| 1531 | status = "disabled"; | |
| 2d4180b1 PD |
1532 | |
| 1533 | stmmac_axi_config_0: stmmac-axi-config { | |
| 1534 | snps,wr_osr_lmt = <0x7>; | |
| 1535 | snps,rd_osr_lmt = <0x7>; | |
| 1536 | snps,blen = <0 0 0 0 16 8 4>; | |
| 1537 | }; | |
| 2366160e PC |
1538 | }; |
| 1539 | ||
| f050e3fe | 1540 | usbh_ohci: usb@5800c000 { |
| a674313c PD |
1541 | compatible = "generic-ohci"; |
| 1542 | reg = <0x5800c000 0x1000>; | |
| 69ef98b2 | 1543 | clocks = <&usbphyc>, <&rcc USBH>; |
| a674313c PD |
1544 | resets = <&rcc USBH_R>; |
| 1545 | interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>; | |
| 1546 | status = "disabled"; | |
| 1547 | }; | |
| 1548 | ||
| f050e3fe | 1549 | usbh_ehci: usb@5800d000 { |
| a674313c PD |
1550 | compatible = "generic-ehci"; |
| 1551 | reg = <0x5800d000 0x1000>; | |
| 69ef98b2 | 1552 | clocks = <&usbphyc>, <&rcc USBH>; |
| a674313c PD |
1553 | resets = <&rcc USBH_R>; |
| 1554 | interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>; | |
| 1555 | companion = <&usbh_ohci>; | |
| 1556 | status = "disabled"; | |
| 1557 | }; | |
| 1558 | ||
| a674313c PD |
1559 | ltdc: display-controller@5a001000 { |
| 1560 | compatible = "st,stm32-ltdc"; | |
| 1561 | reg = <0x5a001000 0x400>; | |
| 1562 | interrupts = <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>, | |
| 1563 | <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>; | |
| 1564 | clocks = <&rcc LTDC_PX>; | |
| 1565 | clock-names = "lcd"; | |
| 1566 | resets = <&rcc LTDC_R>; | |
| 1567 | status = "disabled"; | |
| 1568 | }; | |
| 1569 | ||
| 2366160e PC |
1570 | iwdg2: watchdog@5a002000 { |
| 1571 | compatible = "st,stm32mp1-iwdg"; | |
| 1572 | reg = <0x5a002000 0x400>; | |
| 1573 | clocks = <&rcc IWDG2>, <&rcc CK_LSI>; | |
| 1574 | clock-names = "pclk", "lsi"; | |
| 1575 | status = "disabled"; | |
| 1576 | }; | |
| 1577 | ||
| a674313c PD |
1578 | usbphyc: usbphyc@5a006000 { |
| 1579 | #address-cells = <1>; | |
| 1580 | #size-cells = <0>; | |
| 7e549345 | 1581 | #clock-cells = <0>; |
| a674313c PD |
1582 | compatible = "st,stm32mp1-usbphyc"; |
| 1583 | reg = <0x5a006000 0x1000>; | |
| 1584 | clocks = <&rcc USBPHY_K>; | |
| 1585 | resets = <&rcc USBPHY_R>; | |
| c50151d4 PD |
1586 | vdda1v1-supply = <®11>; |
| 1587 | vdda1v8-supply = <®18>; | |
| a674313c PD |
1588 | status = "disabled"; |
| 1589 | ||
| 1590 | usbphyc_port0: usb-phy@0 { | |
| 1591 | #phy-cells = <0>; | |
| 1592 | reg = <0>; | |
| 1593 | }; | |
| 1594 | ||
| 1595 | usbphyc_port1: usb-phy@1 { | |
| 1596 | #phy-cells = <1>; | |
| 1597 | reg = <1>; | |
| 1598 | }; | |
| 1599 | }; | |
| 1600 | ||
| 1601 | usart1: serial@5c000000 { | |
| 1602 | compatible = "st,stm32h7-uart"; | |
| 1603 | reg = <0x5c000000 0x400>; | |
| 7e549345 | 1604 | interrupts-extended = <&exti 26 IRQ_TYPE_LEVEL_HIGH>; |
| a674313c | 1605 | clocks = <&rcc USART1_K>; |
| 7e549345 | 1606 | wakeup-source; |
| a674313c PD |
1607 | status = "disabled"; |
| 1608 | }; | |
| 1609 | ||
| 2366160e PC |
1610 | spi6: spi@5c001000 { |
| 1611 | #address-cells = <1>; | |
| 1612 | #size-cells = <0>; | |
| 1613 | compatible = "st,stm32h7-spi"; | |
| 1614 | reg = <0x5c001000 0x400>; | |
| 1615 | interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>; | |
| 1616 | clocks = <&rcc SPI6_K>; | |
| 1617 | resets = <&rcc SPI6_R>; | |
| 1618 | dmas = <&mdma1 34 0x0 0x40008 0x0 0x0>, | |
| 1619 | <&mdma1 35 0x0 0x40002 0x0 0x0>; | |
| 1620 | dma-names = "rx", "tx"; | |
| 1621 | status = "disabled"; | |
| 1622 | }; | |
| 1623 | ||
| a674313c | 1624 | i2c4: i2c@5c002000 { |
| 500327e2 | 1625 | compatible = "st,stm32mp15-i2c"; |
| a674313c PD |
1626 | reg = <0x5c002000 0x400>; |
| 1627 | interrupt-names = "event", "error"; | |
| 1628 | interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>, | |
| 1629 | <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>; | |
| 1630 | clocks = <&rcc I2C4_K>; | |
| 1631 | resets = <&rcc I2C4_R>; | |
| 1632 | #address-cells = <1>; | |
| 1633 | #size-cells = <0>; | |
| 500327e2 | 1634 | st,syscfg-fmp = <&syscfg 0x4 0x8>; |
| 1b28a5e2 | 1635 | wakeup-source; |
| 7e549345 | 1636 | i2c-analog-filter; |
| a674313c PD |
1637 | status = "disabled"; |
| 1638 | }; | |
| 1639 | ||
| 2366160e PC |
1640 | rtc: rtc@5c004000 { |
| 1641 | compatible = "st,stm32mp1-rtc"; | |
| 1642 | reg = <0x5c004000 0x400>; | |
| 1643 | clocks = <&rcc RTCAPB>, <&rcc RTC>; | |
| 1644 | clock-names = "pclk", "rtc_ck"; | |
| 189ec2fe | 1645 | interrupts-extended = <&exti 19 IRQ_TYPE_LEVEL_HIGH>; |
| 2366160e PC |
1646 | status = "disabled"; |
| 1647 | }; | |
| 1648 | ||
| 1a4f57c8 | 1649 | bsec: efuse@5c005000 { |
| bfe1f08f PD |
1650 | compatible = "st,stm32mp15-bsec"; |
| 1651 | reg = <0x5c005000 0x400>; | |
| 1652 | #address-cells = <1>; | |
| 1653 | #size-cells = <1>; | |
| f959118b | 1654 | part_number_otp: part-number-otp@4 { |
| 6f2e0ad1 PD |
1655 | reg = <0x4 0x1>; |
| 1656 | }; | |
| f959118b PC |
1657 | vrefint: vrefin-cal@52 { |
| 1658 | reg = <0x52 0x2>; | |
| 1659 | }; | |
| 35a54d41 PD |
1660 | ts_cal1: calib@5c { |
| 1661 | reg = <0x5c 0x2>; | |
| 1662 | }; | |
| 1663 | ts_cal2: calib@5e { | |
| 1664 | reg = <0x5e 0x2>; | |
| 1665 | }; | |
| bfe1f08f PD |
1666 | }; |
| 1667 | ||
| a674313c | 1668 | i2c6: i2c@5c009000 { |
| 500327e2 | 1669 | compatible = "st,stm32mp15-i2c"; |
| a674313c PD |
1670 | reg = <0x5c009000 0x400>; |
| 1671 | interrupt-names = "event", "error"; | |
| 1672 | interrupts = <GIC_SPI 135 IRQ_TYPE_LEVEL_HIGH>, | |
| 1673 | <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>; | |
| 1674 | clocks = <&rcc I2C6_K>; | |
| 1675 | resets = <&rcc I2C6_R>; | |
| 1676 | #address-cells = <1>; | |
| 1677 | #size-cells = <0>; | |
| 500327e2 | 1678 | st,syscfg-fmp = <&syscfg 0x4 0x20>; |
| 1b28a5e2 | 1679 | wakeup-source; |
| 7e549345 | 1680 | i2c-analog-filter; |
| a674313c PD |
1681 | status = "disabled"; |
| 1682 | }; | |
| 1a4f57c8 | 1683 | |
| f050e3fe PD |
1684 | tamp: tamp@5c00a000 { |
| 1685 | compatible = "st,stm32-tamp", "syscon", "simple-mfd"; | |
| 1686 | reg = <0x5c00a000 0x400>; | |
| 1687 | }; | |
| 1688 | ||
| 1a4f57c8 PD |
1689 | /* |
| 1690 | * Break node order to solve dependency probe issue between | |
| 1691 | * pinctrl and exti. | |
| 1692 | */ | |
| 69ef98b2 | 1693 | pinctrl: pinctrl@50002000 { |
| 1a4f57c8 PD |
1694 | #address-cells = <1>; |
| 1695 | #size-cells = <1>; | |
| 1696 | compatible = "st,stm32mp157-pinctrl"; | |
| 1697 | ranges = <0 0x50002000 0xa400>; | |
| 1698 | interrupt-parent = <&exti>; | |
| 1699 | st,syscfg = <&exti 0x60 0xff>; | |
| 1a4f57c8 PD |
1700 | |
| 1701 | gpioa: gpio@50002000 { | |
| 1702 | gpio-controller; | |
| 1703 | #gpio-cells = <2>; | |
| 1704 | interrupt-controller; | |
| 1705 | #interrupt-cells = <2>; | |
| 1706 | reg = <0x0 0x400>; | |
| 1707 | clocks = <&rcc GPIOA>; | |
| 1708 | st,bank-name = "GPIOA"; | |
| 1709 | status = "disabled"; | |
| 1710 | }; | |
| 1711 | ||
| 1712 | gpiob: gpio@50003000 { | |
| 1713 | gpio-controller; | |
| 1714 | #gpio-cells = <2>; | |
| 1715 | interrupt-controller; | |
| 1716 | #interrupt-cells = <2>; | |
| 1717 | reg = <0x1000 0x400>; | |
| 1718 | clocks = <&rcc GPIOB>; | |
| 1719 | st,bank-name = "GPIOB"; | |
| 1720 | status = "disabled"; | |
| 1721 | }; | |
| 1722 | ||
| 1723 | gpioc: gpio@50004000 { | |
| 1724 | gpio-controller; | |
| 1725 | #gpio-cells = <2>; | |
| 1726 | interrupt-controller; | |
| 1727 | #interrupt-cells = <2>; | |
| 1728 | reg = <0x2000 0x400>; | |
| 1729 | clocks = <&rcc GPIOC>; | |
| 1730 | st,bank-name = "GPIOC"; | |
| 1731 | status = "disabled"; | |
| 1732 | }; | |
| 1733 | ||
| 1734 | gpiod: gpio@50005000 { | |
| 1735 | gpio-controller; | |
| 1736 | #gpio-cells = <2>; | |
| 1737 | interrupt-controller; | |
| 1738 | #interrupt-cells = <2>; | |
| 1739 | reg = <0x3000 0x400>; | |
| 1740 | clocks = <&rcc GPIOD>; | |
| 1741 | st,bank-name = "GPIOD"; | |
| 1742 | status = "disabled"; | |
| 1743 | }; | |
| 1744 | ||
| 1745 | gpioe: gpio@50006000 { | |
| 1746 | gpio-controller; | |
| 1747 | #gpio-cells = <2>; | |
| 1748 | interrupt-controller; | |
| 1749 | #interrupt-cells = <2>; | |
| 1750 | reg = <0x4000 0x400>; | |
| 1751 | clocks = <&rcc GPIOE>; | |
| 1752 | st,bank-name = "GPIOE"; | |
| 1753 | status = "disabled"; | |
| 1754 | }; | |
| 1755 | ||
| 1756 | gpiof: gpio@50007000 { | |
| 1757 | gpio-controller; | |
| 1758 | #gpio-cells = <2>; | |
| 1759 | interrupt-controller; | |
| 1760 | #interrupt-cells = <2>; | |
| 1761 | reg = <0x5000 0x400>; | |
| 1762 | clocks = <&rcc GPIOF>; | |
| 1763 | st,bank-name = "GPIOF"; | |
| 1764 | status = "disabled"; | |
| 1765 | }; | |
| 1766 | ||
| 1767 | gpiog: gpio@50008000 { | |
| 1768 | gpio-controller; | |
| 1769 | #gpio-cells = <2>; | |
| 1770 | interrupt-controller; | |
| 1771 | #interrupt-cells = <2>; | |
| 1772 | reg = <0x6000 0x400>; | |
| 1773 | clocks = <&rcc GPIOG>; | |
| 1774 | st,bank-name = "GPIOG"; | |
| 1775 | status = "disabled"; | |
| 1776 | }; | |
| 1777 | ||
| 1778 | gpioh: gpio@50009000 { | |
| 1779 | gpio-controller; | |
| 1780 | #gpio-cells = <2>; | |
| 1781 | interrupt-controller; | |
| 1782 | #interrupt-cells = <2>; | |
| 1783 | reg = <0x7000 0x400>; | |
| 1784 | clocks = <&rcc GPIOH>; | |
| 1785 | st,bank-name = "GPIOH"; | |
| 1786 | status = "disabled"; | |
| 1787 | }; | |
| 1788 | ||
| 1789 | gpioi: gpio@5000a000 { | |
| 1790 | gpio-controller; | |
| 1791 | #gpio-cells = <2>; | |
| 1792 | interrupt-controller; | |
| 1793 | #interrupt-cells = <2>; | |
| 1794 | reg = <0x8000 0x400>; | |
| 1795 | clocks = <&rcc GPIOI>; | |
| 1796 | st,bank-name = "GPIOI"; | |
| 1797 | status = "disabled"; | |
| 1798 | }; | |
| 1799 | ||
| 1800 | gpioj: gpio@5000b000 { | |
| 1801 | gpio-controller; | |
| 1802 | #gpio-cells = <2>; | |
| 1803 | interrupt-controller; | |
| 1804 | #interrupt-cells = <2>; | |
| 1805 | reg = <0x9000 0x400>; | |
| 1806 | clocks = <&rcc GPIOJ>; | |
| 1807 | st,bank-name = "GPIOJ"; | |
| 1808 | status = "disabled"; | |
| 1809 | }; | |
| 1810 | ||
| 1811 | gpiok: gpio@5000c000 { | |
| 1812 | gpio-controller; | |
| 1813 | #gpio-cells = <2>; | |
| 1814 | interrupt-controller; | |
| 1815 | #interrupt-cells = <2>; | |
| 1816 | reg = <0xa000 0x400>; | |
| 1817 | clocks = <&rcc GPIOK>; | |
| 1818 | st,bank-name = "GPIOK"; | |
| 1819 | status = "disabled"; | |
| 1820 | }; | |
| 1821 | }; | |
| 1822 | ||
| 69ef98b2 | 1823 | pinctrl_z: pinctrl@54004000 { |
| 1a4f57c8 PD |
1824 | #address-cells = <1>; |
| 1825 | #size-cells = <1>; | |
| 1826 | compatible = "st,stm32mp157-z-pinctrl"; | |
| 1827 | ranges = <0 0x54004000 0x400>; | |
| 1a4f57c8 PD |
1828 | interrupt-parent = <&exti>; |
| 1829 | st,syscfg = <&exti 0x60 0xff>; | |
| 1a4f57c8 PD |
1830 | |
| 1831 | gpioz: gpio@54004000 { | |
| 1832 | gpio-controller; | |
| 1833 | #gpio-cells = <2>; | |
| 1834 | interrupt-controller; | |
| 1835 | #interrupt-cells = <2>; | |
| 1836 | reg = <0 0x400>; | |
| 1837 | clocks = <&rcc GPIOZ>; | |
| 1838 | st,bank-name = "GPIOZ"; | |
| 1839 | st,bank-ioport = <11>; | |
| 1840 | status = "disabled"; | |
| 1841 | }; | |
| 1842 | }; | |
| a674313c | 1843 | }; |
| 5d2901a4 | 1844 | |
| 1a4f57c8 PD |
1845 | mlahb: ahb { |
| 1846 | compatible = "st,mlahb", "simple-bus"; | |
| 5d2901a4 PD |
1847 | #address-cells = <1>; |
| 1848 | #size-cells = <1>; | |
| 1a4f57c8 | 1849 | ranges; |
| 5d2901a4 PD |
1850 | dma-ranges = <0x00000000 0x38000000 0x10000>, |
| 1851 | <0x10000000 0x10000000 0x60000>, | |
| 1852 | <0x30000000 0x30000000 0x60000>; | |
| 1853 | ||
| 1854 | m4_rproc: m4@10000000 { | |
| 1855 | compatible = "st,stm32mp1-m4"; | |
| 1856 | reg = <0x10000000 0x40000>, | |
| 1857 | <0x30000000 0x40000>, | |
| 1858 | <0x38000000 0x10000>; | |
| 1859 | resets = <&rcc MCU_R>; | |
| f959118b | 1860 | reset-names = "mcu_rst"; |
| 5d2901a4 | 1861 | st,syscfg-holdboot = <&rcc 0x10C 0x1>; |
| 500327e2 | 1862 | st,syscfg-pdds = <&pwr_mcu 0x0 0x1>; |
| f050e3fe PD |
1863 | st,syscfg-rsc-tbl = <&tamp 0x144 0xFFFFFFFF>; |
| 1864 | st,syscfg-m4-state = <&tamp 0x148 0xFFFFFFFF>; | |
| 5d2901a4 PD |
1865 | status = "disabled"; |
| 1866 | }; | |
| 1867 | }; | |
| a674313c | 1868 | }; |