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Merge tag 'u-boot-imx-master-20250127' of https://gitlab.denx.de/u-boot/custodians...
[J-u-boot.git] / arch / arm / dts / stm32f7-pinctrl.dtsi
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PC		 1// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
2/*
3 * Copyright (C) STMicroelectronics 2017 - All Rights Reserved
4 * Author: Alexandre Torgue <[email protected]> for STMicroelectronics.
5 */
6
7#include <dt-bindings/pinctrl/stm32-pinfunc.h>
8#include <dt-bindings/mfd/stm32f7-rcc.h>
9
10/ {
11 soc {
9f603e2f 12 pinctrl: pinctrl@40020000 {
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PC		 13 #address-cells = <1>;
14 #size-cells = <1>;
15 ranges = <0 0x40020000 0x3000>;
16 interrupt-parent = <&exti>;
17 st,syscfg = <&syscfg 0x8>;
18 pins-are-numbered;
19
20 gpioa: gpio@40020000 {
21 gpio-controller;
22 #gpio-cells = <2>;
23 interrupt-controller;
24 #interrupt-cells = <2>;
25 reg = <0x0 0x400>;
26 clocks = <&rcc 0 STM32F7_AHB1_CLOCK(GPIOA)>;
27 st,bank-name = "GPIOA";
28 };
29
30 gpiob: gpio@40020400 {
31 gpio-controller;
32 #gpio-cells = <2>;
33 interrupt-controller;
34 #interrupt-cells = <2>;
35 reg = <0x400 0x400>;
36 clocks = <&rcc 0 STM32F7_AHB1_CLOCK(GPIOB)>;
37 st,bank-name = "GPIOB";
38 };
39
40 gpioc: gpio@40020800 {
41 gpio-controller;
42 #gpio-cells = <2>;
43 interrupt-controller;
44 #interrupt-cells = <2>;
45 reg = <0x800 0x400>;
46 clocks = <&rcc 0 STM32F7_AHB1_CLOCK(GPIOC)>;
47 st,bank-name = "GPIOC";
48 };
49
50 gpiod: gpio@40020c00 {
51 gpio-controller;
52 #gpio-cells = <2>;
53 interrupt-controller;
54 #interrupt-cells = <2>;
55 reg = <0xc00 0x400>;
56 clocks = <&rcc 0 STM32F7_AHB1_CLOCK(GPIOD)>;
57 st,bank-name = "GPIOD";
58 };
59
60 gpioe: gpio@40021000 {
61 gpio-controller;
62 #gpio-cells = <2>;
63 interrupt-controller;
64 #interrupt-cells = <2>;
65 reg = <0x1000 0x400>;
66 clocks = <&rcc 0 STM32F7_AHB1_CLOCK(GPIOE)>;
67 st,bank-name = "GPIOE";
68 };
69
70 gpiof: gpio@40021400 {
71 gpio-controller;
72 #gpio-cells = <2>;
73 interrupt-controller;
74 #interrupt-cells = <2>;
75 reg = <0x1400 0x400>;
76 clocks = <&rcc 0 STM32F7_AHB1_CLOCK(GPIOF)>;
77 st,bank-name = "GPIOF";
78 };
79
80 gpiog: gpio@40021800 {
81 gpio-controller;
82 #gpio-cells = <2>;
83 interrupt-controller;
84 #interrupt-cells = <2>;
85 reg = <0x1800 0x400>;
86 clocks = <&rcc 0 STM32F7_AHB1_CLOCK(GPIOG)>;
87 st,bank-name = "GPIOG";
88 };
89
90 gpioh: gpio@40021c00 {
91 gpio-controller;
92 #gpio-cells = <2>;
93 interrupt-controller;
94 #interrupt-cells = <2>;
95 reg = <0x1c00 0x400>;
96 clocks = <&rcc 0 STM32F7_AHB1_CLOCK(GPIOH)>;
97 st,bank-name = "GPIOH";
98 };
99
100 gpioi: gpio@40022000 {
101 gpio-controller;
102 #gpio-cells = <2>;
103 interrupt-controller;
104 #interrupt-cells = <2>;
105 reg = <0x2000 0x400>;
106 clocks = <&rcc 0 STM32F7_AHB1_CLOCK(GPIOI)>;
107 st,bank-name = "GPIOI";
108 };
109
110 gpioj: gpio@40022400 {
111 gpio-controller;
112 #gpio-cells = <2>;
113 interrupt-controller;
114 #interrupt-cells = <2>;
115 reg = <0x2400 0x400>;
116 clocks = <&rcc 0 STM32F7_AHB1_CLOCK(GPIOJ)>;
117 st,bank-name = "GPIOJ";
118 };
119
120 gpiok: gpio@40022800 {
121 gpio-controller;
122 #gpio-cells = <2>;
123 interrupt-controller;
124 #interrupt-cells = <2>;
125 reg = <0x2800 0x400>;
126 clocks = <&rcc 0 STM32F7_AHB1_CLOCK(GPIOK)>;
127 st,bank-name = "GPIOK";
128 };
129
61c88ace 130 cec_pins_a: cec-0 {
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PC		 131 pins {
132 pinmux = <STM32_PINMUX('A', 15, AF4)>; /* HDMI CEC */
133 slew-rate = <0>;
134 drive-open-drain;
135 bias-disable;
136 };
137 };
138
61c88ace 139 usart1_pins_a: usart1-0 {
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PC		 140 pins1 {
141 pinmux = <STM32_PINMUX('A', 9, AF7)>; /* USART1_TX */
142 bias-disable;
143 drive-push-pull;
144 slew-rate = <0>;
145 };
146 pins2 {
147 pinmux = <STM32_PINMUX('A', 10, AF7)>; /* USART1_RX */
148 bias-disable;
149 };
150 };
151
61c88ace 152 usart1_pins_b: usart1-1 {
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PC		 153 pins1 {
154 pinmux = <STM32_PINMUX('A', 9, AF7)>; /* USART1_TX */
155 bias-disable;
156 drive-push-pull;
157 slew-rate = <0>;
158 };
159 pins2 {
160 pinmux = <STM32_PINMUX('B', 7, AF7)>; /* USART1_RX */
161 bias-disable;
162 };
163 };
164
61c88ace 165 i2c1_pins_b: i2c1-0 {
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PC		 166 pins {
167 pinmux = <STM32_PINMUX('B', 9, AF4)>, /* I2C1 SDA */
168 <STM32_PINMUX('B', 8, AF4)>; /* I2C1 SCL */
169 bias-disable;
170 drive-open-drain;
171 slew-rate = <0>;
172 };
173 };
174
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DB		 175 i2c3_pins_a: i2c3-0 {
176 pins {
177 pinmux = <STM32_PINMUX('H', 8, AF4)>, /* I2C3_SDA */
178 <STM32_PINMUX('H', 7, AF4)>; /* I2C3_SCL */
179 bias-disable;
180 drive-open-drain;
181 slew-rate = <0>;
182 };
183 };
184
61c88ace 185 usbotg_hs_pins_a: usbotg-hs-0 {
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PC		 186 pins {
187 pinmux = <STM32_PINMUX('H', 4, AF10)>, /* OTG_HS_ULPI_NXT */
188 <STM32_PINMUX('I', 11, AF10)>, /* OTG_HS_ULPI_DIR */
189 <STM32_PINMUX('C', 0, AF10)>, /* OTG_HS_ULPI_STP */
190 <STM32_PINMUX('A', 5, AF10)>, /* OTG_HS_ULPI_CK */
191 <STM32_PINMUX('A', 3, AF10)>, /* OTG_HS_ULPI_D0 */
192 <STM32_PINMUX('B', 0, AF10)>, /* OTG_HS_ULPI_D1 */
193 <STM32_PINMUX('B', 1, AF10)>, /* OTG_HS_ULPI_D2 */
194 <STM32_PINMUX('B', 10, AF10)>, /* OTG_HS_ULPI_D3 */
195 <STM32_PINMUX('B', 11, AF10)>, /* OTG_HS_ULPI_D4 */
196 <STM32_PINMUX('B', 12, AF10)>, /* OTG_HS_ULPI_D5 */
197 <STM32_PINMUX('B', 13, AF10)>, /* OTG_HS_ULPI_D6 */
198 <STM32_PINMUX('B', 5, AF10)>; /* OTG_HS_ULPI_D7 */
199 bias-disable;
200 drive-push-pull;
201 slew-rate = <2>;
202 };
203 };
204
61c88ace 205 usbotg_hs_pins_b: usbotg-hs-1 {
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PC		 206 pins {
207 pinmux = <STM32_PINMUX('H', 4, AF10)>, /* OTG_HS_ULPI_NXT */
208 <STM32_PINMUX('C', 2, AF10)>, /* OTG_HS_ULPI_DIR */
209 <STM32_PINMUX('C', 0, AF10)>, /* OTG_HS_ULPI_STP */
210 <STM32_PINMUX('A', 5, AF10)>, /* OTG_HS_ULPI_CK */
211 <STM32_PINMUX('A', 3, AF10)>, /* OTG_HS_ULPI_D0 */
212 <STM32_PINMUX('B', 0, AF10)>, /* OTG_HS_ULPI_D1 */
213 <STM32_PINMUX('B', 1, AF10)>, /* OTG_HS_ULPI_D2 */
214 <STM32_PINMUX('B', 10, AF10)>, /* OTG_HS_ULPI_D3 */
215 <STM32_PINMUX('B', 11, AF10)>, /* OTG_HS_ULPI_D4 */
216 <STM32_PINMUX('B', 12, AF10)>, /* OTG_HS_ULPI_D5 */
217 <STM32_PINMUX('B', 13, AF10)>, /* OTG_HS_ULPI_D6 */
218 <STM32_PINMUX('B', 5, AF10)>; /* OTG_HS_ULPI_D7 */
219 bias-disable;
220 drive-push-pull;
221 slew-rate = <2>;
222 };
223 };
224
61c88ace 225 usbotg_fs_pins_a: usbotg-fs-0 {
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PC		 226 pins {
227 pinmux = <STM32_PINMUX('A', 10, AF10)>, /* OTG_FS_ID */
228 <STM32_PINMUX('A', 11, AF10)>, /* OTG_FS_DM */
229 <STM32_PINMUX('A', 12, AF10)>; /* OTG_FS_DP */
230 bias-disable;
231 drive-push-pull;
232 slew-rate = <2>;
233 };
234 };
235
61c88ace 236 sdio_pins_a: sdio-pins-a-0 {
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PC		 237 pins {
238 pinmux = <STM32_PINMUX('C', 8, AF12)>, /* SDMMC1 D0 */
239 <STM32_PINMUX('C', 9, AF12)>, /* SDMMC1 D1 */
240 <STM32_PINMUX('C', 10, AF12)>, /* SDMMC1 D2 */
241 <STM32_PINMUX('C', 11, AF12)>, /* SDMMC1 D3 */
242 <STM32_PINMUX('C', 12, AF12)>, /* SDMMC1 CLK */
243 <STM32_PINMUX('D', 2, AF12)>; /* SDMMC1 CMD */
244 drive-push-pull;
245 slew-rate = <2>;
246 };
247 };
248
61c88ace 249 sdio_pins_od_a: sdio-pins-od-a-0 {
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PC		 250 pins1 {
251 pinmux = <STM32_PINMUX('C', 8, AF12)>, /* SDMMC1 D0 */
252 <STM32_PINMUX('C', 9, AF12)>, /* SDMMC1 D1 */
253 <STM32_PINMUX('C', 10, AF12)>, /* SDMMC1 D2 */
254 <STM32_PINMUX('C', 11, AF12)>, /* SDMMC1 D3 */
255 <STM32_PINMUX('C', 12, AF12)>; /* SDMMC1 CLK */
256 drive-push-pull;
257 slew-rate = <2>;
258 };
259
260 pins2 {
261 pinmux = <STM32_PINMUX('D', 2, AF12)>; /* SDMMC1 CMD */
262 drive-open-drain;
263 slew-rate = <2>;
264 };
265 };
266
61c88ace 267 sdio_pins_b: sdio-pins-b-0 {
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PC		 268 pins {
269 pinmux = <STM32_PINMUX('G', 9, AF11)>, /* SDMMC2 D0 */
270 <STM32_PINMUX('G', 10, AF11)>, /* SDMMC2 D1 */
271 <STM32_PINMUX('B', 3, AF10)>, /* SDMMC2 D2 */
272 <STM32_PINMUX('B', 4, AF10)>, /* SDMMC2 D3 */
273 <STM32_PINMUX('D', 6, AF11)>, /* SDMMC2 CLK */
274 <STM32_PINMUX('D', 7, AF11)>; /* SDMMC2 CMD */
275 drive-push-pull;
276 slew-rate = <2>;
277 };
278 };
279
61c88ace 280 sdio_pins_od_b: sdio-pins-od-b-0 {
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PC		 281 pins1 {
282 pinmux = <STM32_PINMUX('G', 9, AF11)>, /* SDMMC2 D0 */
283 <STM32_PINMUX('G', 10, AF11)>, /* SDMMC2 D1 */
284 <STM32_PINMUX('B', 3, AF10)>, /* SDMMC2 D2 */
285 <STM32_PINMUX('B', 4, AF10)>, /* SDMMC2 D3 */
286 <STM32_PINMUX('D', 6, AF11)>; /* SDMMC2 CLK */
287 drive-push-pull;
288 slew-rate = <2>;
289 };
290
291 pins2 {
292 pinmux = <STM32_PINMUX('D', 7, AF11)>; /* SDMMC2 CMD */
293 drive-open-drain;
294 slew-rate = <2>;
295 };
296 };
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DB		 297
298 can1_pins_a: can1-0 {
299 pins1 {
300 pinmux = <STM32_PINMUX('A', 12, AF9)>; /* CAN1_TX */
301 };
302 pins2 {
303 pinmux = <STM32_PINMUX('A', 11, AF9)>; /* CAN1_RX */
304 bias-pull-up;
305 };
306 };
307
308 can1_pins_b: can1-1 {
309 pins1 {
310 pinmux = <STM32_PINMUX('B', 9, AF9)>; /* CAN1_TX */
311 };
312 pins2 {
313 pinmux = <STM32_PINMUX('B', 8, AF9)>; /* CAN1_RX */
314 bias-pull-up;
315 };
316 };
317
318 can1_pins_c: can1-2 {
319 pins1 {
320 pinmux = <STM32_PINMUX('D', 1, AF9)>; /* CAN1_TX */
321 };
322 pins2 {
323 pinmux = <STM32_PINMUX('D', 0, AF9)>; /* CAN1_RX */
324 bias-pull-up;
325
326 };
327 };
328
329 can1_pins_d: can1-3 {
330 pins1 {
331 pinmux = <STM32_PINMUX('H', 13, AF9)>; /* CAN1_TX */
332 };
333 pins2 {
334 pinmux = <STM32_PINMUX('H', 14, AF9)>; /* CAN1_RX */
335 bias-pull-up;
336
337 };
338 };
339
340 can2_pins_a: can2-0 {
341 pins1 {
342 pinmux = <STM32_PINMUX('B', 6, AF9)>; /* CAN2_TX */
343 };
344 pins2 {
345 pinmux = <STM32_PINMUX('B', 5, AF9)>; /* CAN2_RX */
346 bias-pull-up;
347 };
348 };
349
350 can2_pins_b: can2-1 {
351 pins1 {
352 pinmux = <STM32_PINMUX('B', 13, AF9)>; /* CAN2_TX */
353 };
354 pins2 {
355 pinmux = <STM32_PINMUX('B', 12, AF9)>; /* CAN2_RX */
356 bias-pull-up;
357 };
358 };
359
360 can3_pins_a: can3-0 {
361 pins1 {
362 pinmux = <STM32_PINMUX('A', 15, AF11)>; /* CAN3_TX */
363 };
364 pins2 {
365 pinmux = <STM32_PINMUX('A', 8, AF11)>; /* CAN3_RX */
366 bias-pull-up;
367 };
368 };
369
370 can3_pins_b: can3-1 {
371 pins1 {
372 pinmux = <STM32_PINMUX('B', 4, AF11)>; /* CAN3_TX */
373 };
374 pins2 {
375 pinmux = <STM32_PINMUX('B', 3, AF11)>; /* CAN3_RX */
376 bias-pull-up;
377 };
378 };
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DB		 379
380 ltdc_pins_a: ltdc-0 {
381 pins {
382 pinmux = <STM32_PINMUX('E', 4, AF14)>, /* LCD_B0 */
383 <STM32_PINMUX('G',12, AF9)>, /* LCD_B4 */
384 <STM32_PINMUX('I', 9, AF14)>, /* LCD_VSYNC */
385 <STM32_PINMUX('I',10, AF14)>, /* LCD_HSYNC */
386 <STM32_PINMUX('I',14, AF14)>, /* LCD_CLK */
387 <STM32_PINMUX('I',15, AF14)>, /* LCD_R0 */
388 <STM32_PINMUX('J', 0, AF14)>, /* LCD_R1 */
389 <STM32_PINMUX('J', 1, AF14)>, /* LCD_R2 */
390 <STM32_PINMUX('J', 2, AF14)>, /* LCD_R3 */
391 <STM32_PINMUX('J', 3, AF14)>, /* LCD_R4 */
392 <STM32_PINMUX('J', 4, AF14)>, /* LCD_R5 */
393 <STM32_PINMUX('J', 5, AF14)>, /* LCD_R6 */
394 <STM32_PINMUX('J', 6, AF14)>, /* LCD_R7 */
395 <STM32_PINMUX('J', 7, AF14)>, /* LCD_G0 */
396 <STM32_PINMUX('J', 8, AF14)>, /* LCD_G1 */
397 <STM32_PINMUX('J', 9, AF14)>, /* LCD_G2 */
398 <STM32_PINMUX('J',10, AF14)>, /* LCD_G3 */
399 <STM32_PINMUX('J',11, AF14)>, /* LCD_G4 */
400 <STM32_PINMUX('J',13, AF14)>, /* LCD_B1 */
401 <STM32_PINMUX('J',14, AF14)>, /* LCD_B2 */
402 <STM32_PINMUX('J',15, AF14)>, /* LCD_B3 */
403 <STM32_PINMUX('K', 0, AF14)>, /* LCD_G5 */
404 <STM32_PINMUX('K', 1, AF14)>, /* LCD_G6 */
405 <STM32_PINMUX('K', 2, AF14)>, /* LCD_G7 */
406 <STM32_PINMUX('K', 4, AF14)>, /* LCD_B5 */
407 <STM32_PINMUX('K', 5, AF14)>, /* LCD_B6 */
408 <STM32_PINMUX('K', 6, AF14)>, /* LCD_B7 */
409 <STM32_PINMUX('K', 7, AF14)>; /* LCD_DE */
410 slew-rate = <2>;
411 };
412 };
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PC		 413 };
414 };
415};
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