[J-u-boot.git] / arch / arm / dts / sama5d27_wlsom1.dtsi

// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/*
 * sama5d27_wlsom1.dtsi - Device Tree file for SAMA5D27 WLSOM1
 *
 * Copyright (C) 2019 Microchip Technology Inc. and its subsidiaries
 *
 * Author: Nicolas Ferre <[email protected]>
 */
#include "sama5d2.dtsi"
#include "sama5d2-pinfunc.h"
/ {
	model = "Microchip SAMA5D27 WLSOM1";
	compatible = "microchip,sama5d27-wlsom1", "atmel,sama5d2", "atmel,sama5";

	memory {
		reg = <0x20000000 0x10000000>;
	};

	ahb {
		apb {
			qspi1: spi@f0024000 {
				pinctrl-names = "default";
				pinctrl-0 = <&pinctrl_qspi1_default>;

				qspi1_flash: spi_flash@0 {
					compatible = "jedec,spi-nor";
					reg = <0>;
					spi-max-frequency = <50000000>;
					spi-rx-bus-width = <4>;
					spi-tx-bus-width = <4>;
				};
			};

			macb0: ethernet@f8008000 {
				pinctrl-names = "default";
				pinctrl-0 = <&pinctrl_macb0_rmii &pinctrl_macb0_phy_irq>;
				phy-mode = "rmii";

				ethernet-phy@0 {
					reg = <0x0>;
				};
			};

			pioA: pinctrl@fc038000 {
				pinctrl_macb0_phy_irq: macb0_phy_irq {
					pinmux = <PIN_PB24__GPIO>;
					bias-disable;
				};

				pinctrl_macb0_rmii: macb0_rmii {
					pinmux = <PIN_PB14__GTXCK>,
						 <PIN_PB15__GTXEN>,
						 <PIN_PB16__GRXDV>,
						 <PIN_PB17__GRXER>,
						 <PIN_PB18__GRX0>,
						 <PIN_PB19__GRX1>,
						 <PIN_PB20__GTX0>,
						 <PIN_PB21__GTX1>,
						 <PIN_PB22__GMDC>,
						 <PIN_PB23__GMDIO>;
					bias-disable;
				};

				pinctrl_qspi1_default: qspi1_default {
					pinmux = <PIN_PB5__QSPI1_SCK>,
						 <PIN_PB6__QSPI1_CS>,
						 <PIN_PB7__QSPI1_IO0>,
						 <PIN_PB8__QSPI1_IO1>,
						 <PIN_PB9__QSPI1_IO2>,
						 <PIN_PB10__QSPI1_IO3>;
					bias-pull-up;
				};
			};
		};
	};
};
Commit	Line	Data
44b5c40b NF	1	// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
	2	/*
	3	* sama5d27_wlsom1.dtsi - Device Tree file for SAMA5D27 WLSOM1
	4	*
	5	* Copyright (C) 2019 Microchip Technology Inc. and its subsidiaries
	6	*
	7	* Author: Nicolas Ferre <[email protected]>
	8	*/
	9	#include "sama5d2.dtsi"
	10	#include "sama5d2-pinfunc.h"
	11	/ {
	12	model = "Microchip SAMA5D27 WLSOM1";
	13	compatible = "microchip,sama5d27-wlsom1", "atmel,sama5d2", "atmel,sama5";
	14
	15	memory {
	16	reg = <0x20000000 0x10000000>;
	17	};
	18
	19	ahb {
	20	apb {
06e0da70 EH	21	qspi1: spi@f0024000 {
	22	pinctrl-names = "default";
	23	pinctrl-0 = <&pinctrl_qspi1_default>;
	24
	25	qspi1_flash: spi_flash@0 {
	26	compatible = "jedec,spi-nor";
	27	reg = <0>;
	28	spi-max-frequency = <50000000>;
	29	spi-rx-bus-width = <4>;
	30	spi-tx-bus-width = <4>;
	31	};
	32	};
	33
44b5c40b NF	34	macb0: ethernet@f8008000 {
	35	pinctrl-names = "default";
	36	pinctrl-0 = <&pinctrl_macb0_rmii &pinctrl_macb0_phy_irq>;
	37	phy-mode = "rmii";
	38
	39	ethernet-phy@0 {
	40	reg = <0x0>;
	41	};
	42	};
	43
2df729e9 SM	44	pioA: pinctrl@fc038000 {
	45	pinctrl_macb0_phy_irq: macb0_phy_irq {
	46	pinmux = <PIN_PB24__GPIO>;
	47	bias-disable;
	48	};
44b5c40b	49
2df729e9 SM	50	pinctrl_macb0_rmii: macb0_rmii {
	51	pinmux = <PIN_PB14__GTXCK>,
	52	<PIN_PB15__GTXEN>,
	53	<PIN_PB16__GRXDV>,
	54	<PIN_PB17__GRXER>,
	55	<PIN_PB18__GRX0>,
	56	<PIN_PB19__GRX1>,
	57	<PIN_PB20__GTX0>,
	58	<PIN_PB21__GTX1>,
	59	<PIN_PB22__GMDC>,
	60	<PIN_PB23__GMDIO>;
	61	bias-disable;
	62	};
44b5c40b	63
2df729e9 SM	64	pinctrl_qspi1_default: qspi1_default {
	65	pinmux = <PIN_PB5__QSPI1_SCK>,
	66	<PIN_PB6__QSPI1_CS>,
	67	<PIN_PB7__QSPI1_IO0>,
	68	<PIN_PB8__QSPI1_IO1>,
	69	<PIN_PB9__QSPI1_IO2>,
	70	<PIN_PB10__QSPI1_IO3>;
	71	bias-pull-up;
44b5c40b NF	72	};
	73	};
	74	};
	75	};
	76	};