projects / J-u-boot.git / blame
| Commit | Line | Data |
|---|---|---|
| 376ac00d RL |
1 | // SPDX-License-Identifier: GPL-2.0 |
| 2 | /* | |
| 3 | * Copyright (C) 2018 MediaTek Inc. | |
| 4 | * | |
| 5 | * Author: Weijie Gao <[email protected]> | |
| 6 | */ | |
| 7 | ||
| 9bc0c7e8 SS |
8 | #include <dt-bindings/reset/mt7629-reset.h> |
| 9 | ||
| 10 | / { | |
| 11 | dramc: dramc@10203000 { | |
| 12 | compatible = "mediatek,mt7629-dramc"; | |
| 13 | reg = <0x10203000 0x600>, /* EMI */ | |
| 14 | <0x10213000 0x1000>, /* DDRPHY */ | |
| 15 | <0x10214000 0xd00>; /* DRAMC_AO */ | |
| 16 | clocks = <&topckgen CLK_TOP_DDRPHYCFG_SEL>, | |
| 17 | <&topckgen CLK_TOP_SYSPLL1_D8>, | |
| 18 | <&topckgen CLK_TOP_MEM_SEL>, | |
| 19 | <&topckgen CLK_TOP_DMPLL>; | |
| 20 | clock-names = "phy", "phy_mux", "mem", "mem_mux"; | |
| 21 | }; | |
| 22 | ||
| 23 | mcucfg: syscon@10200000 { | |
| 24 | compatible = "mediatek,mt7629-mcucfg", "syscon"; | |
| 25 | reg = <0x10200000 0x1000>; | |
| 26 | #clock-cells = <1>; | |
| 27 | }; | |
| 28 | ||
| 29 | timer0: timer@10004000 { | |
| 30 | compatible = "mediatek,timer"; | |
| 31 | reg = <0x10004000 0x80>; | |
| 32 | interrupts = <GIC_SPI 152 IRQ_TYPE_LEVEL_LOW>; | |
| 33 | clocks = <&topckgen CLK_TOP_CLKXTAL_D4>, | |
| 34 | <&topckgen CLK_TOP_10M_SEL>; | |
| 35 | clock-names = "mux", "src"; | |
| 36 | }; | |
| 37 | ||
| 38 | snand: snand@1100d000 { | |
| 39 | compatible = "mediatek,mt7629-snand"; | |
| 40 | reg = <0x1100d000 0x1000>, | |
| 41 | <0x1100e000 0x1000>; | |
| 42 | reg-names = "nfi", "ecc"; | |
| 43 | clocks = <&pericfg CLK_PERI_NFI_PD>, | |
| 44 | <&pericfg CLK_PERI_SNFI_PD>, | |
| 45 | <&pericfg CLK_PERI_NFIECC_PD>; | |
| 46 | clock-names = "nfi_clk", "pad_clk", "ecc_clk"; | |
| 47 | assigned-clocks = <&topckgen CLK_TOP_AXI_SEL>, | |
| 48 | <&topckgen CLK_TOP_NFI_INFRA_SEL>; | |
| 49 | assigned-clock-parents = <&topckgen CLK_TOP_SYSPLL1_D2>, | |
| 50 | <&topckgen CLK_TOP_UNIVPLL2_D8>; | |
| 51 | status = "disabled"; | |
| 52 | }; | |
| 53 | ||
| 54 | wdt-reboot { | |
| 55 | compatible = "wdt-reboot"; | |
| 56 | wdt = <&watchdog>; | |
| 57 | }; | |
| 58 | ||
| 59 | }; | |
| 60 | ||
| 098c0637 | 61 | &infracfg { |
| 8c103c33 | 62 | bootph-all; |
| 098c0637 SS |
63 | }; |
| 64 | ||
| 65 | &pericfg { | |
| 8c103c33 | 66 | bootph-all; |
| 098c0637 SS |
67 | }; |
| 68 | ||
| 69 | &timer0 { | |
| 8c103c33 | 70 | bootph-all; |
| 098c0637 SS |
71 | }; |
| 72 | ||
| 73 | &mcucfg { | |
| 8c103c33 | 74 | bootph-all; |
| 098c0637 SS |
75 | }; |
| 76 | ||
| 77 | &dramc { | |
| 8c103c33 | 78 | bootph-all; |
| 098c0637 SS |
79 | }; |
| 80 | ||
| 81 | &apmixedsys { | |
| 8c103c33 | 82 | bootph-all; |
| 098c0637 SS |
83 | }; |
| 84 | ||
| 85 | &topckgen { | |
| 8c103c33 | 86 | bootph-all; |
| 098c0637 SS |
87 | }; |
| 88 | ||
| 89 | &uart0 { | |
| 8c103c33 | 90 | bootph-all; |
| 9bc0c7e8 SS |
91 | reg-shift = <2>; |
| 92 | assigned-clocks = <&topckgen CLK_TOP_AXI_SEL>; | |
| 93 | assigned-clock-parents = <&topckgen CLK_TOP_SYSPLL1_D2>; | |
| 94 | }; | |
| 95 | ||
| 96 | &qspi { | |
| 97 | bootph-all; | |
| 98 | compatible = "mediatek,mtk-snor"; | |
| 99 | reg = <0x11014000 0x1000>; | |
| 100 | pinctrl-names = "default"; | |
| 101 | pinctrl-0 = <&qspi_pins>; | |
| 102 | status = "okay"; | |
| 103 | ||
| 104 | /delete-node/ flash@0; | |
| 105 | ||
| 106 | spi-flash@0{ | |
| 107 | bootph-all; | |
| 108 | compatible = "jedec,spi-nor"; | |
| 109 | reg = <0>; | |
| 110 | spi-tx-bus-width = <1>; | |
| 111 | spi-rx-bus-width = <1>; | |
| 112 | }; | |
| 098c0637 SS |
113 | }; |
| 114 | ||
| 9bc0c7e8 | 115 | &pio { |
| 8c103c33 | 116 | bootph-all; |
| 9bc0c7e8 SS |
117 | snfi_pins: snfi-pins { |
| 118 | mux { | |
| 119 | bootph-all; | |
| 120 | function = "flash"; | |
| 121 | groups = "snfi"; | |
| 122 | }; | |
| 123 | }; | |
| 124 | snor_pins: snor-pins { | |
| 125 | mux { | |
| 126 | bootph-all; | |
| 127 | function = "flash"; | |
| 128 | groups = "spi_nor"; | |
| 129 | }; | |
| 130 | }; | |
| 131 | }; | |
| 132 | ||
| 133 | &snand { | |
| 134 | pinctrl-names = "default"; | |
| 135 | pinctrl-0 = <&snfi_pins>; | |
| 136 | status = "okay"; | |
| 137 | quad-spi; | |
| 138 | bootph-all; | |
| 139 | }; | |
| 140 | ||
| 141 | ð { | |
| 142 | resets = <ðsys ETHSYS_FE_RST>; | |
| 143 | reset-names = "fe"; | |
| 144 | status = "okay"; | |
| 145 | mediatek,gmac-id = <0>; | |
| 146 | phy-mode = "2500base-x"; | |
| 147 | mediatek,switch = "mt7531"; | |
| 148 | reset-gpios = <&pio 28 GPIO_ACTIVE_HIGH>; | |
| 149 | assigned-clocks = <&topckgen CLK_TOP_ETH_SEL>, | |
| 150 | <&topckgen CLK_TOP_F10M_REF_SEL>, | |
| 151 | <&topckgen CLK_TOP_SGMII_REF_1_SEL>; | |
| 152 | assigned-clock-parents = <&topckgen CLK_TOP_UNIVPLL1_D2>, | |
| 153 | <&topckgen CLK_TOP_SYSPLL4_D16>, | |
| 154 | <&topckgen CLK_TOP_SGMIIPLL_D2>; | |
| 155 | fixed-link { | |
| 156 | speed = <2500>; | |
| 157 | full-duplex; | |
| 158 | }; | |
| 098c0637 | 159 | }; |