[J-u-boot.git] / arch / arm / dts / mt7622.dtsi

// SPDX-License-Identifier: GPL-2.0
/*
 * Copyright (c) 2019 MediaTek Inc.
 * Author: Sam Shih <[email protected]>
 */

#include <dt-bindings/interrupt-controller/irq.h>
#include <dt-bindings/interrupt-controller/arm-gic.h>
#include <dt-bindings/clock/mt7622-clk.h>
#include <dt-bindings/power/mt7629-power.h>
#include <dt-bindings/reset/mt7629-reset.h>
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/phy/phy.h>

/ {
	compatible = "mediatek,mt7622";
	interrupt-parent = <&sysirq>;
	#address-cells = <1>;
	#size-cells = <1>;

	cpus {
		#address-cells = <1>;
		#size-cells = <0>;

		cpu0: cpu@0 {
			device_type = "cpu";
			compatible = "arm,cortex-a53";
			reg = <0x0>;
			clock-frequency = <1300000000>;
		};

		cpu1: cpu@1 {
			device_type = "cpu";
			compatible = "arm,cortex-a53";
			reg = <0x1>;
			clock-frequency = <1300000000>;
		};
	};

	snfi: snfi@1100d000 {
		compatible = "mediatek,mtk-snfi-spi";
		reg = <0x1100d000 0x2000>;
		clocks = <&pericfg CLK_PERI_NFI_PD>,
			 <&pericfg CLK_PERI_SNFI_PD>;
		clock-names = "nfi_clk", "pad_clk";
		assigned-clocks = <&topckgen CLK_TOP_AXI_SEL>,
				  <&topckgen CLK_TOP_NFI_INFRA_SEL>;

		assigned-clock-parents = <&topckgen CLK_TOP_SYSPLL1_D2>,
					 <&topckgen CLK_TOP_UNIVPLL2_D8>;
		status = "disabled";
		#address-cells = <1>;
		#size-cells = <0>;
	};

	snor: snor@11014000 {
		compatible = "mediatek,mtk-snor";
		reg = <0x11014000 0x1000>;
		clocks = <&pericfg CLK_PERI_FLASH_PD>,
			 <&topckgen CLK_TOP_FLASH_SEL>;
		clock-names = "spi", "sf";
		status = "disabled";
		#address-cells = <1>;
		#size-cells = <0>;
	};

	timer {
		compatible = "arm,armv8-timer";
		interrupt-parent = <&gic>;
		interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(2) |
			      IRQ_TYPE_LEVEL_HIGH)>,
			     <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(2) |
			      IRQ_TYPE_LEVEL_HIGH)>,
			     <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(2) |
			      IRQ_TYPE_LEVEL_HIGH)>,
			     <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(2) |
			      IRQ_TYPE_LEVEL_HIGH)>;
		arm,cpu-registers-not-fw-configured;
	};

	timer0: timer@10004000 {
		compatible = "mediatek,timer";
		reg = <0x10004000 0x80>;
		interrupts = <GIC_SPI 152 IRQ_TYPE_LEVEL_LOW>;
		clocks = <&infracfg CLK_INFRA_APXGPT_PD>;
		clock-names = "system-clk";
	};

	infracfg: infracfg@10000000 {
		compatible = "mediatek,mt7622-infracfg",
			     "syscon";
		reg = <0x10000000 0x1000>;
		#clock-cells = <1>;
		#reset-cells = <1>;
	};

	pericfg: pericfg@10002000 {
		compatible = "mediatek,mt7622-pericfg", "syscon";
		reg = <0x10002000 0x1000>;
		#clock-cells = <1>;
	};

	scpsys: scpsys@10006000 {
		compatible = "mediatek,mt7622-scpsys",
			     "syscon";
		#power-domain-cells = <1>;
		reg = <0x10006000 0x1000>;
		interrupts = <GIC_SPI 165 IRQ_TYPE_LEVEL_LOW>,
			     <GIC_SPI 166 IRQ_TYPE_LEVEL_LOW>,
			     <GIC_SPI 167 IRQ_TYPE_LEVEL_LOW>,
			     <GIC_SPI 168 IRQ_TYPE_LEVEL_LOW>;
		infracfg = <&infracfg>;
		clocks = <&topckgen CLK_TOP_HIF_SEL>;
		clock-names = "hif_sel";
	};

	sysirq: interrupt-controller@10200620 {
		compatible = "mediatek,sysirq";
		reg = <0x10200620 0x20>;
		interrupt-controller;
		#interrupt-cells = <3>;
		interrupt-parent = <&gic>;
	};

	apmixedsys: apmixedsys@10209000 {
		compatible = "mediatek,mt7622-apmixedsys";
		reg = <0x10209000 0x1000>;
		#clock-cells = <1>;
	};

	topckgen: topckgen@10210000 {
		compatible = "mediatek,mt7622-topckgen";
		reg = <0x10210000 0x1000>;
		#clock-cells = <1>;
	};

	pinctrl: pinctrl@10211000 {
		compatible = "mediatek,mt7622-pinctrl";
		reg = <0x10211000 0x1000>;
		gpio: gpio-controller {
			gpio-controller;
			#gpio-cells = <2>;
		};
	};

	watchdog: watchdog@10212000 {
		compatible = "mediatek,wdt";
		reg = <0x10212000 0x800>;
	};

	wdt-reboot {
		compatible = "wdt-reboot";
		wdt = <&watchdog>;
	};

	gic: interrupt-controller@10300000 {
		compatible = "arm,gic-400";
		interrupt-controller;
		#interrupt-cells = <3>;
		interrupt-parent = <&gic>;
		reg = <0x10310000 0x1000>,
		      <0x10320000 0x1000>,
		      <0x10340000 0x2000>,
		      <0x10360000 0x2000>;
	};

	uart0: serial@11002000 {
		compatible = "mediatek,hsuart";
		reg = <0x11002000 0x400>;
		reg-shift = <2>;
		interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_LOW>;
		clocks = <&topckgen CLK_TOP_UART_SEL>,
			 <&pericfg CLK_PERI_UART0_PD>;
		clock-names = "baud", "bus";
		status = "disabled";
		assigned-clocks = <&topckgen CLK_TOP_AXI_SEL>;
		assigned-clock-parents = <&topckgen CLK_TOP_SYSPLL1_D2>;
		mediatek,force-highspeed;
	};

	mmc0: mmc@11230000 {
		compatible = "mediatek,mt7622-mmc";
		reg = <0x11230000 0x1000>;
		interrupts = <GIC_SPI 79 IRQ_TYPE_LEVEL_LOW>;
		clocks = <&pericfg CLK_PERI_MSDC30_0_PD>,
			 <&topckgen CLK_TOP_MSDC50_0_SEL>;
		clock-names = "source", "hclk";
		status = "disabled";
	};

	mmc1: mmc@11240000 {
		compatible = "mediatek,mt7622-mmc";
		reg = <0x11240000 0x1000>;
		interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_LOW>;
		clocks = <&pericfg CLK_PERI_MSDC30_1_PD>,
			 <&topckgen CLK_TOP_AXI_SEL>;
		clock-names = "source", "hclk";
		status = "disabled";
	};

	ssusbsys: ssusbsys@1a000000 {
		compatible = "mediatek,mt7622-ssusbsys",
			     "syscon";
		reg = <0x1a000000 0x1000>;
		#clock-cells = <1>;
		#reset-cells = <1>;
	};

	pciesys: pciesys@1a100800 {
		compatible = "mediatek,mt7622-pciesys", "syscon";
		reg = <0x1a100800 0x1000>;
		#clock-cells = <1>;
		#reset-cells = <1>;
	};

	pcie: pcie@1a140000 {
		compatible = "mediatek,mt7622-pcie";
		device_type = "pci";
		reg = <0x1a140000 0x1000>,
		      <0x1a143000 0x1000>,
		      <0x1a145000 0x1000>;
		reg-names = "subsys", "port0", "port1";
		#address-cells = <3>;
		#size-cells = <2>;
		interrupts = <GIC_SPI 228 IRQ_TYPE_LEVEL_LOW>,
			     <GIC_SPI 229 IRQ_TYPE_LEVEL_LOW>;
		clocks = <&pciesys CLK_PCIE_P0_MAC_EN>,
			 <&pciesys CLK_PCIE_P1_MAC_EN>,
			 <&pciesys CLK_PCIE_P0_AHB_EN>,
			 <&pciesys CLK_PCIE_P0_AHB_EN>,
			 <&pciesys CLK_PCIE_P0_AUX_EN>,
			 <&pciesys CLK_PCIE_P1_AUX_EN>,
			 <&pciesys CLK_PCIE_P0_AXI_EN>,
			 <&pciesys CLK_PCIE_P1_AXI_EN>,
			 <&pciesys CLK_PCIE_P0_OBFF_EN>,
			 <&pciesys CLK_PCIE_P1_OBFF_EN>,
			 <&pciesys CLK_PCIE_P0_PIPE_EN>,
			 <&pciesys CLK_PCIE_P1_PIPE_EN>;
		clock-names = "sys_ck0", "sys_ck1", "ahb_ck0", "ahb_ck1",
			      "aux_ck0", "aux_ck1", "axi_ck0", "axi_ck1",
			      "obff_ck0", "obff_ck1", "pipe_ck0", "pipe_ck1";
		power-domains = <&scpsys MT7629_POWER_DOMAIN_HIF0>;
		bus-range = <0x00 0xff>;
		ranges = <0x82000000 0 0x20000000 0x20000000 0 0x10000000>;
		status = "disabled";

		pcie0: pcie@0,0 {
			reg = <0x0000 0 0 0 0>;
			#address-cells = <3>;
			#size-cells = <2>;
			#interrupt-cells = <1>;
			ranges;
			status = "disabled";

			interrupt-map-mask = <0 0 0 7>;
			interrupt-map = <0 0 0 1 &pcie_intc0 0>,
					<0 0 0 2 &pcie_intc0 1>,
					<0 0 0 3 &pcie_intc0 2>,
					<0 0 0 4 &pcie_intc0 3>;
			pcie_intc0: interrupt-controller {
				interrupt-controller;
				#address-cells = <0>;
				#interrupt-cells = <1>;
			};
		};

		pcie1: pcie@1,0 {
			reg = <0x0800 0 0 0 0>;
			#address-cells = <3>;
			#size-cells = <2>;
			#interrupt-cells = <1>;
			ranges;
			status = "disabled";

			interrupt-map-mask = <0 0 0 7>;
			interrupt-map = <0 0 0 1 &pcie_intc1 0>,
					<0 0 0 2 &pcie_intc1 1>,
					<0 0 0 3 &pcie_intc1 2>,
					<0 0 0 4 &pcie_intc1 3>;
			pcie_intc1: interrupt-controller {
				interrupt-controller;
				#address-cells = <0>;
				#interrupt-cells = <1>;
			};
		};
	};

	sata: sata@1a200000 {
		compatible = "mediatek,mtk-ahci";
		reg = <0x1a200000 0x1100>;
		resets = <&pciesys MT7622_SATA_AXI_BUS_RST>,
			<&pciesys MT7622_SATA_PHY_SW_RST>,
			<&pciesys MT7622_SATA_PHY_REG_RST>;
		reset-names = "axi", "sw", "reg";
		mediatek,phy-mode = <&pciesys>;
		ports-implemented = <0x1>;
		phys = <&sata_port PHY_TYPE_SATA>;
		phy-names = "sata-phy";
		status = "okay";
	};

	sata_phy: sata-phy@1a243000 {
		compatible = "mediatek,generic-tphy-v1";
		reg = <0x1a243000 0x0100>;
		#address-cells = <1>;
		#size-cells = <1>;
		ranges;
		status = "okay";

		sata_port: sata-phy@1a243000 {
			reg = <0x1a243000 0x0100>;
			clocks = <&topckgen CLK_TOP_ETH_500M>;
			clock-names = "ref";
			#phy-cells = <1>;
			status = "okay";
		};
	};

	ssusb: usb@1a0c0000 {
		compatible = "mediatek,mt7622-xhci",
			     "mediatek,mtk-xhci";
		reg = <0x1a0c0000 0x01000>,
		      <0x1a0c4700 0x0100>;
		reg-names = "mac", "ippc";
		interrupts = <GIC_SPI 232 IRQ_TYPE_LEVEL_LOW>;
		power-domains = <&scpsys MT7629_POWER_DOMAIN_HIF1>;
		clocks = <&ssusbsys CLK_SSUSB_SYS_EN>,
			 <&ssusbsys CLK_SSUSB_REF_EN>,
			 <&ssusbsys CLK_SSUSB_MCU_EN>,
			 <&ssusbsys CLK_SSUSB_DMA_EN>;
		clock-names = "sys_ck", "ref_ck", "mcu_ck", "dma_ck";
		phys = <&u2port0 PHY_TYPE_USB2>,
		       <&u3port0 PHY_TYPE_USB3>,
		       <&u2port1 PHY_TYPE_USB2>;
		status = "disabled";
	};

	u3phy: usb-phy@1a0c4000 {
		compatible = "mediatek,mt7622-u3phy",
			     "mediatek,generic-tphy-v1";
		reg = <0x1a0c4000 0x700>;
		#address-cells = <1>;
		#size-cells = <1>;
		ranges;
		status = "disabled";

		u2port0: usb-phy@1a0c4800 {
			reg = <0x1a0c4800 0x0100>;
			#phy-cells = <1>;
			clocks = <&ssusbsys CLK_SSUSB_U2_PHY_EN>;
			clock-names = "ref";
		};

		u3port0: usb-phy@1a0c4900 {
			reg = <0x1a0c4900 0x0700>;
			#phy-cells = <1>;
		};

		u2port1: usb-phy@1a0c5000 {
			reg = <0x1a0c5000 0x0100>;
			#phy-cells = <1>;
			clocks = <&ssusbsys CLK_SSUSB_U2_PHY_1P_EN>;
			clock-names = "ref";
		};
	};

	ethsys: syscon@1b000000 {
		compatible = "mediatek,mt7622-ethsys", "syscon";
		reg = <0x1b000000 0x1000>;
		#clock-cells = <1>;
		#reset-cells = <1>;
	};

	eth: ethernet@1b100000 {
		compatible = "mediatek,mt7622-eth", "syscon";
		reg = <0x1b100000 0x20000>;
		clocks = <&topckgen CLK_TOP_ETH_SEL>,
			 <&ethsys CLK_ETH_ESW_EN>,
			 <&ethsys CLK_ETH_GP0_EN>,
			 <&ethsys CLK_ETH_GP1_EN>,
			 <&ethsys CLK_ETH_GP2_EN>,
			 <&sgmiisys CLK_SGMII_TX250M_EN>,
			 <&sgmiisys CLK_SGMII_RX250M_EN>,
			 <&sgmiisys CLK_SGMII_CDR_REF>,
			 <&sgmiisys CLK_SGMII_CDR_FB>,
			 <&topckgen CLK_TOP_SGMIIPLL>,
			 <&apmixedsys CLK_APMIXED_ETH2PLL>;
		clock-names = "ethif", "esw", "gp0", "gp1", "gp2",
			      "sgmii_tx250m", "sgmii_rx250m",
			      "sgmii_cdr_ref", "sgmii_cdr_fb", "sgmii_ck",
			      "eth2pll";
		power-domains = <&scpsys MT7629_POWER_DOMAIN_ETHSYS>;
		resets = <&ethsys ETHSYS_FE_RST>;
		reset-names = "fe";
		mediatek,ethsys = <&ethsys>;
		mediatek,sgmiisys = <&sgmiisys>;
		#address-cells = <1>;
		#size-cells = <0>;
		status = "disabled";
	};

	sgmiisys: sgmiisys@1b128000 {
		compatible = "mediatek,mt7622-sgmiisys", "syscon";
		reg = <0x1b128000 0x3000>;
		#clock-cells = <1>;
	};

	pwm: pwm@11006000 {
		compatible = "mediatek,mt7622-pwm";
		reg = <0x11006000 0x1000>;
		#clock-cells = <1>;
		#pwm-cells = <2>;
		interrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL_LOW>;
		clocks = <&topckgen CLK_TOP_PWM_SEL>,
			 <&pericfg CLK_PERI_PWM_PD>,
			 <&pericfg CLK_PERI_PWM1_PD>,
			 <&pericfg CLK_PERI_PWM2_PD>,
			 <&pericfg CLK_PERI_PWM3_PD>,
			 <&pericfg CLK_PERI_PWM4_PD>,
			 <&pericfg CLK_PERI_PWM5_PD>,
			 <&pericfg CLK_PERI_PWM6_PD>;
		clock-names = "top", "main", "pwm1", "pwm2", "pwm3", "pwm4",
			      "pwm5", "pwm6";
		status = "disabled";
	};

	soft_i2c: soft_i2c@0 {
		#address-cells = <1>;
		#size-cells = <0>;
		compatible = "i2c-gpio";
		gpios = <&gpio 56 GPIO_ACTIVE_HIGH>, /* SDA */
			<&gpio 55 GPIO_ACTIVE_HIGH>; /* CLK */
		i2c-gpio,delay-us = <5>;
		status = "disabled";
	};

	i2c1: i2c@11008000 {
		compatible = "mediatek,mt7622-i2c";
		reg = <0x11008000 0x90>,
		      <0x11000180 0x80>;
		interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_LOW>;
		clock-div = <16>;
		clocks = <&pericfg CLK_PERI_I2C1_PD>,
			 <&pericfg CLK_PERI_AP_DMA_PD>;
		clock-names = "main", "dma";
		#address-cells = <1>;
		#size-cells = <0>;
		status = "disabled";
	};

};
Commit	Line	Data
ac57e2b0 SS	1	// SPDX-License-Identifier: GPL-2.0
	2	/*
	3	* Copyright (c) 2019 MediaTek Inc.
	4	* Author: Sam Shih <[email protected]>
	5	*/
	6
	7	#include <dt-bindings/interrupt-controller/irq.h>
	8	#include <dt-bindings/interrupt-controller/arm-gic.h>
	9	#include <dt-bindings/clock/mt7622-clk.h>
6efa4505 M	10	#include <dt-bindings/power/mt7629-power.h>
	11	#include <dt-bindings/reset/mt7629-reset.h>
	12	#include <dt-bindings/gpio/gpio.h>
7cf8537d	13	#include <dt-bindings/phy/phy.h>
ac57e2b0 SS	14
	15	/ {
	16	compatible = "mediatek,mt7622";
	17	interrupt-parent = <&sysirq>;
	18	#address-cells = <1>;
	19	#size-cells = <1>;
	20
	21	cpus {
	22	#address-cells = <1>;
	23	#size-cells = <0>;
	24
	25	cpu0: cpu@0 {
	26	device_type = "cpu";
	27	compatible = "arm,cortex-a53";
	28	reg = <0x0>;
	29	clock-frequency = <1300000000>;
	30	};
	31
	32	cpu1: cpu@1 {
	33	device_type = "cpu";
	34	compatible = "arm,cortex-a53";
	35	reg = <0x1>;
	36	clock-frequency = <1300000000>;
	37	};
	38	};
	39
	40	snfi: snfi@1100d000 {
	41	compatible = "mediatek,mtk-snfi-spi";
	42	reg = <0x1100d000 0x2000>;
	43	clocks = <&pericfg CLK_PERI_NFI_PD>,
	44	<&pericfg CLK_PERI_SNFI_PD>;
	45	clock-names = "nfi_clk", "pad_clk";
	46	assigned-clocks = <&topckgen CLK_TOP_AXI_SEL>,
	47	<&topckgen CLK_TOP_NFI_INFRA_SEL>;
	48
	49	assigned-clock-parents = <&topckgen CLK_TOP_SYSPLL1_D2>,
	50	<&topckgen CLK_TOP_UNIVPLL2_D8>;
	51	status = "disabled";
	52	#address-cells = <1>;
	53	#size-cells = <0>;
	54	};
	55
3f1250a9 SH	56	snor: snor@11014000 {
	57	compatible = "mediatek,mtk-snor";
	58	reg = <0x11014000 0x1000>;
	59	clocks = <&pericfg CLK_PERI_FLASH_PD>,
	60	<&topckgen CLK_TOP_FLASH_SEL>;
	61	clock-names = "spi", "sf";
	62	status = "disabled";
	63	#address-cells = <1>;
	64	#size-cells = <0>;
	65	};
	66
ac57e2b0 SS	67	timer {
	68	compatible = "arm,armv8-timer";
	69	interrupt-parent = <&gic>;
	70	interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(2) \|
	71	IRQ_TYPE_LEVEL_HIGH)>,
	72	<GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(2) \|
	73	IRQ_TYPE_LEVEL_HIGH)>,
	74	<GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(2) \|
	75	IRQ_TYPE_LEVEL_HIGH)>,
	76	<GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(2) \|
	77	IRQ_TYPE_LEVEL_HIGH)>;
	78	arm,cpu-registers-not-fw-configured;
	79	};
	80
	81	timer0: timer@10004000 {
	82	compatible = "mediatek,timer";
	83	reg = <0x10004000 0x80>;
	84	interrupts = <GIC_SPI 152 IRQ_TYPE_LEVEL_LOW>;
ac7a51c0	85	clocks = <&infracfg CLK_INFRA_APXGPT_PD>;
ac57e2b0 SS	86	clock-names = "system-clk";
	87	};
	88
ac57e2b0 SS	89	infracfg: infracfg@10000000 {
	90	compatible = "mediatek,mt7622-infracfg",
	91	"syscon";
	92	reg = <0x10000000 0x1000>;
	93	#clock-cells = <1>;
	94	#reset-cells = <1>;
	95	};
	96
	97	pericfg: pericfg@10002000 {
	98	compatible = "mediatek,mt7622-pericfg", "syscon";
	99	reg = <0x10002000 0x1000>;
	100	#clock-cells = <1>;
	101	};
	102
	103	scpsys: scpsys@10006000 {
	104	compatible = "mediatek,mt7622-scpsys",
	105	"syscon";
	106	#power-domain-cells = <1>;
	107	reg = <0x10006000 0x1000>;
	108	interrupts = <GIC_SPI 165 IRQ_TYPE_LEVEL_LOW>,
	109	<GIC_SPI 166 IRQ_TYPE_LEVEL_LOW>,
	110	<GIC_SPI 167 IRQ_TYPE_LEVEL_LOW>,
	111	<GIC_SPI 168 IRQ_TYPE_LEVEL_LOW>;
	112	infracfg = <&infracfg>;
	113	clocks = <&topckgen CLK_TOP_HIF_SEL>;
	114	clock-names = "hif_sel";
	115	};
	116
	117	sysirq: interrupt-controller@10200620 {
	118	compatible = "mediatek,sysirq";
	119	reg = <0x10200620 0x20>;
	120	interrupt-controller;
	121	#interrupt-cells = <3>;
	122	interrupt-parent = <&gic>;
	123	};
	124
	125	apmixedsys: apmixedsys@10209000 {
	126	compatible = "mediatek,mt7622-apmixedsys";
	127	reg = <0x10209000 0x1000>;
	128	#clock-cells = <1>;
	129	};
	130
	131	topckgen: topckgen@10210000 {
	132	compatible = "mediatek,mt7622-topckgen";
	133	reg = <0x10210000 0x1000>;
	134	#clock-cells = <1>;
	135	};
	136
	137	pinctrl: pinctrl@10211000 {
	138	compatible = "mediatek,mt7622-pinctrl";
	139	reg = <0x10211000 0x1000>;
	140	gpio: gpio-controller {
	141	gpio-controller;
	142	#gpio-cells = <2>;
	143	};
	144	};
	145
	146	watchdog: watchdog@10212000 {
	147	compatible = "mediatek,wdt";
	148	reg = <0x10212000 0x800>;
	149	};
	150
35d0fdbf FW	151	wdt-reboot {
	152	compatible = "wdt-reboot";
	153	wdt = <&watchdog>;
	154	};
	155
ac57e2b0 SS	156	gic: interrupt-controller@10300000 {
	157	compatible = "arm,gic-400";
	158	interrupt-controller;
	159	#interrupt-cells = <3>;
	160	interrupt-parent = <&gic>;
	161	reg = <0x10310000 0x1000>,
	162	<0x10320000 0x1000>,
	163	<0x10340000 0x2000>,
	164	<0x10360000 0x2000>;
	165	};
	166
	167	uart0: serial@11002000 {
	168	compatible = "mediatek,hsuart";
	169	reg = <0x11002000 0x400>;
	170	reg-shift = <2>;
	171	interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_LOW>;
	172	clocks = <&topckgen CLK_TOP_UART_SEL>,
	173	<&pericfg CLK_PERI_UART0_PD>;
	174	clock-names = "baud", "bus";
	175	status = "disabled";
	176	assigned-clocks = <&topckgen CLK_TOP_AXI_SEL>;
	177	assigned-clock-parents = <&topckgen CLK_TOP_SYSPLL1_D2>;
bc15e303	178	mediatek,force-highspeed;
ac57e2b0 SS	179	};
	180
	181	mmc0: mmc@11230000 {
	182	compatible = "mediatek,mt7622-mmc";
	183	reg = <0x11230000 0x1000>;
	184	interrupts = <GIC_SPI 79 IRQ_TYPE_LEVEL_LOW>;
	185	clocks = <&pericfg CLK_PERI_MSDC30_0_PD>,
	186	<&topckgen CLK_TOP_MSDC50_0_SEL>;
	187	clock-names = "source", "hclk";
	188	status = "disabled";
	189	};
	190
	191	mmc1: mmc@11240000 {
	192	compatible = "mediatek,mt7622-mmc";
	193	reg = <0x11240000 0x1000>;
	194	interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_LOW>;
	195	clocks = <&pericfg CLK_PERI_MSDC30_1_PD>,
	196	<&topckgen CLK_TOP_AXI_SEL>;
	197	clock-names = "source", "hclk";
	198	status = "disabled";
	199	};
6efa4505	200
a13666b2 FW	201	ssusbsys: ssusbsys@1a000000 {
	202	compatible = "mediatek,mt7622-ssusbsys",
	203	"syscon";
	204	reg = <0x1a000000 0x1000>;
	205	#clock-cells = <1>;
	206	#reset-cells = <1>;
	207	};
	208
0cc587dd CL	209	pciesys: pciesys@1a100800 {
	210	compatible = "mediatek,mt7622-pciesys", "syscon";
	211	reg = <0x1a100800 0x1000>;
	212	#clock-cells = <1>;
	213	#reset-cells = <1>;
	214	};
	215
bb9d3ad5 CL	216	pcie: pcie@1a140000 {
	217	compatible = "mediatek,mt7622-pcie";
	218	device_type = "pci";
	219	reg = <0x1a140000 0x1000>,
	220	<0x1a143000 0x1000>,
	221	<0x1a145000 0x1000>;
	222	reg-names = "subsys", "port0", "port1";
	223	#address-cells = <3>;
	224	#size-cells = <2>;
	225	interrupts = <GIC_SPI 228 IRQ_TYPE_LEVEL_LOW>,
	226	<GIC_SPI 229 IRQ_TYPE_LEVEL_LOW>;
	227	clocks = <&pciesys CLK_PCIE_P0_MAC_EN>,
	228	<&pciesys CLK_PCIE_P1_MAC_EN>,
	229	<&pciesys CLK_PCIE_P0_AHB_EN>,
	230	<&pciesys CLK_PCIE_P0_AHB_EN>,
	231	<&pciesys CLK_PCIE_P0_AUX_EN>,
	232	<&pciesys CLK_PCIE_P1_AUX_EN>,
	233	<&pciesys CLK_PCIE_P0_AXI_EN>,
	234	<&pciesys CLK_PCIE_P1_AXI_EN>,
	235	<&pciesys CLK_PCIE_P0_OBFF_EN>,
	236	<&pciesys CLK_PCIE_P1_OBFF_EN>,
	237	<&pciesys CLK_PCIE_P0_PIPE_EN>,
	238	<&pciesys CLK_PCIE_P1_PIPE_EN>;
	239	clock-names = "sys_ck0", "sys_ck1", "ahb_ck0", "ahb_ck1",
	240	"aux_ck0", "aux_ck1", "axi_ck0", "axi_ck1",
	241	"obff_ck0", "obff_ck1", "pipe_ck0", "pipe_ck1";
	242	power-domains = <&scpsys MT7629_POWER_DOMAIN_HIF0>;
	243	bus-range = <0x00 0xff>;
	244	ranges = <0x82000000 0 0x20000000 0x20000000 0 0x10000000>;
	245	status = "disabled";
	246
	247	pcie0: pcie@0,0 {
	248	reg = <0x0000 0 0 0 0>;
	249	#address-cells = <3>;
	250	#size-cells = <2>;
	251	#interrupt-cells = <1>;
	252	ranges;
	253	status = "disabled";
	254
	255	interrupt-map-mask = <0 0 0 7>;
	256	interrupt-map = <0 0 0 1 &pcie_intc0 0>,
	257	<0 0 0 2 &pcie_intc0 1>,
	258	<0 0 0 3 &pcie_intc0 2>,
	259	<0 0 0 4 &pcie_intc0 3>;
	260	pcie_intc0: interrupt-controller {
	261	interrupt-controller;
	262	#address-cells = <0>;
	263	#interrupt-cells = <1>;
	264	};
	265	};
	266
	267	pcie1: pcie@1,0 {
	268	reg = <0x0800 0 0 0 0>;
	269	#address-cells = <3>;
	270	#size-cells = <2>;
	271	#interrupt-cells = <1>;
	272	ranges;
	273	status = "disabled";
	274
	275	interrupt-map-mask = <0 0 0 7>;
	276	interrupt-map = <0 0 0 1 &pcie_intc1 0>,
	277	<0 0 0 2 &pcie_intc1 1>,
	278	<0 0 0 3 &pcie_intc1 2>,
	279	<0 0 0 4 &pcie_intc1 3>;
280	pcie_intc1: interrupt-controller {
281	interrupt-controller;
282	#address-cells = <0>;
283	#interrupt-cells = <1>;
284	};
285	};
286	};
287
7cf8537d FW	288	sata: sata@1a200000 {
	289	compatible = "mediatek,mtk-ahci";
	290	reg = <0x1a200000 0x1100>;
	291	resets = <&pciesys MT7622_SATA_AXI_BUS_RST>,
	292	<&pciesys MT7622_SATA_PHY_SW_RST>,
	293	<&pciesys MT7622_SATA_PHY_REG_RST>;
	294	reset-names = "axi", "sw", "reg";
	295	mediatek,phy-mode = <&pciesys>;
	296	ports-implemented = <0x1>;
	297	phys = <&sata_port PHY_TYPE_SATA>;
	298	phy-names = "sata-phy";
	299	status = "okay";
	300	};
	301
	302	sata_phy: sata-phy@1a243000 {
	303	compatible = "mediatek,generic-tphy-v1";
	304	reg = <0x1a243000 0x0100>;
	305	#address-cells = <1>;
	306	#size-cells = <1>;
	307	ranges;
	308	status = "okay";
	309
	310	sata_port: sata-phy@1a243000 {
	311	reg = <0x1a243000 0x0100>;
	312	clocks = <&topckgen CLK_TOP_ETH_500M>;
	313	clock-names = "ref";
	314	#phy-cells = <1>;
	315	status = "okay";
	316	};
	317	};
	318
a13666b2 FW	319	ssusb: usb@1a0c0000 {
	320	compatible = "mediatek,mt7622-xhci",
	321	"mediatek,mtk-xhci";
	322	reg = <0x1a0c0000 0x01000>,
	323	<0x1a0c4700 0x0100>;
	324	reg-names = "mac", "ippc";
	325	interrupts = <GIC_SPI 232 IRQ_TYPE_LEVEL_LOW>;
	326	power-domains = <&scpsys MT7629_POWER_DOMAIN_HIF1>;
	327	clocks = <&ssusbsys CLK_SSUSB_SYS_EN>,
	328	<&ssusbsys CLK_SSUSB_REF_EN>,
	329	<&ssusbsys CLK_SSUSB_MCU_EN>,
	330	<&ssusbsys CLK_SSUSB_DMA_EN>;
	331	clock-names = "sys_ck", "ref_ck", "mcu_ck", "dma_ck";
	332	phys = <&u2port0 PHY_TYPE_USB2>,
	333	<&u3port0 PHY_TYPE_USB3>,
	334	<&u2port1 PHY_TYPE_USB2>;
	335	status = "disabled";
	336	};
	337
	338	u3phy: usb-phy@1a0c4000 {
	339	compatible = "mediatek,mt7622-u3phy",
	340	"mediatek,generic-tphy-v1";
	341	reg = <0x1a0c4000 0x700>;
	342	#address-cells = <1>;
	343	#size-cells = <1>;
	344	ranges;
	345	status = "disabled";
	346
	347	u2port0: usb-phy@1a0c4800 {
	348	reg = <0x1a0c4800 0x0100>;
	349	#phy-cells = <1>;
	350	clocks = <&ssusbsys CLK_SSUSB_U2_PHY_EN>;
	351	clock-names = "ref";
	352	};
	353
	354	u3port0: usb-phy@1a0c4900 {
	355	reg = <0x1a0c4900 0x0700>;
	356	#phy-cells = <1>;
	357	};
	358
	359	u2port1: usb-phy@1a0c5000 {
	360	reg = <0x1a0c5000 0x0100>;
	361	#phy-cells = <1>;
	362	clocks = <&ssusbsys CLK_SSUSB_U2_PHY_1P_EN>;
	363	clock-names = "ref";
	364	};
	365	};
	366
6efa4505 M	367	ethsys: syscon@1b000000 {
	368	compatible = "mediatek,mt7622-ethsys", "syscon";
	369	reg = <0x1b000000 0x1000>;
	370	#clock-cells = <1>;
	371	#reset-cells = <1>;
	372	};
	373
	374	eth: ethernet@1b100000 {
	375	compatible = "mediatek,mt7622-eth", "syscon";
	376	reg = <0x1b100000 0x20000>;
	377	clocks = <&topckgen CLK_TOP_ETH_SEL>,
	378	<&ethsys CLK_ETH_ESW_EN>,
	379	<&ethsys CLK_ETH_GP0_EN>,
	380	<&ethsys CLK_ETH_GP1_EN>,
	381	<&ethsys CLK_ETH_GP2_EN>,
	382	<&sgmiisys CLK_SGMII_TX250M_EN>,
	383	<&sgmiisys CLK_SGMII_RX250M_EN>,
	384	<&sgmiisys CLK_SGMII_CDR_REF>,
	385	<&sgmiisys CLK_SGMII_CDR_FB>,
	386	<&topckgen CLK_TOP_SGMIIPLL>,
	387	<&apmixedsys CLK_APMIXED_ETH2PLL>;
	388	clock-names = "ethif", "esw", "gp0", "gp1", "gp2",
	389	"sgmii_tx250m", "sgmii_rx250m",
	390	"sgmii_cdr_ref", "sgmii_cdr_fb", "sgmii_ck",
	391	"eth2pll";
	392	power-domains = <&scpsys MT7629_POWER_DOMAIN_ETHSYS>;
	393	resets = <&ethsys ETHSYS_FE_RST>;
	394	reset-names = "fe";
	395	mediatek,ethsys = <&ethsys>;
	396	mediatek,sgmiisys = <&sgmiisys>;
	397	#address-cells = <1>;
	398	#size-cells = <0>;
	399	status = "disabled";
	400	};
	401
	402	sgmiisys: sgmiisys@1b128000 {
	403	compatible = "mediatek,mt7622-sgmiisys", "syscon";
	404	reg = <0x1b128000 0x3000>;
	405	#clock-cells = <1>;
	406	};
	407
25a1b5ef SS	408	pwm: pwm@11006000 {
	409	compatible = "mediatek,mt7622-pwm";
	410	reg = <0x11006000 0x1000>;
	411	#clock-cells = <1>;
	412	#pwm-cells = <2>;
	413	interrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL_LOW>;
	414	clocks = <&topckgen CLK_TOP_PWM_SEL>,
	415	<&pericfg CLK_PERI_PWM_PD>,
	416	<&pericfg CLK_PERI_PWM1_PD>,
	417	<&pericfg CLK_PERI_PWM2_PD>,
	418	<&pericfg CLK_PERI_PWM3_PD>,
	419	<&pericfg CLK_PERI_PWM4_PD>,
	420	<&pericfg CLK_PERI_PWM5_PD>,
	421	<&pericfg CLK_PERI_PWM6_PD>;
	422	clock-names = "top", "main", "pwm1", "pwm2", "pwm3", "pwm4",
	423	"pwm5", "pwm6";
	424	status = "disabled";
	425	};
	426
663e6262 WG	427	soft_i2c: soft_i2c@0 {
	428	#address-cells = <1>;
	429	#size-cells = <0>;
	430	compatible = "i2c-gpio";
	431	gpios = <&gpio 56 GPIO_ACTIVE_HIGH>, /* SDA */
	432	<&gpio 55 GPIO_ACTIVE_HIGH>; /* CLK */
	433	i2c-gpio,delay-us = <5>;
	434	status = "disabled";
	435	};
	436
	437	i2c1: i2c@11008000 {
	438	compatible = "mediatek,mt7622-i2c";
	439	reg = <0x11008000 0x90>,
	440	<0x11000180 0x80>;
	441	interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_LOW>;
	442	clock-div = <16>;
	443	clocks = <&pericfg CLK_PERI_I2C1_PD>,
	444	<&pericfg CLK_PERI_AP_DMA_PD>;
	445	clock-names = "main", "dma";
	446	#address-cells = <1>;
	447	#size-cells = <0>;
	448	status = "disabled";
	449	};
	450
ac57e2b0	451	};