[J-u-boot.git] / arch / arm / dts / imx7d-sdb-qspi.dts

// SPDX-License-Identifier: GPL-2.0+
/*
 * Copyright (C) 2015 Freescale Semiconductor, Inc.
 * Copyright 2018 NXP
 */

#include "imx7d-sdb.dts"

&iomuxc {
	qspi1 {
		pinctrl_qspi1_1: qspi1grp_1 {
			fsl,pins = <
				MX7D_PAD_EPDC_DATA00__QSPI_A_DATA0 0x51
				MX7D_PAD_EPDC_DATA01__QSPI_A_DATA1 0x51
				MX7D_PAD_EPDC_DATA02__QSPI_A_DATA2 0x51
				MX7D_PAD_EPDC_DATA03__QSPI_A_DATA3 0x51
				MX7D_PAD_EPDC_DATA05__QSPI_A_SCLK 0x51
				MX7D_PAD_EPDC_DATA06__QSPI_A_SS0_B 0x51
			>;
		};
	};
};

&qspi {
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_qspi1_1>;
	status = "okay";
	ddrsmp=<0>;

	flash0: mx25l51245g@0 {
		#address-cells = <1>;
		#size-cells = <1>;
		compatible = "macronix,mx25l51245g";
		spi-max-frequency = <29000000>;
		/* take off one dummy cycle */
		spi-nor,ddr-quad-read-dummy = <5>;
		reg = <0>;
	};
};
Commit	Line	Data
3b823350 YL	1	// SPDX-License-Identifier: GPL-2.0+
	2	/*
	3	* Copyright (C) 2015 Freescale Semiconductor, Inc.
	4	* Copyright 2018 NXP
	5	*/
	6
	7	#include "imx7d-sdb.dts"
	8
3b823350 YL	9	&iomuxc {
	10	qspi1 {
	11	pinctrl_qspi1_1: qspi1grp_1 {
	12	fsl,pins = <
	13	MX7D_PAD_EPDC_DATA00__QSPI_A_DATA0 0x51
	14	MX7D_PAD_EPDC_DATA01__QSPI_A_DATA1 0x51
	15	MX7D_PAD_EPDC_DATA02__QSPI_A_DATA2 0x51
	16	MX7D_PAD_EPDC_DATA03__QSPI_A_DATA3 0x51
	17	MX7D_PAD_EPDC_DATA05__QSPI_A_SCLK 0x51
	18	MX7D_PAD_EPDC_DATA06__QSPI_A_SS0_B 0x51
	19	>;
	20	};
	21	};
	22	};
	23
868b5cb7	24	&qspi {
3b823350 YL	25	pinctrl-names = "default";
	26	pinctrl-0 = <&pinctrl_qspi1_1>;
	27	status = "okay";
	28	ddrsmp=<0>;
	29
	30	flash0: mx25l51245g@0 {
	31	#address-cells = <1>;
	32	#size-cells = <1>;
	33	compatible = "macronix,mx25l51245g";
	34	spi-max-frequency = <29000000>;
	35	/* take off one dummy cycle */
	36	spi-nor,ddr-quad-read-dummy = <5>;
	37	reg = <0>;
	38	};
	39	};