[J-u-boot.git] / arch / arm / dts / fsl-ls1043a.dtsi

// SPDX-License-Identifier: GPL-2.0+ OR X11
/*
 * Device Tree Include file for NXP Layerscape-1043A family SoC.
 *
 * Copyright 2020-2021 NXP
 * Copyright (C) 2014-2015, Freescale Semiconductor
 *
 * Mingkai Hu <[email protected]>
 */

#include "skeleton64.dtsi"
#include <dt-bindings/clock/fsl,qoriq-clockgen.h>
#include <dt-bindings/interrupt-controller/arm-gic.h>

/ {
	compatible = "fsl,ls1043a";
	interrupt-parent = <&gic>;

	sysclk: sysclk {
		compatible = "fixed-clock";
		#clock-cells = <0>;
		clock-frequency = <100000000>;
		clock-output-names = "sysclk";
	};

	gic: interrupt-controller@1400000 {
		compatible = "arm,gic-400";
		#interrupt-cells = <3>;
		interrupt-controller;
		reg = <0x0 0x1401000 0 0x1000>, /* GICD */
		      <0x0 0x1402000 0 0x2000>, /* GICC */
		      <0x0 0x1404000 0 0x2000>, /* GICH */
		      <0x0 0x1406000 0 0x2000>; /* GICV */
		interrupts = <1 9 0xf08>;
	};

	soc: soc {
		compatible = "simple-bus";
		#address-cells = <2>;
		#size-cells = <2>;
		ranges;

		sfp: efuse@1e80000 {
			compatible = "fsl,ls1021a-sfp";
			reg = <0x0 0x1e80000 0x0 0x1000>;
			clocks = <&clockgen 4 3>;
			clock-names = "sfp";
		};

		clockgen: clocking@1ee1000 {
			compatible = "fsl,ls1043a-clockgen";
			reg = <0x0 0x1ee1000 0x0 0x1000>;
			#clock-cells = <2>;
			clocks = <&sysclk>;
		};

		dspi0: dspi@2100000 {
			compatible = "fsl,vf610-dspi";
			#address-cells = <1>;
			#size-cells = <0>;
			reg = <0x0 0x2100000 0x0 0x10000>;
			interrupts = <0 64 0x4>;
			clock-names = "dspi";
			clocks = <&clockgen 4 0>;
			spi-num-chipselects = <6>;
			big-endian;
			status = "disabled";
		};

		dspi1: dspi@2110000 {
			compatible = "fsl,vf610-dspi";
			#address-cells = <1>;
			#size-cells = <0>;
			reg = <0x0 0x2110000 0x0 0x10000>;
			interrupts = <0 65 0x4>;
			clock-names = "dspi";
			clocks = <&clockgen 4 0>;
			spi-num-chipselects = <6>;
			big-endian;
			status = "disabled";
		};

		esdhc: esdhc@1560000 {
			compatible = "fsl,esdhc";
			reg = <0x0 0x1560000 0x0 0x10000>;
			interrupts = <0 62 0x4>;
			big-endian;
			bus-width = <4>;
		};

		gpio0: gpio@2300000 {
			compatible = "fsl,ls1043a-gpio", "fsl,qoriq-gpio";
			reg = <0x0 0x2300000 0x0 0x10000>;
			interrupts = <0 66 0x4>;
			gpio-controller;
			#gpio-cells = <2>;
			interrupt-controller;
			#interrupt-cells = <2>;
		};

		gpio1: gpio@2310000 {
			compatible = "fsl,ls1043a-gpio", "fsl,qoriq-gpio";
			reg = <0x0 0x2310000 0x0 0x10000>;
			interrupts = <0 67 0x4>;
			gpio-controller;
			#gpio-cells = <2>;
			interrupt-controller;
			#interrupt-cells = <2>;
		};

		gpio2: gpio@2320000 {
			compatible = "fsl,ls1043a-gpio", "fsl,qoriq-gpio";
			reg = <0x0 0x2320000 0x0 0x10000>;
			interrupts = <0 68 0x4>;
			gpio-controller;
			#gpio-cells = <2>;
			interrupt-controller;
			#interrupt-cells = <2>;
		};

		gpio3: gpio@2330000 {
			compatible = "fsl,ls1043a-gpio", "fsl,qoriq-gpio";
			reg = <0x0 0x2330000 0x0 0x10000>;
			interrupts = <0 134 0x4>;
			gpio-controller;
			#gpio-cells = <2>;
			interrupt-controller;
			#interrupt-cells = <2>;
		};

		ifc: ifc@1530000 {
			compatible = "fsl,ifc", "simple-bus";
			reg = <0x0 0x1530000 0x0 0x10000>;
			interrupts = <0 43 0x4>;
		};

		crypto: crypto@1700000 {
			compatible = "fsl,sec-v5.4", "fsl,sec-v5.0",
				     "fsl,sec-v4.0";
			fsl,sec-era = <3>;
			#address-cells = <1>;
			#size-cells = <1>;
			ranges = <0x0 0x00 0x1700000 0x100000>;
			reg = <0x00 0x1700000 0x0 0x100000>;
			interrupts = <0 75 0x4>;

			sec_jr0: jr@10000 {
				compatible = "fsl,sec-v5.4-job-ring",
					     "fsl,sec-v5.0-job-ring",
					     "fsl,sec-v4.0-job-ring";
				reg	   = <0x10000 0x10000>;
				interrupts = <0 71 0x4>;
			};

			sec_jr1: jr@20000 {
				compatible = "fsl,sec-v5.4-job-ring",
					     "fsl,sec-v5.0-job-ring",
					     "fsl,sec-v4.0-job-ring";
				reg	   = <0x20000 0x10000>;
				interrupts = <0 72 0x4>;
			};

			sec_jr2: jr@30000 {
				compatible = "fsl,sec-v5.4-job-ring",
					     "fsl,sec-v5.0-job-ring",
					     "fsl,sec-v4.0-job-ring";
				reg	   = <0x30000 0x10000>;
				interrupts = <0 73 0x4>;
			};

			sec_jr3: jr@40000 {
				compatible = "fsl,sec-v5.4-job-ring",
					     "fsl,sec-v5.0-job-ring",
					     "fsl,sec-v4.0-job-ring";
				reg	   = <0x40000 0x10000>;
				interrupts = <0 74 0x4>;
			};
		};

		i2c0: i2c@2180000 {
			compatible = "fsl,vf610-i2c";
			#address-cells = <1>;
			#size-cells = <0>;
			reg = <0x0 0x2180000 0x0 0x10000>;
			interrupts = <0 56 0x4>;
			clock-names = "i2c";
			clocks = <&clockgen 4 0>;
			status = "disabled";
		};

		i2c1: i2c@2190000 {
			compatible = "fsl,vf610-i2c";
			#address-cells = <1>;
			#size-cells = <0>;
			reg = <0x0 0x2190000 0x0 0x10000>;
			interrupts = <0 57 0x4>;
			clock-names = "i2c";
			clocks = <&clockgen 4 0>;
			status = "disabled";
		};

		i2c2: i2c@21a0000 {
			compatible = "fsl,vf610-i2c";
			#address-cells = <1>;
			#size-cells = <0>;
			reg = <0x0 0x21a0000 0x0 0x10000>;
			interrupts = <0 58 0x4>;
			clock-names = "i2c";
			clocks = <&clockgen 4 0>;
			status = "disabled";
		};

		i2c3: i2c@21b0000 {
			compatible = "fsl,vf610-i2c";
			#address-cells = <1>;
			#size-cells = <0>;
			reg = <0x0 0x21b0000 0x0 0x10000>;
			interrupts = <0 59 0x4>;
			clock-names = "i2c";
			clocks = <&clockgen 4 0>;
			status = "disabled";
		};

		duart0: serial@21c0500 {
			compatible = "fsl,ns16550", "ns16550a";
			reg = <0x00 0x21c0500 0x0 0x100>;
			interrupts = <0 54 0x4>;
			clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL
					    QORIQ_CLK_PLL_DIV(1)>;
		};

		duart1: serial@21c0600 {
			compatible = "fsl,ns16550", "ns16550a";
			reg = <0x00 0x21c0600 0x0 0x100>;
			interrupts = <0 54 0x4>;
			clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL
					    QORIQ_CLK_PLL_DIV(1)>;
		};

		duart2: serial@21d0500 {
			compatible = "fsl,ns16550", "ns16550a";
			reg = <0x0 0x21d0500 0x0 0x100>;
			interrupts = <0 55 0x4>;
			clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL
					    QORIQ_CLK_PLL_DIV(1)>;
		};

		duart3: serial@21d0600 {
			compatible = "fsl,ns16550", "ns16550a";
			reg = <0x0 0x21d0600 0x0 0x100>;
			interrupts = <0 55 0x4>;
			clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL
					    QORIQ_CLK_PLL_DIV(1)>;
		};

		lpuart0: serial@2950000 {
			compatible = "fsl,ls1021a-lpuart";
			reg = <0x0 0x2950000 0x0 0x1000>;
			interrupts = <0 48 0x4>;
			clocks = <&sysclk>;
			clock-names = "ipg";
			status = "disabled";
		};

		lpuart1: serial@2960000 {
			compatible = "fsl,ls1021a-lpuart";
			reg = <0x0 0x2960000 0x0 0x1000>;
			interrupts = <0 49 0x4>;
			clocks = <&sysclk>;
			clock-names = "ipg";
			status = "disabled";
		};

		lpuart2: serial@2970000 {
			compatible = "fsl,ls1021a-lpuart";
			reg = <0x0 0x2970000 0x0 0x1000>;
			interrupts = <0 50 0x4>;
			clock-names = "ipg";
			clocks = <&sysclk>;
			status = "disabled";
		};

		lpuart3: serial@2980000 {
			compatible = "fsl,ls1021a-lpuart";
			reg = <0x0 0x2980000 0x0 0x1000>;
			interrupts = <0 51 0x4>;
			clocks = <&sysclk>;
			clock-names = "ipg";
			status = "disabled";
		};

		lpuart4: serial@2990000 {
			compatible = "fsl,ls1021a-lpuart";
			reg = <0x0 0x2990000 0x0 0x1000>;
			interrupts = <0 52 0x4>;
			clocks = <&sysclk>;
			clock-names = "ipg";
			status = "disabled";
		};

		lpuart5: serial@29a0000 {
			compatible = "fsl,ls1021a-lpuart";
			reg = <0x0 0x29a0000 0x0 0x1000>;
			interrupts = <0 53 0x4>;
			clocks = <&sysclk>;
			clock-names = "ipg";
			status = "disabled";
		};
		qspi: quadspi@1550000 {
			compatible = "fsl,ls1021a-qspi";
			#address-cells = <1>;
			#size-cells = <0>;
			reg = <0x0 0x1550000 0x0 0x10000>,
				<0x0 0x40000000 0x0 0x1000000>;
			reg-names = "QuadSPI", "QuadSPI-memory";
			status = "disabled";
		};

		usb0: usb3@2f00000 {
			compatible = "fsl,layerscape-dwc3";
			reg = <0x0 0x2f00000 0x0 0x10000>;
			interrupts = <0 60 0x4>;
			dr_mode = "host";
		};

		usb1: usb3@3000000 {
			compatible = "fsl,layerscape-dwc3";
			reg = <0x0 0x3000000 0x0 0x10000>;
			interrupts = <0 61 0x4>;
			dr_mode = "host";
		};

		usb2: usb3@3100000 {
			compatible = "fsl,layerscape-dwc3";
			reg = <0x0 0x3100000 0x0 0x10000>;
			interrupts = <0 63 0x4>;
			dr_mode = "host";
		};

		pcie1: pcie@3400000 {
			compatible = "fsl,ls-pcie", "snps,dw-pcie";
			reg = <0x00 0x03400000 0x0 0x10000   /* dbi registers */
			       0x00 0x03410000 0x0 0x10000   /* lut registers */
			       0x40 0x00000000 0x0 0x20000>; /* configuration space */
			reg-names = "dbi", "lut", "config";
			big-endian;
			#address-cells = <3>;
			#size-cells = <2>;
			device_type = "pci";
			bus-range = <0x0 0xff>;
			ranges = <0x81000000 0x0 0x00000000 0x40 0x00020000 0x0 0x00010000   /* downstream I/O */
				  0x82000000 0x0 0x40000000 0x40 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */
		};

		pcie2: pcie@3500000 {
			compatible = "fsl,ls-pcie", "snps,dw-pcie";
			reg = <0x00 0x03500000 0x0 0x10000   /* dbi registers */
			       0x00 0x03510000 0x0 0x10000   /* lut registers */
			       0x48 0x00000000 0x0 0x20000>; /* configuration space */
			reg-names = "dbi", "lut", "config";
			big-endian;
			#address-cells = <3>;
			#size-cells = <2>;
			device_type = "pci";
			num-lanes = <2>;
			bus-range = <0x0 0xff>;
			ranges = <0x81000000 0x0 0x00000000 0x48 0x00020000 0x0 0x00010000   /* downstream I/O */
				  0x82000000 0x0 0x40000000 0x48 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */
		};

		pcie3: pcie@3600000 {
			compatible = "fsl,ls-pcie", "snps,dw-pcie";
			reg = <0x00 0x03600000 0x0 0x10000   /* dbi registers */
			       0x00 0x03610000 0x0 0x10000   /* lut registers */
			       0x50 0x00000000 0x0 0x20000>; /* configuration space */
			reg-names = "dbi", "lut", "config";
			big-endian;
			#address-cells = <3>;
			#size-cells = <2>;
			device_type = "pci";
			bus-range = <0x0 0xff>;
			ranges = <0x81000000 0x0 0x00000000 0x50 0x00020000 0x0 0x00010000   /* downstream I/O */
				  0x82000000 0x0 0x40000000 0x50 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */
		};

		sata: sata@3200000 {
			compatible = "fsl,ls1043a-ahci";
			reg = <0x0 0x3200000 0x0 0x10000 /* ccsr sata base */
			       0x0 0x20140520 0x0 0x4>;  /* ecc sata addr*/
			reg-names = "ahci", "sata-ecc";
			interrupts = <0 69 4>;
			clocks = <&clockgen 4 0>;
			status = "disabled";
		};
	};
};
Commit	Line	Data
4549e789	1	// SPDX-License-Identifier: GPL-2.0+ OR X11
e1cecb4d	2	/*
04c2d93d	3	* Device Tree Include file for NXP Layerscape-1043A family SoC.
e1cecb4d	4	*
88071ca2	5	* Copyright 2020-2021 NXP
e1cecb4d GQ	6	* Copyright (C) 2014-2015, Freescale Semiconductor
	7	*
	8	* Mingkai Hu <[email protected]>
e1cecb4d GQ	9	*/
e1cecb4d GQ	10
41651ea0 CG	11	#include "skeleton64.dtsi"
	12	#include <dt-bindings/clock/fsl,qoriq-clockgen.h>
	13	#include <dt-bindings/interrupt-controller/arm-gic.h>
e1cecb4d GQ	14
	15	/ {
	16	compatible = "fsl,ls1043a";
	17	interrupt-parent = <&gic>;
e1cecb4d GQ	18
	19	sysclk: sysclk {
	20	compatible = "fixed-clock";
	21	#clock-cells = <0>;
	22	clock-frequency = <100000000>;
	23	clock-output-names = "sysclk";
	24	};
	25
	26	gic: interrupt-controller@1400000 {
	27	compatible = "arm,gic-400";
	28	#interrupt-cells = <3>;
	29	interrupt-controller;
	30	reg = <0x0 0x1401000 0 0x1000>, /* GICD */
	31	<0x0 0x1402000 0 0x2000>, /* GICC */
	32	<0x0 0x1404000 0 0x2000>, /* GICH */
	33	<0x0 0x1406000 0 0x2000>; /* GICV */
	34	interrupts = <1 9 0xf08>;
	35	};
	36
be1d7589	37	soc: soc {
e1cecb4d GQ	38	compatible = "simple-bus";
	39	#address-cells = <2>;
	40	#size-cells = <2>;
	41	ranges;
	42
70416011 SA	43	sfp: efuse@1e80000 {
	44	compatible = "fsl,ls1021a-sfp";
	45	reg = <0x0 0x1e80000 0x0 0x1000>;
	46	clocks = <&clockgen 4 3>;
	47	clock-names = "sfp";
	48	};
	49
e1cecb4d GQ	50	clockgen: clocking@1ee1000 {
	51	compatible = "fsl,ls1043a-clockgen";
	52	reg = <0x0 0x1ee1000 0x0 0x1000>;
	53	#clock-cells = <2>;
	54	clocks = <&sysclk>;
	55	};
	56
28752cf8 GQ	57	dspi0: dspi@2100000 {
	58	compatible = "fsl,vf610-dspi";
	59	#address-cells = <1>;
	60	#size-cells = <0>;
	61	reg = <0x0 0x2100000 0x0 0x10000>;
	62	interrupts = <0 64 0x4>;
	63	clock-names = "dspi";
	64	clocks = <&clockgen 4 0>;
8c580892	65	spi-num-chipselects = <6>;
28752cf8 GQ	66	big-endian;
	67	status = "disabled";
	68	};
	69
	70	dspi1: dspi@2110000 {
	71	compatible = "fsl,vf610-dspi";
	72	#address-cells = <1>;
	73	#size-cells = <0>;
	74	reg = <0x0 0x2110000 0x0 0x10000>;
	75	interrupts = <0 65 0x4>;
	76	clock-names = "dspi";
	77	clocks = <&clockgen 4 0>;
8c580892	78	spi-num-chipselects = <6>;
28752cf8 GQ	79	big-endian;
	80	status = "disabled";
	81	};
	82
bdccf128 YZ	83	esdhc: esdhc@1560000 {
	84	compatible = "fsl,esdhc";
	85	reg = <0x0 0x1560000 0x0 0x10000>;
	86	interrupts = <0 62 0x4>;
	87	big-endian;
	88	bus-width = <4>;
	89	};
	90
b609f1ad BL	91	gpio0: gpio@2300000 {
	92	compatible = "fsl,ls1043a-gpio", "fsl,qoriq-gpio";
	93	reg = <0x0 0x2300000 0x0 0x10000>;
	94	interrupts = <0 66 0x4>;
	95	gpio-controller;
	96	#gpio-cells = <2>;
	97	interrupt-controller;
	98	#interrupt-cells = <2>;
	99	};
	100
	101	gpio1: gpio@2310000 {
	102	compatible = "fsl,ls1043a-gpio", "fsl,qoriq-gpio";
	103	reg = <0x0 0x2310000 0x0 0x10000>;
	104	interrupts = <0 67 0x4>;
	105	gpio-controller;
	106	#gpio-cells = <2>;
	107	interrupt-controller;
	108	#interrupt-cells = <2>;
	109	};
	110
	111	gpio2: gpio@2320000 {
	112	compatible = "fsl,ls1043a-gpio", "fsl,qoriq-gpio";
	113	reg = <0x0 0x2320000 0x0 0x10000>;
	114	interrupts = <0 68 0x4>;
	115	gpio-controller;
	116	#gpio-cells = <2>;
	117	interrupt-controller;
	118	#interrupt-cells = <2>;
	119	};
	120
	121	gpio3: gpio@2330000 {
	122	compatible = "fsl,ls1043a-gpio", "fsl,qoriq-gpio";
	123	reg = <0x0 0x2330000 0x0 0x10000>;
	124	interrupts = <0 134 0x4>;
	125	gpio-controller;
	126	#gpio-cells = <2>;
	127	interrupt-controller;
	128	#interrupt-cells = <2>;
	129	};
	130
e1cecb4d GQ	131	ifc: ifc@1530000 {
	132	compatible = "fsl,ifc", "simple-bus";
	133	reg = <0x0 0x1530000 0x0 0x10000>;
	134	interrupts = <0 43 0x4>;
	135	};
	136
88071ca2 GJ	137	crypto: crypto@1700000 {
	138	compatible = "fsl,sec-v5.4", "fsl,sec-v5.0",
	139	"fsl,sec-v4.0";
	140	fsl,sec-era = <3>;
	141	#address-cells = <1>;
	142	#size-cells = <1>;
	143	ranges = <0x0 0x00 0x1700000 0x100000>;
	144	reg = <0x00 0x1700000 0x0 0x100000>;
	145	interrupts = <0 75 0x4>;
	146
	147	sec_jr0: jr@10000 {
	148	compatible = "fsl,sec-v5.4-job-ring",
	149	"fsl,sec-v5.0-job-ring",
	150	"fsl,sec-v4.0-job-ring";
	151	reg = <0x10000 0x10000>;
	152	interrupts = <0 71 0x4>;
	153	};
	154
	155	sec_jr1: jr@20000 {
	156	compatible = "fsl,sec-v5.4-job-ring",
	157	"fsl,sec-v5.0-job-ring",
	158	"fsl,sec-v4.0-job-ring";
	159	reg = <0x20000 0x10000>;
	160	interrupts = <0 72 0x4>;
	161	};
	162
	163	sec_jr2: jr@30000 {
	164	compatible = "fsl,sec-v5.4-job-ring",
	165	"fsl,sec-v5.0-job-ring",
	166	"fsl,sec-v4.0-job-ring";
	167	reg = <0x30000 0x10000>;
	168	interrupts = <0 73 0x4>;
	169	};
	170
	171	sec_jr3: jr@40000 {
	172	compatible = "fsl,sec-v5.4-job-ring",
	173	"fsl,sec-v5.0-job-ring",
	174	"fsl,sec-v4.0-job-ring";
	175	reg = <0x40000 0x10000>;
	176	interrupts = <0 74 0x4>;
	177	};
	178	};
	179
e1cecb4d GQ	180	i2c0: i2c@2180000 {
	181	compatible = "fsl,vf610-i2c";
	182	#address-cells = <1>;
	183	#size-cells = <0>;
	184	reg = <0x0 0x2180000 0x0 0x10000>;
	185	interrupts = <0 56 0x4>;
	186	clock-names = "i2c";
	187	clocks = <&clockgen 4 0>;
	188	status = "disabled";
	189	};
	190
	191	i2c1: i2c@2190000 {
	192	compatible = "fsl,vf610-i2c";
	193	#address-cells = <1>;
	194	#size-cells = <0>;
	195	reg = <0x0 0x2190000 0x0 0x10000>;
	196	interrupts = <0 57 0x4>;
	197	clock-names = "i2c";
	198	clocks = <&clockgen 4 0>;
	199	status = "disabled";
	200	};
	201
	202	i2c2: i2c@21a0000 {
	203	compatible = "fsl,vf610-i2c";
	204	#address-cells = <1>;
	205	#size-cells = <0>;
	206	reg = <0x0 0x21a0000 0x0 0x10000>;
	207	interrupts = <0 58 0x4>;
	208	clock-names = "i2c";
	209	clocks = <&clockgen 4 0>;
	210	status = "disabled";
	211	};
	212
	213	i2c3: i2c@21b0000 {
	214	compatible = "fsl,vf610-i2c";
	215	#address-cells = <1>;
	216	#size-cells = <0>;
	217	reg = <0x0 0x21b0000 0x0 0x10000>;
	218	interrupts = <0 59 0x4>;
	219	clock-names = "i2c";
	220	clocks = <&clockgen 4 0>;
	221	status = "disabled";
	222	};
	223
	224	duart0: serial@21c0500 {
	225	compatible = "fsl,ns16550", "ns16550a";
	226	reg = <0x00 0x21c0500 0x0 0x100>;
	227	interrupts = <0 54 0x4>;
41651ea0 CG	228	clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL
41651ea0 CG	229	QORIQ_CLK_PLL_DIV(1)>;
e1cecb4d GQ	230	};
	231
	232	duart1: serial@21c0600 {
	233	compatible = "fsl,ns16550", "ns16550a";
	234	reg = <0x00 0x21c0600 0x0 0x100>;
	235	interrupts = <0 54 0x4>;
41651ea0 CG	236	clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL
41651ea0 CG	237	QORIQ_CLK_PLL_DIV(1)>;
e1cecb4d GQ	238	};
	239
	240	duart2: serial@21d0500 {
	241	compatible = "fsl,ns16550", "ns16550a";
	242	reg = <0x0 0x21d0500 0x0 0x100>;
	243	interrupts = <0 55 0x4>;
41651ea0 CG	244	clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL
41651ea0 CG	245	QORIQ_CLK_PLL_DIV(1)>;
e1cecb4d GQ	246	};
	247
	248	duart3: serial@21d0600 {
	249	compatible = "fsl,ns16550", "ns16550a";
	250	reg = <0x0 0x21d0600 0x0 0x100>;
	251	interrupts = <0 55 0x4>;
41651ea0 CG	252	clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL
41651ea0 CG	253	QORIQ_CLK_PLL_DIV(1)>;
e1cecb4d	254	};
2970e14f WS	255
	256	lpuart0: serial@2950000 {
	257	compatible = "fsl,ls1021a-lpuart";
	258	reg = <0x0 0x2950000 0x0 0x1000>;
	259	interrupts = <0 48 0x4>;
	260	clocks = <&sysclk>;
	261	clock-names = "ipg";
	262	status = "disabled";
	263	};
	264
	265	lpuart1: serial@2960000 {
	266	compatible = "fsl,ls1021a-lpuart";
	267	reg = <0x0 0x2960000 0x0 0x1000>;
	268	interrupts = <0 49 0x4>;
	269	clocks = <&sysclk>;
	270	clock-names = "ipg";
	271	status = "disabled";
	272	};
	273
	274	lpuart2: serial@2970000 {
	275	compatible = "fsl,ls1021a-lpuart";
	276	reg = <0x0 0x2970000 0x0 0x1000>;
	277	interrupts = <0 50 0x4>;
	278	clock-names = "ipg";
	279	clocks = <&sysclk>;
	280	status = "disabled";
	281	};
	282
	283	lpuart3: serial@2980000 {
	284	compatible = "fsl,ls1021a-lpuart";
	285	reg = <0x0 0x2980000 0x0 0x1000>;
	286	interrupts = <0 51 0x4>;
	287	clocks = <&sysclk>;
	288	clock-names = "ipg";
	289	status = "disabled";
	290	};
	291
	292	lpuart4: serial@2990000 {
	293	compatible = "fsl,ls1021a-lpuart";
	294	reg = <0x0 0x2990000 0x0 0x1000>;
	295	interrupts = <0 52 0x4>;
	296	clocks = <&sysclk>;
	297	clock-names = "ipg";
	298	status = "disabled";
	299	};
	300
	301	lpuart5: serial@29a0000 {
	302	compatible = "fsl,ls1021a-lpuart";
	303	reg = <0x0 0x29a0000 0x0 0x1000>;
	304	interrupts = <0 53 0x4>;
	305	clocks = <&sysclk>;
	306	clock-names = "ipg";
	307	status = "disabled";
	308	};
166ef1e9	309	qspi: quadspi@1550000 {
b480bcca	310	compatible = "fsl,ls1021a-qspi";
166ef1e9 GQ	311	#address-cells = <1>;
166ef1e9 GQ	312	#size-cells = <0>;
87e566d7	313	reg = <0x0 0x1550000 0x0 0x10000>,
b480bcca	314	<0x0 0x40000000 0x0 0x1000000>;
87e566d7	315	reg-names = "QuadSPI", "QuadSPI-memory";
166ef1e9 GQ	316	status = "disabled";
166ef1e9 GQ	317	};
e1e3fc14 SD	318
	319	usb0: usb3@2f00000 {
	320	compatible = "fsl,layerscape-dwc3";
	321	reg = <0x0 0x2f00000 0x0 0x10000>;
	322	interrupts = <0 60 0x4>;
	323	dr_mode = "host";
	324	};
	325
	326	usb1: usb3@3000000 {
	327	compatible = "fsl,layerscape-dwc3";
	328	reg = <0x0 0x3000000 0x0 0x10000>;
	329	interrupts = <0 61 0x4>;
	330	dr_mode = "host";
	331	};
	332
	333	usb2: usb3@3100000 {
	334	compatible = "fsl,layerscape-dwc3";
	335	reg = <0x0 0x3100000 0x0 0x10000>;
	336	interrupts = <0 63 0x4>;
	337	dr_mode = "host";
	338	};
ed9bddef	339
04c2d93d	340	pcie1: pcie@3400000 {
ed9bddef ML	341	compatible = "fsl,ls-pcie", "snps,dw-pcie";
	342	reg = <0x00 0x03400000 0x0 0x10000 /* dbi registers */
	343	0x00 0x03410000 0x0 0x10000 /* lut registers */
	344	0x40 0x00000000 0x0 0x20000>; /* configuration space */
	345	reg-names = "dbi", "lut", "config";
	346	big-endian;
	347	#address-cells = <3>;
	348	#size-cells = <2>;
	349	device_type = "pci";
	350	bus-range = <0x0 0xff>;
	351	ranges = <0x81000000 0x0 0x00000000 0x40 0x00020000 0x0 0x00010000 /* downstream I/O */
	352	0x82000000 0x0 0x40000000 0x40 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */
	353	};
	354
04c2d93d	355	pcie2: pcie@3500000 {
ed9bddef ML	356	compatible = "fsl,ls-pcie", "snps,dw-pcie";
	357	reg = <0x00 0x03500000 0x0 0x10000 /* dbi registers */
	358	0x00 0x03510000 0x0 0x10000 /* lut registers */
	359	0x48 0x00000000 0x0 0x20000>; /* configuration space */
	360	reg-names = "dbi", "lut", "config";
	361	big-endian;
	362	#address-cells = <3>;
	363	#size-cells = <2>;
	364	device_type = "pci";
	365	num-lanes = <2>;
	366	bus-range = <0x0 0xff>;
	367	ranges = <0x81000000 0x0 0x00000000 0x48 0x00020000 0x0 0x00010000 /* downstream I/O */
	368	0x82000000 0x0 0x40000000 0x48 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */
	369	};
	370
04c2d93d	371	pcie3: pcie@3600000 {
ed9bddef ML	372	compatible = "fsl,ls-pcie", "snps,dw-pcie";
	373	reg = <0x00 0x03600000 0x0 0x10000 /* dbi registers */
	374	0x00 0x03610000 0x0 0x10000 /* lut registers */
	375	0x50 0x00000000 0x0 0x20000>; /* configuration space */
	376	reg-names = "dbi", "lut", "config";
	377	big-endian;
	378	#address-cells = <3>;
	379	#size-cells = <2>;
	380	device_type = "pci";
	381	bus-range = <0x0 0xff>;
	382	ranges = <0x81000000 0x0 0x00000000 0x50 0x00020000 0x0 0x00010000 /* downstream I/O */
	383	0x82000000 0x0 0x40000000 0x50 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */
	384	};
d9211656 PM	385
	386	sata: sata@3200000 {
	387	compatible = "fsl,ls1043a-ahci";
e765ee5c PM	388	reg = <0x0 0x3200000 0x0 0x10000 /* ccsr sata base */
e765ee5c PM	389	0x0 0x20140520 0x0 0x4>; /* ecc sata addr*/
cde9b147	390	reg-names = "ahci", "sata-ecc";
d9211656 PM	391	interrupts = <0 69 4>;
	392	clocks = <&clockgen 4 0>;
	393	status = "disabled";
	394	};
e1cecb4d GQ	395	};
e1cecb4d GQ	396	};