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Commit | Line | Data |
---|---|---|
14e4b149 | 1 | /* |
2 | * This device tree is copied from | |
17c5fb19 | 3 | * https://raw.githubusercontent.com/torvalds/linux/34ea5c9d/arch/arm/boot/dts/aspeed-g5.dtsi |
14e4b149 | 4 | */ |
5 | #include "skeleton.dtsi" | |
6 | ||
7 | / { | |
8 | model = "Aspeed BMC"; | |
9 | compatible = "aspeed,ast2500"; | |
10 | #address-cells = <1>; | |
11 | #size-cells = <1>; | |
12 | interrupt-parent = <&vic>; | |
13 | ||
6bdccc30 CLG |
14 | aliases { |
15 | i2c0 = &i2c0; | |
16 | i2c1 = &i2c1; | |
17 | i2c2 = &i2c2; | |
18 | i2c3 = &i2c3; | |
19 | i2c4 = &i2c4; | |
20 | i2c5 = &i2c5; | |
21 | i2c6 = &i2c6; | |
22 | i2c7 = &i2c7; | |
23 | i2c8 = &i2c8; | |
24 | i2c9 = &i2c9; | |
25 | i2c10 = &i2c10; | |
26 | i2c11 = &i2c11; | |
27 | i2c12 = &i2c12; | |
28 | i2c13 = &i2c13; | |
29 | serial0 = &uart1; | |
30 | serial1 = &uart2; | |
31 | serial2 = &uart3; | |
32 | serial3 = &uart4; | |
33 | serial4 = &uart5; | |
34 | serial5 = &vuart; | |
35 | }; | |
36 | ||
14e4b149 | 37 | cpus { |
38 | #address-cells = <1>; | |
39 | #size-cells = <0>; | |
40 | ||
41 | cpu@0 { | |
42 | compatible = "arm,arm1176jzf-s"; | |
43 | device_type = "cpu"; | |
44 | reg = <0>; | |
45 | }; | |
46 | }; | |
47 | ||
6bdccc30 CLG |
48 | memory@80000000 { |
49 | device_type = "memory"; | |
50 | reg = <0x80000000 0>; | |
51 | }; | |
52 | ||
14e4b149 | 53 | ahb { |
54 | compatible = "simple-bus"; | |
55 | #address-cells = <1>; | |
56 | #size-cells = <1>; | |
57 | ranges; | |
58 | ||
6bdccc30 | 59 | fmc: flash-controller@1e620000 { |
d37b4f37 | 60 | reg = <0x1e620000 0xc4>, <0x20000000 0x10000000>; |
6bdccc30 CLG |
61 | #address-cells = <1>; |
62 | #size-cells = <0>; | |
63 | compatible = "aspeed,ast2500-fmc"; | |
d37b4f37 CTK |
64 | clocks = <&scu ASPEED_CLK_AHB>; |
65 | num-cs = <3>; | |
6bdccc30 | 66 | status = "disabled"; |
d37b4f37 | 67 | |
6bdccc30 CLG |
68 | flash@0 { |
69 | reg = < 0 >; | |
70 | compatible = "jedec,spi-nor"; | |
71 | status = "disabled"; | |
72 | }; | |
d37b4f37 | 73 | |
6bdccc30 CLG |
74 | flash@1 { |
75 | reg = < 1 >; | |
76 | compatible = "jedec,spi-nor"; | |
77 | status = "disabled"; | |
78 | }; | |
d37b4f37 | 79 | |
6bdccc30 CLG |
80 | flash@2 { |
81 | reg = < 2 >; | |
82 | compatible = "jedec,spi-nor"; | |
83 | status = "disabled"; | |
84 | }; | |
85 | }; | |
86 | ||
87 | spi1: flash-controller@1e630000 { | |
d37b4f37 | 88 | reg = <0x1e630000 0xc4>, <0x30000000 0x08000000>; |
6bdccc30 CLG |
89 | #address-cells = <1>; |
90 | #size-cells = <0>; | |
91 | compatible = "aspeed,ast2500-spi"; | |
d37b4f37 CTK |
92 | clocks = <&scu ASPEED_CLK_AHB>; |
93 | num-cs = <2>; | |
6bdccc30 | 94 | status = "disabled"; |
d37b4f37 | 95 | |
6bdccc30 CLG |
96 | flash@0 { |
97 | reg = < 0 >; | |
98 | compatible = "jedec,spi-nor"; | |
99 | status = "disabled"; | |
100 | }; | |
d37b4f37 | 101 | |
6bdccc30 CLG |
102 | flash@1 { |
103 | reg = < 1 >; | |
104 | compatible = "jedec,spi-nor"; | |
105 | status = "disabled"; | |
106 | }; | |
107 | }; | |
108 | ||
109 | spi2: flash-controller@1e631000 { | |
d37b4f37 | 110 | reg = <0x1e631000 0xc4>, <0x38000000 0x08000000>; |
6bdccc30 CLG |
111 | #address-cells = <1>; |
112 | #size-cells = <0>; | |
113 | compatible = "aspeed,ast2500-spi"; | |
d37b4f37 CTK |
114 | clocks = <&scu ASPEED_CLK_AHB>; |
115 | num-cs = <2>; | |
6bdccc30 | 116 | status = "disabled"; |
d37b4f37 | 117 | |
6bdccc30 CLG |
118 | flash@0 { |
119 | reg = < 0 >; | |
120 | compatible = "jedec,spi-nor"; | |
121 | status = "disabled"; | |
122 | }; | |
d37b4f37 | 123 | |
6bdccc30 CLG |
124 | flash@1 { |
125 | reg = < 1 >; | |
126 | compatible = "jedec,spi-nor"; | |
127 | status = "disabled"; | |
128 | }; | |
129 | }; | |
130 | ||
14e4b149 | 131 | vic: interrupt-controller@1e6c0080 { |
132 | compatible = "aspeed,ast2400-vic"; | |
133 | interrupt-controller; | |
134 | #interrupt-cells = <1>; | |
135 | valid-sources = <0xfefff7ff 0x0807ffff>; | |
136 | reg = <0x1e6c0080 0x80>; | |
137 | }; | |
138 | ||
17c5fb19 | 139 | mac0: ethernet@1e660000 { |
6bdccc30 | 140 | compatible = "aspeed,ast2500-mac", "faraday,ftgmac100"; |
17c5fb19 | 141 | reg = <0x1e660000 0x180>; |
142 | interrupts = <2>; | |
17c5fb19 | 143 | status = "disabled"; |
144 | }; | |
145 | ||
146 | mac1: ethernet@1e680000 { | |
6bdccc30 | 147 | compatible = "aspeed,ast2500-mac", "faraday,ftgmac100"; |
17c5fb19 | 148 | reg = <0x1e680000 0x180>; |
149 | interrupts = <3>; | |
6bdccc30 CLG |
150 | status = "disabled"; |
151 | }; | |
152 | ||
153 | ehci0: usb@1e6a1000 { | |
154 | compatible = "aspeed,ast2500-ehci", "generic-ehci"; | |
155 | reg = <0x1e6a1000 0x100>; | |
156 | interrupts = <5>; | |
157 | status = "disabled"; | |
158 | }; | |
159 | ||
160 | ehci1: usb@1e6a3000 { | |
161 | compatible = "aspeed,ast2500-ehci", "generic-ehci"; | |
162 | reg = <0x1e6a3000 0x100>; | |
163 | interrupts = <13>; | |
164 | status = "disabled"; | |
165 | }; | |
166 | ||
167 | uhci: usb@1e6b0000 { | |
168 | compatible = "aspeed,ast2500-uhci", "generic-uhci"; | |
169 | reg = <0x1e6b0000 0x100>; | |
170 | interrupts = <14>; | |
171 | #ports = <2>; | |
17c5fb19 | 172 | status = "disabled"; |
173 | }; | |
174 | ||
14e4b149 | 175 | apb { |
176 | compatible = "simple-bus"; | |
177 | #address-cells = <1>; | |
178 | #size-cells = <1>; | |
179 | ranges; | |
180 | ||
17c5fb19 | 181 | syscon: syscon@1e6e2000 { |
182 | compatible = "aspeed,g5-scu", "syscon", "simple-mfd"; | |
183 | reg = <0x1e6e2000 0x1a8>; | |
6bdccc30 CLG |
184 | #clock-cells = <1>; |
185 | #reset-cells = <1>; | |
17c5fb19 | 186 | |
187 | pinctrl: pinctrl { | |
188 | compatible = "aspeed,g5-pinctrl"; | |
189 | aspeed,external-nodes = <&gfx &lhc>; | |
190 | ||
6bdccc30 CLG |
191 | }; |
192 | }; | |
17c5fb19 | 193 | |
6bdccc30 CLG |
194 | rng: hwrng@1e6e2078 { |
195 | compatible = "timeriomem_rng"; | |
196 | reg = <0x1e6e2078 0x4>; | |
197 | period = <1>; | |
198 | quality = <100>; | |
199 | }; | |
17c5fb19 | 200 | |
6bdccc30 CLG |
201 | gfx: display@1e6e6000 { |
202 | compatible = "aspeed,ast2500-gfx", "syscon"; | |
203 | reg = <0x1e6e6000 0x1000>; | |
204 | reg-io-width = <4>; | |
205 | }; | |
17c5fb19 | 206 | |
6bdccc30 CLG |
207 | adc: adc@1e6e9000 { |
208 | compatible = "aspeed,ast2500-adc"; | |
209 | reg = <0x1e6e9000 0xb0>; | |
210 | #io-channel-cells = <1>; | |
211 | status = "disabled"; | |
212 | }; | |
17c5fb19 | 213 | |
6bdccc30 CLG |
214 | sram@1e720000 { |
215 | compatible = "mmio-sram"; | |
216 | reg = <0x1e720000 0x9000>; // 36K | |
217 | }; | |
17c5fb19 | 218 | |
0b2a749b JS |
219 | sdmmc: sd-controller@1e740000 { |
220 | compatible = "aspeed,ast2500-sd-controller"; | |
221 | reg = <0x1e740000 0x100>; | |
222 | #address-cells = <1>; | |
223 | #size-cells = <1>; | |
224 | ranges = <0 0x1e740000 0x10000>; | |
225 | clocks = <&scu ASPEED_CLK_GATE_SDCLK>; | |
226 | status = "disabled"; | |
227 | ||
228 | sdhci0: sdhci@100 { | |
229 | compatible = "aspeed,ast2500-sdhci"; | |
230 | reg = <0x100 0x100>; | |
231 | interrupts = <26>; | |
232 | sdhci,auto-cmd12; | |
233 | clocks = <&scu ASPEED_CLK_SDIO>; | |
234 | status = "disabled"; | |
235 | }; | |
236 | ||
237 | sdhci1: sdhci@200 { | |
238 | compatible = "aspeed,ast2500-sdhci"; | |
239 | reg = <0x200 0x100>; | |
240 | interrupts = <26>; | |
241 | sdhci,auto-cmd12; | |
242 | clocks = <&scu ASPEED_CLK_SDIO>; | |
243 | status = "disabled"; | |
244 | }; | |
245 | }; | |
246 | ||
6bdccc30 CLG |
247 | gpio: gpio@1e780000 { |
248 | #gpio-cells = <2>; | |
249 | gpio-controller; | |
250 | compatible = "aspeed,ast2500-gpio"; | |
251 | reg = <0x1e780000 0x1000>; | |
252 | interrupts = <20>; | |
253 | gpio-ranges = <&pinctrl 0 0 220>; | |
7da87549 | 254 | ngpios = <228>; |
6bdccc30 CLG |
255 | interrupt-controller; |
256 | }; | |
17c5fb19 | 257 | |
be298254 BT |
258 | sgpio: sgpio@1e780200 { |
259 | compatible = "aspeed,ast2500-sgpio"; | |
260 | reg = <0x1e780200 0x100>; | |
261 | interrupts = <40>; | |
262 | clocks = <&scu ASPEED_CLK_APB>; | |
263 | #gpio-cells = <2>; | |
264 | gpio-controller; | |
265 | #interrupt-cells = <2>; | |
266 | interrupt-controller; | |
267 | bus-frequency = <1000000>; | |
268 | pinctrl-names = "default"; | |
269 | pinctrl-0 = <&pinctrl_sgpm_default>; | |
270 | status = "disabled"; | |
271 | }; | |
272 | ||
6bdccc30 CLG |
273 | timer: timer@1e782000 { |
274 | /* This timer is a Faraday FTTMR010 derivative */ | |
275 | compatible = "aspeed,ast2400-timer"; | |
276 | reg = <0x1e782000 0x90>; | |
277 | }; | |
17c5fb19 | 278 | |
6bdccc30 CLG |
279 | uart1: serial@1e783000 { |
280 | compatible = "ns16550a"; | |
281 | reg = <0x1e783000 0x20>; | |
282 | reg-shift = <2>; | |
283 | interrupts = <9>; | |
284 | no-loopback-test; | |
285 | status = "disabled"; | |
286 | }; | |
17c5fb19 | 287 | |
6bdccc30 CLG |
288 | uart5: serial@1e784000 { |
289 | compatible = "ns16550a"; | |
290 | reg = <0x1e784000 0x20>; | |
291 | reg-shift = <2>; | |
292 | interrupts = <10>; | |
293 | no-loopback-test; | |
294 | status = "disabled"; | |
295 | }; | |
17c5fb19 | 296 | |
6bdccc30 CLG |
297 | wdt1: watchdog@1e785000 { |
298 | compatible = "aspeed,wdt"; | |
299 | reg = <0x1e785000 0x1c>; | |
300 | interrupts = <27>; | |
301 | }; | |
17c5fb19 | 302 | |
6bdccc30 CLG |
303 | wdt2: watchdog@1e785020 { |
304 | compatible = "aspeed,wdt"; | |
305 | reg = <0x1e785020 0x1c>; | |
306 | interrupts = <27>; | |
307 | status = "disabled"; | |
308 | }; | |
17c5fb19 | 309 | |
6bdccc30 CLG |
310 | wdt3: watchdog@1e785040 { |
311 | compatible = "aspeed,wdt"; | |
312 | reg = <0x1e785040 0x1c>; | |
313 | status = "disabled"; | |
314 | }; | |
17c5fb19 | 315 | |
6bdccc30 CLG |
316 | pwm_tacho: pwm-tacho-controller@1e786000 { |
317 | compatible = "aspeed,ast2500-pwm-tacho"; | |
318 | #address-cells = <1>; | |
319 | #size-cells = <0>; | |
320 | reg = <0x1e786000 0x1000>; | |
321 | status = "disabled"; | |
322 | }; | |
17c5fb19 | 323 | |
6bdccc30 CLG |
324 | vuart: serial@1e787000 { |
325 | compatible = "aspeed,ast2500-vuart"; | |
326 | reg = <0x1e787000 0x40>; | |
327 | reg-shift = <2>; | |
328 | interrupts = <8>; | |
329 | no-loopback-test; | |
330 | status = "disabled"; | |
331 | }; | |
17c5fb19 | 332 | |
6bdccc30 CLG |
333 | lpc: lpc@1e789000 { |
334 | compatible = "aspeed,ast2500-lpc", "simple-mfd"; | |
335 | reg = <0x1e789000 0x1000>; | |
17c5fb19 | 336 | |
6bdccc30 CLG |
337 | #address-cells = <1>; |
338 | #size-cells = <1>; | |
339 | ranges = <0x0 0x1e789000 0x1000>; | |
17c5fb19 | 340 | |
6bdccc30 CLG |
341 | lpc_bmc: lpc-bmc@0 { |
342 | compatible = "aspeed,ast2500-lpc-bmc"; | |
343 | reg = <0x0 0x80>; | |
344 | }; | |
17c5fb19 | 345 | |
6bdccc30 CLG |
346 | lpc_host: lpc-host@80 { |
347 | compatible = "aspeed,ast2500-lpc-host", "simple-mfd", "syscon"; | |
348 | reg = <0x80 0x1e0>; | |
349 | reg-io-width = <4>; | |
17c5fb19 | 350 | |
6bdccc30 CLG |
351 | #address-cells = <1>; |
352 | #size-cells = <1>; | |
353 | ranges = <0x0 0x80 0x1e0>; | |
17c5fb19 | 354 | |
6bdccc30 CLG |
355 | lpc_ctrl: lpc-ctrl@0 { |
356 | compatible = "aspeed,ast2500-lpc-ctrl"; | |
357 | reg = <0x0 0x80>; | |
358 | status = "disabled"; | |
17c5fb19 | 359 | }; |
360 | ||
6bdccc30 CLG |
361 | lpc_snoop: lpc-snoop@0 { |
362 | compatible = "aspeed,ast2500-lpc-snoop"; | |
363 | reg = <0x0 0x80>; | |
364 | interrupts = <8>; | |
365 | status = "disabled"; | |
17c5fb19 | 366 | }; |
367 | ||
6bdccc30 CLG |
368 | lhc: lhc@20 { |
369 | compatible = "aspeed,ast2500-lhc"; | |
370 | reg = <0x20 0x24 0x48 0x8>; | |
17c5fb19 | 371 | }; |
372 | ||
6bdccc30 CLG |
373 | lpc_reset: reset-controller@18 { |
374 | compatible = "aspeed,ast2500-lpc-reset"; | |
375 | reg = <0x18 0x4>; | |
376 | #reset-cells = <1>; | |
17c5fb19 | 377 | }; |
378 | ||
6bdccc30 CLG |
379 | ibt: ibt@c0 { |
380 | compatible = "aspeed,ast2500-ibt-bmc"; | |
381 | reg = <0xc0 0x18>; | |
382 | interrupts = <8>; | |
383 | status = "disabled"; | |
17c5fb19 | 384 | }; |
6bdccc30 CLG |
385 | }; |
386 | }; | |
17c5fb19 | 387 | |
6bdccc30 CLG |
388 | uart2: serial@1e78d000 { |
389 | compatible = "ns16550a"; | |
390 | reg = <0x1e78d000 0x20>; | |
391 | reg-shift = <2>; | |
392 | interrupts = <32>; | |
393 | no-loopback-test; | |
394 | status = "disabled"; | |
395 | }; | |
17c5fb19 | 396 | |
6bdccc30 CLG |
397 | uart3: serial@1e78e000 { |
398 | compatible = "ns16550a"; | |
399 | reg = <0x1e78e000 0x20>; | |
400 | reg-shift = <2>; | |
401 | interrupts = <33>; | |
402 | no-loopback-test; | |
403 | status = "disabled"; | |
404 | }; | |
17c5fb19 | 405 | |
6bdccc30 CLG |
406 | uart4: serial@1e78f000 { |
407 | compatible = "ns16550a"; | |
408 | reg = <0x1e78f000 0x20>; | |
409 | reg-shift = <2>; | |
410 | interrupts = <34>; | |
411 | no-loopback-test; | |
412 | status = "disabled"; | |
413 | }; | |
17c5fb19 | 414 | |
6bdccc30 CLG |
415 | i2c: i2c@1e78a000 { |
416 | compatible = "simple-bus"; | |
417 | #address-cells = <1>; | |
418 | #size-cells = <1>; | |
419 | ranges = <0 0x1e78a000 0x1000>; | |
420 | }; | |
421 | }; | |
422 | }; | |
423 | }; | |
17c5fb19 | 424 | |
6bdccc30 CLG |
425 | &i2c { |
426 | i2c_ic: interrupt-controller@0 { | |
427 | #interrupt-cells = <1>; | |
428 | compatible = "aspeed,ast2500-i2c-ic"; | |
429 | reg = <0x0 0x40>; | |
430 | interrupts = <12>; | |
431 | interrupt-controller; | |
432 | }; | |
17c5fb19 | 433 | |
6bdccc30 CLG |
434 | i2c0: i2c-bus@40 { |
435 | #address-cells = <1>; | |
436 | #size-cells = <0>; | |
437 | #interrupt-cells = <1>; | |
438 | ||
439 | reg = <0x40 0x40>; | |
440 | compatible = "aspeed,ast2500-i2c-bus"; | |
441 | bus-frequency = <100000>; | |
442 | interrupts = <0>; | |
443 | interrupt-parent = <&i2c_ic>; | |
444 | status = "disabled"; | |
445 | /* Does not need pinctrl properties */ | |
446 | }; | |
17c5fb19 | 447 | |
6bdccc30 CLG |
448 | i2c1: i2c-bus@80 { |
449 | #address-cells = <1>; | |
450 | #size-cells = <0>; | |
451 | #interrupt-cells = <1>; | |
452 | ||
453 | reg = <0x80 0x40>; | |
454 | compatible = "aspeed,ast2500-i2c-bus"; | |
455 | bus-frequency = <100000>; | |
456 | interrupts = <1>; | |
457 | interrupt-parent = <&i2c_ic>; | |
458 | status = "disabled"; | |
459 | /* Does not need pinctrl properties */ | |
460 | }; | |
17c5fb19 | 461 | |
6bdccc30 CLG |
462 | i2c2: i2c-bus@c0 { |
463 | #address-cells = <1>; | |
464 | #size-cells = <0>; | |
465 | #interrupt-cells = <1>; | |
466 | ||
467 | reg = <0xc0 0x40>; | |
468 | compatible = "aspeed,ast2500-i2c-bus"; | |
469 | bus-frequency = <100000>; | |
470 | interrupts = <2>; | |
471 | interrupt-parent = <&i2c_ic>; | |
472 | pinctrl-names = "default"; | |
473 | pinctrl-0 = <&pinctrl_i2c3_default>; | |
474 | status = "disabled"; | |
475 | }; | |
17c5fb19 | 476 | |
6bdccc30 CLG |
477 | i2c3: i2c-bus@100 { |
478 | #address-cells = <1>; | |
479 | #size-cells = <0>; | |
480 | #interrupt-cells = <1>; | |
481 | ||
482 | reg = <0x100 0x40>; | |
483 | compatible = "aspeed,ast2500-i2c-bus"; | |
484 | bus-frequency = <100000>; | |
485 | interrupts = <3>; | |
486 | interrupt-parent = <&i2c_ic>; | |
487 | pinctrl-names = "default"; | |
488 | pinctrl-0 = <&pinctrl_i2c4_default>; | |
489 | status = "disabled"; | |
490 | }; | |
17c5fb19 | 491 | |
6bdccc30 CLG |
492 | i2c4: i2c-bus@140 { |
493 | #address-cells = <1>; | |
494 | #size-cells = <0>; | |
495 | #interrupt-cells = <1>; | |
496 | ||
497 | reg = <0x140 0x40>; | |
498 | compatible = "aspeed,ast2500-i2c-bus"; | |
499 | bus-frequency = <100000>; | |
500 | interrupts = <4>; | |
501 | interrupt-parent = <&i2c_ic>; | |
502 | pinctrl-names = "default"; | |
503 | pinctrl-0 = <&pinctrl_i2c5_default>; | |
504 | status = "disabled"; | |
505 | }; | |
17c5fb19 | 506 | |
6bdccc30 CLG |
507 | i2c5: i2c-bus@180 { |
508 | #address-cells = <1>; | |
509 | #size-cells = <0>; | |
510 | #interrupt-cells = <1>; | |
511 | ||
512 | reg = <0x180 0x40>; | |
513 | compatible = "aspeed,ast2500-i2c-bus"; | |
514 | bus-frequency = <100000>; | |
515 | interrupts = <5>; | |
516 | interrupt-parent = <&i2c_ic>; | |
517 | pinctrl-names = "default"; | |
518 | pinctrl-0 = <&pinctrl_i2c6_default>; | |
519 | status = "disabled"; | |
520 | }; | |
17c5fb19 | 521 | |
6bdccc30 CLG |
522 | i2c6: i2c-bus@1c0 { |
523 | #address-cells = <1>; | |
524 | #size-cells = <0>; | |
525 | #interrupt-cells = <1>; | |
526 | ||
527 | reg = <0x1c0 0x40>; | |
528 | compatible = "aspeed,ast2500-i2c-bus"; | |
529 | bus-frequency = <100000>; | |
530 | interrupts = <6>; | |
531 | interrupt-parent = <&i2c_ic>; | |
532 | pinctrl-names = "default"; | |
533 | pinctrl-0 = <&pinctrl_i2c7_default>; | |
534 | status = "disabled"; | |
535 | }; | |
17c5fb19 | 536 | |
6bdccc30 CLG |
537 | i2c7: i2c-bus@300 { |
538 | #address-cells = <1>; | |
539 | #size-cells = <0>; | |
540 | #interrupt-cells = <1>; | |
541 | ||
542 | reg = <0x300 0x40>; | |
543 | compatible = "aspeed,ast2500-i2c-bus"; | |
544 | bus-frequency = <100000>; | |
545 | interrupts = <7>; | |
546 | interrupt-parent = <&i2c_ic>; | |
547 | pinctrl-names = "default"; | |
548 | pinctrl-0 = <&pinctrl_i2c8_default>; | |
549 | status = "disabled"; | |
550 | }; | |
17c5fb19 | 551 | |
6bdccc30 CLG |
552 | i2c8: i2c-bus@340 { |
553 | #address-cells = <1>; | |
554 | #size-cells = <0>; | |
555 | #interrupt-cells = <1>; | |
556 | ||
557 | reg = <0x340 0x40>; | |
558 | compatible = "aspeed,ast2500-i2c-bus"; | |
559 | bus-frequency = <100000>; | |
560 | interrupts = <8>; | |
561 | interrupt-parent = <&i2c_ic>; | |
562 | pinctrl-names = "default"; | |
563 | pinctrl-0 = <&pinctrl_i2c9_default>; | |
564 | status = "disabled"; | |
565 | }; | |
17c5fb19 | 566 | |
6bdccc30 CLG |
567 | i2c9: i2c-bus@380 { |
568 | #address-cells = <1>; | |
569 | #size-cells = <0>; | |
570 | #interrupt-cells = <1>; | |
571 | ||
572 | reg = <0x380 0x40>; | |
573 | compatible = "aspeed,ast2500-i2c-bus"; | |
574 | bus-frequency = <100000>; | |
575 | interrupts = <9>; | |
576 | interrupt-parent = <&i2c_ic>; | |
577 | pinctrl-names = "default"; | |
578 | pinctrl-0 = <&pinctrl_i2c10_default>; | |
579 | status = "disabled"; | |
580 | }; | |
17c5fb19 | 581 | |
6bdccc30 CLG |
582 | i2c10: i2c-bus@3c0 { |
583 | #address-cells = <1>; | |
584 | #size-cells = <0>; | |
585 | #interrupt-cells = <1>; | |
586 | ||
587 | reg = <0x3c0 0x40>; | |
588 | compatible = "aspeed,ast2500-i2c-bus"; | |
589 | bus-frequency = <100000>; | |
590 | interrupts = <10>; | |
591 | interrupt-parent = <&i2c_ic>; | |
592 | pinctrl-names = "default"; | |
593 | pinctrl-0 = <&pinctrl_i2c11_default>; | |
594 | status = "disabled"; | |
595 | }; | |
17c5fb19 | 596 | |
6bdccc30 CLG |
597 | i2c11: i2c-bus@400 { |
598 | #address-cells = <1>; | |
599 | #size-cells = <0>; | |
600 | #interrupt-cells = <1>; | |
601 | ||
602 | reg = <0x400 0x40>; | |
603 | compatible = "aspeed,ast2500-i2c-bus"; | |
604 | bus-frequency = <100000>; | |
605 | interrupts = <11>; | |
606 | interrupt-parent = <&i2c_ic>; | |
607 | pinctrl-names = "default"; | |
608 | pinctrl-0 = <&pinctrl_i2c12_default>; | |
609 | status = "disabled"; | |
610 | }; | |
17c5fb19 | 611 | |
6bdccc30 CLG |
612 | i2c12: i2c-bus@440 { |
613 | #address-cells = <1>; | |
614 | #size-cells = <0>; | |
615 | #interrupt-cells = <1>; | |
616 | ||
617 | reg = <0x440 0x40>; | |
618 | compatible = "aspeed,ast2500-i2c-bus"; | |
619 | bus-frequency = <100000>; | |
620 | interrupts = <12>; | |
621 | interrupt-parent = <&i2c_ic>; | |
622 | pinctrl-names = "default"; | |
623 | pinctrl-0 = <&pinctrl_i2c13_default>; | |
624 | status = "disabled"; | |
625 | }; | |
17c5fb19 | 626 | |
6bdccc30 CLG |
627 | i2c13: i2c-bus@480 { |
628 | #address-cells = <1>; | |
629 | #size-cells = <0>; | |
630 | #interrupt-cells = <1>; | |
631 | ||
632 | reg = <0x480 0x40>; | |
633 | compatible = "aspeed,ast2500-i2c-bus"; | |
634 | bus-frequency = <100000>; | |
635 | interrupts = <13>; | |
636 | interrupt-parent = <&i2c_ic>; | |
637 | pinctrl-names = "default"; | |
638 | pinctrl-0 = <&pinctrl_i2c14_default>; | |
639 | status = "disabled"; | |
640 | }; | |
641 | }; | |
17c5fb19 | 642 | |
6bdccc30 CLG |
643 | &pinctrl { |
644 | pinctrl_acpi_default: acpi_default { | |
645 | function = "ACPI"; | |
646 | groups = "ACPI"; | |
647 | }; | |
17c5fb19 | 648 | |
6bdccc30 CLG |
649 | pinctrl_adc0_default: adc0_default { |
650 | function = "ADC0"; | |
651 | groups = "ADC0"; | |
652 | }; | |
17c5fb19 | 653 | |
6bdccc30 CLG |
654 | pinctrl_adc1_default: adc1_default { |
655 | function = "ADC1"; | |
656 | groups = "ADC1"; | |
657 | }; | |
17c5fb19 | 658 | |
6bdccc30 CLG |
659 | pinctrl_adc10_default: adc10_default { |
660 | function = "ADC10"; | |
661 | groups = "ADC10"; | |
662 | }; | |
17c5fb19 | 663 | |
6bdccc30 CLG |
664 | pinctrl_adc11_default: adc11_default { |
665 | function = "ADC11"; | |
666 | groups = "ADC11"; | |
667 | }; | |
17c5fb19 | 668 | |
6bdccc30 CLG |
669 | pinctrl_adc12_default: adc12_default { |
670 | function = "ADC12"; | |
671 | groups = "ADC12"; | |
672 | }; | |
17c5fb19 | 673 | |
6bdccc30 CLG |
674 | pinctrl_adc13_default: adc13_default { |
675 | function = "ADC13"; | |
676 | groups = "ADC13"; | |
677 | }; | |
17c5fb19 | 678 | |
6bdccc30 CLG |
679 | pinctrl_adc14_default: adc14_default { |
680 | function = "ADC14"; | |
681 | groups = "ADC14"; | |
682 | }; | |
17c5fb19 | 683 | |
6bdccc30 CLG |
684 | pinctrl_adc15_default: adc15_default { |
685 | function = "ADC15"; | |
686 | groups = "ADC15"; | |
687 | }; | |
17c5fb19 | 688 | |
6bdccc30 CLG |
689 | pinctrl_adc2_default: adc2_default { |
690 | function = "ADC2"; | |
691 | groups = "ADC2"; | |
692 | }; | |
17c5fb19 | 693 | |
6bdccc30 CLG |
694 | pinctrl_adc3_default: adc3_default { |
695 | function = "ADC3"; | |
696 | groups = "ADC3"; | |
697 | }; | |
17c5fb19 | 698 | |
6bdccc30 CLG |
699 | pinctrl_adc4_default: adc4_default { |
700 | function = "ADC4"; | |
701 | groups = "ADC4"; | |
702 | }; | |
17c5fb19 | 703 | |
6bdccc30 CLG |
704 | pinctrl_adc5_default: adc5_default { |
705 | function = "ADC5"; | |
706 | groups = "ADC5"; | |
707 | }; | |
17c5fb19 | 708 | |
6bdccc30 CLG |
709 | pinctrl_adc6_default: adc6_default { |
710 | function = "ADC6"; | |
711 | groups = "ADC6"; | |
712 | }; | |
17c5fb19 | 713 | |
6bdccc30 CLG |
714 | pinctrl_adc7_default: adc7_default { |
715 | function = "ADC7"; | |
716 | groups = "ADC7"; | |
717 | }; | |
17c5fb19 | 718 | |
6bdccc30 CLG |
719 | pinctrl_adc8_default: adc8_default { |
720 | function = "ADC8"; | |
721 | groups = "ADC8"; | |
722 | }; | |
17c5fb19 | 723 | |
6bdccc30 CLG |
724 | pinctrl_adc9_default: adc9_default { |
725 | function = "ADC9"; | |
726 | groups = "ADC9"; | |
727 | }; | |
17c5fb19 | 728 | |
6bdccc30 CLG |
729 | pinctrl_bmcint_default: bmcint_default { |
730 | function = "BMCINT"; | |
731 | groups = "BMCINT"; | |
732 | }; | |
17c5fb19 | 733 | |
6bdccc30 CLG |
734 | pinctrl_ddcclk_default: ddcclk_default { |
735 | function = "DDCCLK"; | |
736 | groups = "DDCCLK"; | |
737 | }; | |
17c5fb19 | 738 | |
6bdccc30 CLG |
739 | pinctrl_ddcdat_default: ddcdat_default { |
740 | function = "DDCDAT"; | |
741 | groups = "DDCDAT"; | |
742 | }; | |
17c5fb19 | 743 | |
6bdccc30 CLG |
744 | pinctrl_espi_default: espi_default { |
745 | function = "ESPI"; | |
746 | groups = "ESPI"; | |
747 | }; | |
17c5fb19 | 748 | |
6bdccc30 CLG |
749 | pinctrl_fwspics1_default: fwspics1_default { |
750 | function = "FWSPICS1"; | |
751 | groups = "FWSPICS1"; | |
752 | }; | |
17c5fb19 | 753 | |
6bdccc30 CLG |
754 | pinctrl_fwspics2_default: fwspics2_default { |
755 | function = "FWSPICS2"; | |
756 | groups = "FWSPICS2"; | |
757 | }; | |
17c5fb19 | 758 | |
6bdccc30 CLG |
759 | pinctrl_gpid0_default: gpid0_default { |
760 | function = "GPID0"; | |
761 | groups = "GPID0"; | |
762 | }; | |
17c5fb19 | 763 | |
6bdccc30 CLG |
764 | pinctrl_gpid2_default: gpid2_default { |
765 | function = "GPID2"; | |
766 | groups = "GPID2"; | |
767 | }; | |
17c5fb19 | 768 | |
6bdccc30 CLG |
769 | pinctrl_gpid4_default: gpid4_default { |
770 | function = "GPID4"; | |
771 | groups = "GPID4"; | |
772 | }; | |
17c5fb19 | 773 | |
6bdccc30 CLG |
774 | pinctrl_gpid6_default: gpid6_default { |
775 | function = "GPID6"; | |
776 | groups = "GPID6"; | |
777 | }; | |
17c5fb19 | 778 | |
6bdccc30 CLG |
779 | pinctrl_gpie0_default: gpie0_default { |
780 | function = "GPIE0"; | |
781 | groups = "GPIE0"; | |
782 | }; | |
17c5fb19 | 783 | |
6bdccc30 CLG |
784 | pinctrl_gpie2_default: gpie2_default { |
785 | function = "GPIE2"; | |
786 | groups = "GPIE2"; | |
787 | }; | |
17c5fb19 | 788 | |
6bdccc30 CLG |
789 | pinctrl_gpie4_default: gpie4_default { |
790 | function = "GPIE4"; | |
791 | groups = "GPIE4"; | |
792 | }; | |
17c5fb19 | 793 | |
6bdccc30 CLG |
794 | pinctrl_gpie6_default: gpie6_default { |
795 | function = "GPIE6"; | |
796 | groups = "GPIE6"; | |
797 | }; | |
17c5fb19 | 798 | |
6bdccc30 CLG |
799 | pinctrl_i2c10_default: i2c10_default { |
800 | function = "I2C10"; | |
801 | groups = "I2C10"; | |
802 | }; | |
17c5fb19 | 803 | |
6bdccc30 CLG |
804 | pinctrl_i2c11_default: i2c11_default { |
805 | function = "I2C11"; | |
806 | groups = "I2C11"; | |
807 | }; | |
17c5fb19 | 808 | |
6bdccc30 CLG |
809 | pinctrl_i2c12_default: i2c12_default { |
810 | function = "I2C12"; | |
811 | groups = "I2C12"; | |
812 | }; | |
17c5fb19 | 813 | |
6bdccc30 CLG |
814 | pinctrl_i2c13_default: i2c13_default { |
815 | function = "I2C13"; | |
816 | groups = "I2C13"; | |
817 | }; | |
17c5fb19 | 818 | |
6bdccc30 CLG |
819 | pinctrl_i2c14_default: i2c14_default { |
820 | function = "I2C14"; | |
821 | groups = "I2C14"; | |
822 | }; | |
17c5fb19 | 823 | |
6bdccc30 CLG |
824 | pinctrl_i2c3_default: i2c3_default { |
825 | function = "I2C3"; | |
826 | groups = "I2C3"; | |
827 | }; | |
17c5fb19 | 828 | |
6bdccc30 CLG |
829 | pinctrl_i2c4_default: i2c4_default { |
830 | function = "I2C4"; | |
831 | groups = "I2C4"; | |
832 | }; | |
17c5fb19 | 833 | |
6bdccc30 CLG |
834 | pinctrl_i2c5_default: i2c5_default { |
835 | function = "I2C5"; | |
836 | groups = "I2C5"; | |
837 | }; | |
17c5fb19 | 838 | |
6bdccc30 CLG |
839 | pinctrl_i2c6_default: i2c6_default { |
840 | function = "I2C6"; | |
841 | groups = "I2C6"; | |
842 | }; | |
17c5fb19 | 843 | |
6bdccc30 CLG |
844 | pinctrl_i2c7_default: i2c7_default { |
845 | function = "I2C7"; | |
846 | groups = "I2C7"; | |
847 | }; | |
17c5fb19 | 848 | |
6bdccc30 CLG |
849 | pinctrl_i2c8_default: i2c8_default { |
850 | function = "I2C8"; | |
851 | groups = "I2C8"; | |
852 | }; | |
17c5fb19 | 853 | |
6bdccc30 CLG |
854 | pinctrl_i2c9_default: i2c9_default { |
855 | function = "I2C9"; | |
856 | groups = "I2C9"; | |
857 | }; | |
17c5fb19 | 858 | |
6bdccc30 CLG |
859 | pinctrl_lad0_default: lad0_default { |
860 | function = "LAD0"; | |
861 | groups = "LAD0"; | |
862 | }; | |
17c5fb19 | 863 | |
6bdccc30 CLG |
864 | pinctrl_lad1_default: lad1_default { |
865 | function = "LAD1"; | |
866 | groups = "LAD1"; | |
867 | }; | |
17c5fb19 | 868 | |
6bdccc30 CLG |
869 | pinctrl_lad2_default: lad2_default { |
870 | function = "LAD2"; | |
871 | groups = "LAD2"; | |
872 | }; | |
17c5fb19 | 873 | |
6bdccc30 CLG |
874 | pinctrl_lad3_default: lad3_default { |
875 | function = "LAD3"; | |
876 | groups = "LAD3"; | |
877 | }; | |
17c5fb19 | 878 | |
6bdccc30 CLG |
879 | pinctrl_lclk_default: lclk_default { |
880 | function = "LCLK"; | |
881 | groups = "LCLK"; | |
882 | }; | |
17c5fb19 | 883 | |
6bdccc30 CLG |
884 | pinctrl_lframe_default: lframe_default { |
885 | function = "LFRAME"; | |
886 | groups = "LFRAME"; | |
887 | }; | |
17c5fb19 | 888 | |
6bdccc30 CLG |
889 | pinctrl_lpchc_default: lpchc_default { |
890 | function = "LPCHC"; | |
891 | groups = "LPCHC"; | |
892 | }; | |
17c5fb19 | 893 | |
6bdccc30 CLG |
894 | pinctrl_lpcpd_default: lpcpd_default { |
895 | function = "LPCPD"; | |
896 | groups = "LPCPD"; | |
897 | }; | |
17c5fb19 | 898 | |
6bdccc30 CLG |
899 | pinctrl_lpcplus_default: lpcplus_default { |
900 | function = "LPCPLUS"; | |
901 | groups = "LPCPLUS"; | |
902 | }; | |
17c5fb19 | 903 | |
6bdccc30 CLG |
904 | pinctrl_lpcpme_default: lpcpme_default { |
905 | function = "LPCPME"; | |
906 | groups = "LPCPME"; | |
907 | }; | |
17c5fb19 | 908 | |
6bdccc30 CLG |
909 | pinctrl_lpcrst_default: lpcrst_default { |
910 | function = "LPCRST"; | |
911 | groups = "LPCRST"; | |
912 | }; | |
17c5fb19 | 913 | |
6bdccc30 CLG |
914 | pinctrl_lpcsmi_default: lpcsmi_default { |
915 | function = "LPCSMI"; | |
916 | groups = "LPCSMI"; | |
917 | }; | |
17c5fb19 | 918 | |
6bdccc30 CLG |
919 | pinctrl_lsirq_default: lsirq_default { |
920 | function = "LSIRQ"; | |
921 | groups = "LSIRQ"; | |
922 | }; | |
17c5fb19 | 923 | |
6bdccc30 CLG |
924 | pinctrl_mac1link_default: mac1link_default { |
925 | function = "MAC1LINK"; | |
926 | groups = "MAC1LINK"; | |
927 | }; | |
17c5fb19 | 928 | |
6bdccc30 CLG |
929 | pinctrl_mac2link_default: mac2link_default { |
930 | function = "MAC2LINK"; | |
931 | groups = "MAC2LINK"; | |
932 | }; | |
17c5fb19 | 933 | |
6bdccc30 CLG |
934 | pinctrl_mdio1_default: mdio1_default { |
935 | function = "MDIO1"; | |
936 | groups = "MDIO1"; | |
937 | }; | |
17c5fb19 | 938 | |
6bdccc30 CLG |
939 | pinctrl_mdio2_default: mdio2_default { |
940 | function = "MDIO2"; | |
941 | groups = "MDIO2"; | |
942 | }; | |
17c5fb19 | 943 | |
6bdccc30 CLG |
944 | pinctrl_ncts1_default: ncts1_default { |
945 | function = "NCTS1"; | |
946 | groups = "NCTS1"; | |
947 | }; | |
17c5fb19 | 948 | |
6bdccc30 CLG |
949 | pinctrl_ncts2_default: ncts2_default { |
950 | function = "NCTS2"; | |
951 | groups = "NCTS2"; | |
952 | }; | |
17c5fb19 | 953 | |
6bdccc30 CLG |
954 | pinctrl_ncts3_default: ncts3_default { |
955 | function = "NCTS3"; | |
956 | groups = "NCTS3"; | |
957 | }; | |
17c5fb19 | 958 | |
6bdccc30 CLG |
959 | pinctrl_ncts4_default: ncts4_default { |
960 | function = "NCTS4"; | |
961 | groups = "NCTS4"; | |
962 | }; | |
17c5fb19 | 963 | |
6bdccc30 CLG |
964 | pinctrl_ndcd1_default: ndcd1_default { |
965 | function = "NDCD1"; | |
966 | groups = "NDCD1"; | |
967 | }; | |
17c5fb19 | 968 | |
6bdccc30 CLG |
969 | pinctrl_ndcd2_default: ndcd2_default { |
970 | function = "NDCD2"; | |
971 | groups = "NDCD2"; | |
972 | }; | |
17c5fb19 | 973 | |
6bdccc30 CLG |
974 | pinctrl_ndcd3_default: ndcd3_default { |
975 | function = "NDCD3"; | |
976 | groups = "NDCD3"; | |
977 | }; | |
17c5fb19 | 978 | |
6bdccc30 CLG |
979 | pinctrl_ndcd4_default: ndcd4_default { |
980 | function = "NDCD4"; | |
981 | groups = "NDCD4"; | |
982 | }; | |
17c5fb19 | 983 | |
6bdccc30 CLG |
984 | pinctrl_ndsr1_default: ndsr1_default { |
985 | function = "NDSR1"; | |
986 | groups = "NDSR1"; | |
987 | }; | |
17c5fb19 | 988 | |
6bdccc30 CLG |
989 | pinctrl_ndsr2_default: ndsr2_default { |
990 | function = "NDSR2"; | |
991 | groups = "NDSR2"; | |
992 | }; | |
17c5fb19 | 993 | |
6bdccc30 CLG |
994 | pinctrl_ndsr3_default: ndsr3_default { |
995 | function = "NDSR3"; | |
996 | groups = "NDSR3"; | |
997 | }; | |
17c5fb19 | 998 | |
6bdccc30 CLG |
999 | pinctrl_ndsr4_default: ndsr4_default { |
1000 | function = "NDSR4"; | |
1001 | groups = "NDSR4"; | |
1002 | }; | |
17c5fb19 | 1003 | |
6bdccc30 CLG |
1004 | pinctrl_ndtr1_default: ndtr1_default { |
1005 | function = "NDTR1"; | |
1006 | groups = "NDTR1"; | |
1007 | }; | |
17c5fb19 | 1008 | |
6bdccc30 CLG |
1009 | pinctrl_ndtr2_default: ndtr2_default { |
1010 | function = "NDTR2"; | |
1011 | groups = "NDTR2"; | |
1012 | }; | |
17c5fb19 | 1013 | |
6bdccc30 CLG |
1014 | pinctrl_ndtr3_default: ndtr3_default { |
1015 | function = "NDTR3"; | |
1016 | groups = "NDTR3"; | |
1017 | }; | |
17c5fb19 | 1018 | |
6bdccc30 CLG |
1019 | pinctrl_ndtr4_default: ndtr4_default { |
1020 | function = "NDTR4"; | |
1021 | groups = "NDTR4"; | |
1022 | }; | |
17c5fb19 | 1023 | |
6bdccc30 CLG |
1024 | pinctrl_nri1_default: nri1_default { |
1025 | function = "NRI1"; | |
1026 | groups = "NRI1"; | |
1027 | }; | |
17c5fb19 | 1028 | |
6bdccc30 CLG |
1029 | pinctrl_nri2_default: nri2_default { |
1030 | function = "NRI2"; | |
1031 | groups = "NRI2"; | |
1032 | }; | |
17c5fb19 | 1033 | |
6bdccc30 CLG |
1034 | pinctrl_nri3_default: nri3_default { |
1035 | function = "NRI3"; | |
1036 | groups = "NRI3"; | |
1037 | }; | |
17c5fb19 | 1038 | |
6bdccc30 CLG |
1039 | pinctrl_nri4_default: nri4_default { |
1040 | function = "NRI4"; | |
1041 | groups = "NRI4"; | |
1042 | }; | |
17c5fb19 | 1043 | |
6bdccc30 CLG |
1044 | pinctrl_nrts1_default: nrts1_default { |
1045 | function = "NRTS1"; | |
1046 | groups = "NRTS1"; | |
1047 | }; | |
17c5fb19 | 1048 | |
6bdccc30 CLG |
1049 | pinctrl_nrts2_default: nrts2_default { |
1050 | function = "NRTS2"; | |
1051 | groups = "NRTS2"; | |
1052 | }; | |
17c5fb19 | 1053 | |
6bdccc30 CLG |
1054 | pinctrl_nrts3_default: nrts3_default { |
1055 | function = "NRTS3"; | |
1056 | groups = "NRTS3"; | |
1057 | }; | |
17c5fb19 | 1058 | |
6bdccc30 CLG |
1059 | pinctrl_nrts4_default: nrts4_default { |
1060 | function = "NRTS4"; | |
1061 | groups = "NRTS4"; | |
1062 | }; | |
17c5fb19 | 1063 | |
6bdccc30 CLG |
1064 | pinctrl_oscclk_default: oscclk_default { |
1065 | function = "OSCCLK"; | |
1066 | groups = "OSCCLK"; | |
1067 | }; | |
17c5fb19 | 1068 | |
6bdccc30 CLG |
1069 | pinctrl_pewake_default: pewake_default { |
1070 | function = "PEWAKE"; | |
1071 | groups = "PEWAKE"; | |
1072 | }; | |
17c5fb19 | 1073 | |
6bdccc30 CLG |
1074 | pinctrl_pnor_default: pnor_default { |
1075 | function = "PNOR"; | |
1076 | groups = "PNOR"; | |
1077 | }; | |
17c5fb19 | 1078 | |
6bdccc30 CLG |
1079 | pinctrl_pwm0_default: pwm0_default { |
1080 | function = "PWM0"; | |
1081 | groups = "PWM0"; | |
1082 | }; | |
17c5fb19 | 1083 | |
6bdccc30 CLG |
1084 | pinctrl_pwm1_default: pwm1_default { |
1085 | function = "PWM1"; | |
1086 | groups = "PWM1"; | |
1087 | }; | |
17c5fb19 | 1088 | |
6bdccc30 CLG |
1089 | pinctrl_pwm2_default: pwm2_default { |
1090 | function = "PWM2"; | |
1091 | groups = "PWM2"; | |
1092 | }; | |
17c5fb19 | 1093 | |
6bdccc30 CLG |
1094 | pinctrl_pwm3_default: pwm3_default { |
1095 | function = "PWM3"; | |
1096 | groups = "PWM3"; | |
1097 | }; | |
17c5fb19 | 1098 | |
6bdccc30 CLG |
1099 | pinctrl_pwm4_default: pwm4_default { |
1100 | function = "PWM4"; | |
1101 | groups = "PWM4"; | |
1102 | }; | |
17c5fb19 | 1103 | |
6bdccc30 CLG |
1104 | pinctrl_pwm5_default: pwm5_default { |
1105 | function = "PWM5"; | |
1106 | groups = "PWM5"; | |
1107 | }; | |
17c5fb19 | 1108 | |
6bdccc30 CLG |
1109 | pinctrl_pwm6_default: pwm6_default { |
1110 | function = "PWM6"; | |
1111 | groups = "PWM6"; | |
1112 | }; | |
17c5fb19 | 1113 | |
6bdccc30 CLG |
1114 | pinctrl_pwm7_default: pwm7_default { |
1115 | function = "PWM7"; | |
1116 | groups = "PWM7"; | |
1117 | }; | |
17c5fb19 | 1118 | |
6bdccc30 CLG |
1119 | pinctrl_rgmii1_default: rgmii1_default { |
1120 | function = "RGMII1"; | |
1121 | groups = "RGMII1"; | |
1122 | }; | |
17c5fb19 | 1123 | |
6bdccc30 CLG |
1124 | pinctrl_rgmii2_default: rgmii2_default { |
1125 | function = "RGMII2"; | |
1126 | groups = "RGMII2"; | |
1127 | }; | |
17c5fb19 | 1128 | |
6bdccc30 CLG |
1129 | pinctrl_rmii1_default: rmii1_default { |
1130 | function = "RMII1"; | |
1131 | groups = "RMII1"; | |
1132 | }; | |
17c5fb19 | 1133 | |
6bdccc30 CLG |
1134 | pinctrl_rmii2_default: rmii2_default { |
1135 | function = "RMII2"; | |
1136 | groups = "RMII2"; | |
1137 | }; | |
17c5fb19 | 1138 | |
6bdccc30 CLG |
1139 | pinctrl_rxd1_default: rxd1_default { |
1140 | function = "RXD1"; | |
1141 | groups = "RXD1"; | |
1142 | }; | |
17c5fb19 | 1143 | |
6bdccc30 CLG |
1144 | pinctrl_rxd2_default: rxd2_default { |
1145 | function = "RXD2"; | |
1146 | groups = "RXD2"; | |
1147 | }; | |
17c5fb19 | 1148 | |
6bdccc30 CLG |
1149 | pinctrl_rxd3_default: rxd3_default { |
1150 | function = "RXD3"; | |
1151 | groups = "RXD3"; | |
1152 | }; | |
17c5fb19 | 1153 | |
6bdccc30 CLG |
1154 | pinctrl_rxd4_default: rxd4_default { |
1155 | function = "RXD4"; | |
1156 | groups = "RXD4"; | |
1157 | }; | |
17c5fb19 | 1158 | |
6bdccc30 CLG |
1159 | pinctrl_salt1_default: salt1_default { |
1160 | function = "SALT1"; | |
1161 | groups = "SALT1"; | |
1162 | }; | |
17c5fb19 | 1163 | |
6bdccc30 CLG |
1164 | pinctrl_salt10_default: salt10_default { |
1165 | function = "SALT10"; | |
1166 | groups = "SALT10"; | |
1167 | }; | |
17c5fb19 | 1168 | |
6bdccc30 CLG |
1169 | pinctrl_salt11_default: salt11_default { |
1170 | function = "SALT11"; | |
1171 | groups = "SALT11"; | |
1172 | }; | |
17c5fb19 | 1173 | |
6bdccc30 CLG |
1174 | pinctrl_salt12_default: salt12_default { |
1175 | function = "SALT12"; | |
1176 | groups = "SALT12"; | |
1177 | }; | |
17c5fb19 | 1178 | |
6bdccc30 CLG |
1179 | pinctrl_salt13_default: salt13_default { |
1180 | function = "SALT13"; | |
1181 | groups = "SALT13"; | |
1182 | }; | |
17c5fb19 | 1183 | |
6bdccc30 CLG |
1184 | pinctrl_salt14_default: salt14_default { |
1185 | function = "SALT14"; | |
1186 | groups = "SALT14"; | |
1187 | }; | |
17c5fb19 | 1188 | |
6bdccc30 CLG |
1189 | pinctrl_salt2_default: salt2_default { |
1190 | function = "SALT2"; | |
1191 | groups = "SALT2"; | |
1192 | }; | |
17c5fb19 | 1193 | |
6bdccc30 CLG |
1194 | pinctrl_salt3_default: salt3_default { |
1195 | function = "SALT3"; | |
1196 | groups = "SALT3"; | |
1197 | }; | |
17c5fb19 | 1198 | |
6bdccc30 CLG |
1199 | pinctrl_salt4_default: salt4_default { |
1200 | function = "SALT4"; | |
1201 | groups = "SALT4"; | |
1202 | }; | |
17c5fb19 | 1203 | |
6bdccc30 CLG |
1204 | pinctrl_salt5_default: salt5_default { |
1205 | function = "SALT5"; | |
1206 | groups = "SALT5"; | |
1207 | }; | |
17c5fb19 | 1208 | |
6bdccc30 CLG |
1209 | pinctrl_salt6_default: salt6_default { |
1210 | function = "SALT6"; | |
1211 | groups = "SALT6"; | |
1212 | }; | |
17c5fb19 | 1213 | |
6bdccc30 CLG |
1214 | pinctrl_salt7_default: salt7_default { |
1215 | function = "SALT7"; | |
1216 | groups = "SALT7"; | |
1217 | }; | |
17c5fb19 | 1218 | |
6bdccc30 CLG |
1219 | pinctrl_salt8_default: salt8_default { |
1220 | function = "SALT8"; | |
1221 | groups = "SALT8"; | |
1222 | }; | |
17c5fb19 | 1223 | |
6bdccc30 CLG |
1224 | pinctrl_salt9_default: salt9_default { |
1225 | function = "SALT9"; | |
1226 | groups = "SALT9"; | |
1227 | }; | |
17c5fb19 | 1228 | |
6bdccc30 CLG |
1229 | pinctrl_scl1_default: scl1_default { |
1230 | function = "SCL1"; | |
1231 | groups = "SCL1"; | |
1232 | }; | |
17c5fb19 | 1233 | |
6bdccc30 CLG |
1234 | pinctrl_scl2_default: scl2_default { |
1235 | function = "SCL2"; | |
1236 | groups = "SCL2"; | |
1237 | }; | |
17c5fb19 | 1238 | |
6bdccc30 CLG |
1239 | pinctrl_sd1_default: sd1_default { |
1240 | function = "SD1"; | |
1241 | groups = "SD1"; | |
1242 | }; | |
14e4b149 | 1243 | |
6bdccc30 CLG |
1244 | pinctrl_sd2_default: sd2_default { |
1245 | function = "SD2"; | |
1246 | groups = "SD2"; | |
1247 | }; | |
14e4b149 | 1248 | |
6bdccc30 CLG |
1249 | pinctrl_sda1_default: sda1_default { |
1250 | function = "SDA1"; | |
1251 | groups = "SDA1"; | |
1252 | }; | |
14e4b149 | 1253 | |
6bdccc30 CLG |
1254 | pinctrl_sda2_default: sda2_default { |
1255 | function = "SDA2"; | |
1256 | groups = "SDA2"; | |
1257 | }; | |
14e4b149 | 1258 | |
6bdccc30 CLG |
1259 | pinctrl_sgps1_default: sgps1_default { |
1260 | function = "SGPS1"; | |
1261 | groups = "SGPS1"; | |
1262 | }; | |
17c5fb19 | 1263 | |
6bdccc30 CLG |
1264 | pinctrl_sgps2_default: sgps2_default { |
1265 | function = "SGPS2"; | |
1266 | groups = "SGPS2"; | |
1267 | }; | |
14e4b149 | 1268 | |
6bdccc30 CLG |
1269 | pinctrl_sioonctrl_default: sioonctrl_default { |
1270 | function = "SIOONCTRL"; | |
1271 | groups = "SIOONCTRL"; | |
1272 | }; | |
17c5fb19 | 1273 | |
6bdccc30 CLG |
1274 | pinctrl_siopbi_default: siopbi_default { |
1275 | function = "SIOPBI"; | |
1276 | groups = "SIOPBI"; | |
1277 | }; | |
14e4b149 | 1278 | |
6bdccc30 CLG |
1279 | pinctrl_siopbo_default: siopbo_default { |
1280 | function = "SIOPBO"; | |
1281 | groups = "SIOPBO"; | |
1282 | }; | |
17c5fb19 | 1283 | |
6bdccc30 CLG |
1284 | pinctrl_siopwreq_default: siopwreq_default { |
1285 | function = "SIOPWREQ"; | |
1286 | groups = "SIOPWREQ"; | |
1287 | }; | |
14e4b149 | 1288 | |
6bdccc30 CLG |
1289 | pinctrl_siopwrgd_default: siopwrgd_default { |
1290 | function = "SIOPWRGD"; | |
1291 | groups = "SIOPWRGD"; | |
1292 | }; | |
14e4b149 | 1293 | |
6bdccc30 CLG |
1294 | pinctrl_sios3_default: sios3_default { |
1295 | function = "SIOS3"; | |
1296 | groups = "SIOS3"; | |
1297 | }; | |
14e4b149 | 1298 | |
6bdccc30 CLG |
1299 | pinctrl_sios5_default: sios5_default { |
1300 | function = "SIOS5"; | |
1301 | groups = "SIOS5"; | |
1302 | }; | |
14e4b149 | 1303 | |
6bdccc30 CLG |
1304 | pinctrl_siosci_default: siosci_default { |
1305 | function = "SIOSCI"; | |
1306 | groups = "SIOSCI"; | |
1307 | }; | |
17c5fb19 | 1308 | |
6bdccc30 CLG |
1309 | pinctrl_spi1_default: spi1_default { |
1310 | function = "SPI1"; | |
1311 | groups = "SPI1"; | |
1312 | }; | |
17c5fb19 | 1313 | |
6bdccc30 CLG |
1314 | pinctrl_spi1cs1_default: spi1cs1_default { |
1315 | function = "SPI1CS1"; | |
1316 | groups = "SPI1CS1"; | |
1317 | }; | |
17c5fb19 | 1318 | |
6bdccc30 CLG |
1319 | pinctrl_spi1debug_default: spi1debug_default { |
1320 | function = "SPI1DEBUG"; | |
1321 | groups = "SPI1DEBUG"; | |
1322 | }; | |
17c5fb19 | 1323 | |
6bdccc30 CLG |
1324 | pinctrl_spi1passthru_default: spi1passthru_default { |
1325 | function = "SPI1PASSTHRU"; | |
1326 | groups = "SPI1PASSTHRU"; | |
1327 | }; | |
17c5fb19 | 1328 | |
6bdccc30 CLG |
1329 | pinctrl_spi2ck_default: spi2ck_default { |
1330 | function = "SPI2CK"; | |
1331 | groups = "SPI2CK"; | |
1332 | }; | |
17c5fb19 | 1333 | |
6bdccc30 CLG |
1334 | pinctrl_spi2cs0_default: spi2cs0_default { |
1335 | function = "SPI2CS0"; | |
1336 | groups = "SPI2CS0"; | |
1337 | }; | |
17c5fb19 | 1338 | |
6bdccc30 CLG |
1339 | pinctrl_spi2cs1_default: spi2cs1_default { |
1340 | function = "SPI2CS1"; | |
1341 | groups = "SPI2CS1"; | |
1342 | }; | |
14e4b149 | 1343 | |
6bdccc30 CLG |
1344 | pinctrl_spi2miso_default: spi2miso_default { |
1345 | function = "SPI2MISO"; | |
1346 | groups = "SPI2MISO"; | |
1347 | }; | |
14e4b149 | 1348 | |
6bdccc30 CLG |
1349 | pinctrl_spi2mosi_default: spi2mosi_default { |
1350 | function = "SPI2MOSI"; | |
1351 | groups = "SPI2MOSI"; | |
1352 | }; | |
14e4b149 | 1353 | |
6bdccc30 CLG |
1354 | pinctrl_timer3_default: timer3_default { |
1355 | function = "TIMER3"; | |
1356 | groups = "TIMER3"; | |
1357 | }; | |
14e4b149 | 1358 | |
6bdccc30 CLG |
1359 | pinctrl_timer4_default: timer4_default { |
1360 | function = "TIMER4"; | |
1361 | groups = "TIMER4"; | |
1362 | }; | |
1363 | ||
1364 | pinctrl_timer5_default: timer5_default { | |
1365 | function = "TIMER5"; | |
1366 | groups = "TIMER5"; | |
1367 | }; | |
1368 | ||
1369 | pinctrl_timer6_default: timer6_default { | |
1370 | function = "TIMER6"; | |
1371 | groups = "TIMER6"; | |
1372 | }; | |
1373 | ||
1374 | pinctrl_timer7_default: timer7_default { | |
1375 | function = "TIMER7"; | |
1376 | groups = "TIMER7"; | |
1377 | }; | |
1378 | ||
1379 | pinctrl_timer8_default: timer8_default { | |
1380 | function = "TIMER8"; | |
1381 | groups = "TIMER8"; | |
1382 | }; | |
1383 | ||
1384 | pinctrl_txd1_default: txd1_default { | |
1385 | function = "TXD1"; | |
1386 | groups = "TXD1"; | |
1387 | }; | |
1388 | ||
1389 | pinctrl_txd2_default: txd2_default { | |
1390 | function = "TXD2"; | |
1391 | groups = "TXD2"; | |
1392 | }; | |
1393 | ||
1394 | pinctrl_txd3_default: txd3_default { | |
1395 | function = "TXD3"; | |
1396 | groups = "TXD3"; | |
1397 | }; | |
1398 | ||
1399 | pinctrl_txd4_default: txd4_default { | |
1400 | function = "TXD4"; | |
1401 | groups = "TXD4"; | |
1402 | }; | |
1403 | ||
1404 | pinctrl_uart6_default: uart6_default { | |
1405 | function = "UART6"; | |
1406 | groups = "UART6"; | |
1407 | }; | |
1408 | ||
1409 | pinctrl_usbcki_default: usbcki_default { | |
1410 | function = "USBCKI"; | |
1411 | groups = "USBCKI"; | |
1412 | }; | |
1413 | ||
1414 | pinctrl_usb2ah_default: usb2ah_default { | |
1415 | function = "USB2AH"; | |
1416 | groups = "USB2AH"; | |
1417 | }; | |
1418 | ||
1419 | pinctrl_usb11bhid_default: usb11bhid_default { | |
1420 | function = "USB11BHID"; | |
1421 | groups = "USB11BHID"; | |
1422 | }; | |
1423 | ||
1424 | pinctrl_usb2bh_default: usb2bh_default { | |
1425 | function = "USB2BH"; | |
1426 | groups = "USB2BH"; | |
1427 | }; | |
1428 | ||
1429 | pinctrl_vgabiosrom_default: vgabiosrom_default { | |
1430 | function = "VGABIOSROM"; | |
1431 | groups = "VGABIOSROM"; | |
1432 | }; | |
1433 | ||
1434 | pinctrl_vgahs_default: vgahs_default { | |
1435 | function = "VGAHS"; | |
1436 | groups = "VGAHS"; | |
1437 | }; | |
1438 | ||
1439 | pinctrl_vgavs_default: vgavs_default { | |
1440 | function = "VGAVS"; | |
1441 | groups = "VGAVS"; | |
1442 | }; | |
1443 | ||
1444 | pinctrl_vpi24_default: vpi24_default { | |
1445 | function = "VPI24"; | |
1446 | groups = "VPI24"; | |
1447 | }; | |
1448 | ||
1449 | pinctrl_vpo_default: vpo_default { | |
1450 | function = "VPO"; | |
1451 | groups = "VPO"; | |
1452 | }; | |
1453 | ||
1454 | pinctrl_wdtrst1_default: wdtrst1_default { | |
1455 | function = "WDTRST1"; | |
1456 | groups = "WDTRST1"; | |
1457 | }; | |
1458 | ||
1459 | pinctrl_wdtrst2_default: wdtrst2_default { | |
1460 | function = "WDTRST2"; | |
1461 | groups = "WDTRST2"; | |
14e4b149 | 1462 | }; |
be298254 BT |
1463 | |
1464 | pinctrl_sgpm_default: sgpm_default { | |
1465 | function = "SGPM"; | |
1466 | groups = "SGPM"; | |
1467 | }; | |
14e4b149 | 1468 | }; |