[J-u-boot.git] / arch / arm / dts / armada-37xx.dtsi

// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/*
 * Device Tree Include file for Marvell Armada 37xx family of SoCs.
 *
 * Copyright (C) 2016 Marvell
 *
 * Gregory CLEMENT <[email protected]>
 *
 */

#include <dt-bindings/interrupt-controller/arm-gic.h>

/ {
	model = "Marvell Armada 37xx SoC";
	compatible = "marvell,armada3700";
	interrupt-parent = <&gic>;
	#address-cells = <2>;
	#size-cells = <2>;

	aliases {
		serial0 = &uart0;
		serial1 = &uart1;
	};

	reserved-memory {
		#address-cells = <2>;
		#size-cells = <2>;
		ranges;

		/*
		 * The PSCI firmware region depicted below is the default one
		 * and should be updated by the bootloader.
		 */
		psci-area@4000000 {
			reg = <0 0x4000000 0 0x200000>;
			no-map;
		};
	};

	cpus {
		#address-cells = <1>;
		#size-cells = <0>;
		cpu0: cpu@0 {
			device_type = "cpu";
			compatible = "arm,cortex-a53";
			reg = <0>;
			clocks = <&nb_periph_clk 16>;
			enable-method = "psci";
		};
	};

	psci {
		compatible = "arm,psci-0.2";
		method = "smc";
	};

	timer {
		compatible = "arm,armv8-timer";
		interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_HIGH>,
			     <GIC_PPI 14 IRQ_TYPE_LEVEL_HIGH>,
			     <GIC_PPI 11 IRQ_TYPE_LEVEL_HIGH>,
			     <GIC_PPI 10 IRQ_TYPE_LEVEL_HIGH>;
	};

	pmu {
		compatible = "arm,armv8-pmuv3";
		interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_HIGH>;
	};

	soc {
		compatible = "simple-bus";
		#address-cells = <2>;
		#size-cells = <2>;
		ranges;

		internal-regs@d0000000 {
			#address-cells = <1>;
			#size-cells = <1>;
			compatible = "simple-bus";
			/* 32M internal register @ 0xd000_0000 */
			ranges = <0x0 0x0 0xd0000000 0x2000000>;

			wdt: watchdog@8300 {
				compatible = "marvell,armada-3700-wdt";
				reg = <0x8300 0x40>;
				marvell,system-controller = <&cpu_misc>;
				clocks = <&xtalclk>;
			};

			cpu_misc: system-controller@d000 {
				compatible = "marvell,armada-3700-cpu-misc",
					     "syscon";
				reg = <0xd000 0x1000>;
			};

			spi0: spi@10600 {
				compatible = "marvell,armada-3700-spi";
				#address-cells = <1>;
				#size-cells = <0>;
				reg = <0x10600 0xA00>;
				clocks = <&nb_periph_clk 7>;
				interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>;
				num-cs = <4>;
				status = "disabled";
			};

			i2c0: i2c@11000 {
				compatible = "marvell,armada-3700-i2c";
				reg = <0x11000 0x24>;
				#address-cells = <1>;
				#size-cells = <0>;
				clocks = <&nb_periph_clk 10>;
				interrupts = <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>;
				mrvl,i2c-fast-mode;
				status = "disabled";
			};

			i2c1: i2c@11080 {
				compatible = "marvell,armada-3700-i2c";
				reg = <0x11080 0x24>;
				#address-cells = <1>;
				#size-cells = <0>;
				clocks = <&nb_periph_clk 9>;
				interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>;
				mrvl,i2c-fast-mode;
				status = "disabled";
			};

			avs: avs@11500 {
				compatible = "marvell,armada-3700-avs",
					     "syscon";
				reg = <0x11500 0x40>;
			};

			uart0: serial@12000 {
				compatible = "marvell,armada-3700-uart";
				reg = <0x12000 0x18>;
				clocks = <&xtalclk>;
				interrupts =
				<GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>,
				<GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>,
				<GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
				interrupt-names = "uart-sum", "uart-tx", "uart-rx";
				status = "disabled";
			};

			uart1: serial@12200 {
				compatible = "marvell,armada-3700-uart-ext";
				reg = <0x12200 0x30>;
				clocks = <&xtalclk>;
				interrupts =
				<GIC_SPI 30 IRQ_TYPE_EDGE_RISING>,
				<GIC_SPI 31 IRQ_TYPE_EDGE_RISING>;
				interrupt-names = "uart-tx", "uart-rx";
				status = "disabled";
			};

			nb_periph_clk: nb-periph-clk@13000 {
				compatible = "marvell,armada-3700-periph-clock-nb",
					     "syscon";
				reg = <0x13000 0x100>;
				clocks = <&tbg 0>, <&tbg 1>, <&tbg 2>,
				<&tbg 3>, <&xtalclk>;
				#clock-cells = <1>;
			};

			sb_periph_clk: sb-periph-clk@18000 {
				compatible = "marvell,armada-3700-periph-clock-sb";
				reg = <0x18000 0x100>;
				clocks = <&tbg 0>, <&tbg 1>, <&tbg 2>,
				<&tbg 3>, <&xtalclk>;
				#clock-cells = <1>;
			};

			tbg: tbg@13200 {
				compatible = "marvell,armada-3700-tbg-clock";
				reg = <0x13200 0x100>;
				clocks = <&xtalclk>;
				#clock-cells = <1>;
			};

			pinctrl_nb: pinctrl@13800 {
				compatible = "marvell,armada3710-nb-pinctrl",
					     "syscon", "simple-mfd";
				reg = <0x13800 0x100>, <0x13C00 0x20>;
				/* MPP1[19:0] */
				gpionb: gpio {
					#gpio-cells = <2>;
					gpio-ranges = <&pinctrl_nb 0 0 36>;
					gpio-controller;
					interrupt-controller;
					#interrupt-cells = <2>;
					interrupts =
					<GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>,
					<GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>,
					<GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>,
					<GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>,
					<GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>,
					<GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>,
					<GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>,
					<GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>,
					<GIC_SPI 152 IRQ_TYPE_LEVEL_HIGH>,
					<GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>,
					<GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>,
					<GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>;
				};

				xtalclk: xtal-clk {
					compatible = "marvell,armada-3700-xtal-clock";
					clock-output-names = "xtal";
					#clock-cells = <0>;
				};

				spi_quad_pins: spi-quad-pins {
					groups = "spi_quad";
					function = "spi";
				};

				spi_cs1_pins: spi-cs1-pins {
					groups = "spi_cs1";
					function = "spi";
				};

				i2c1_pins: i2c1-pins {
					groups = "i2c1";
					function = "i2c";
				};

				i2c2_pins: i2c2-pins {
					groups = "i2c2";
					function = "i2c";
				};

				uart1_pins: uart1-pins {
					groups = "uart1";
					function = "uart";
				};

				uart2_pins: uart2-pins {
					groups = "uart2";
					function = "uart";
				};

				mmc_pins: mmc-pins {
					groups = "emmc_nb";
					function = "emmc";
				};
			};

			nb_pm: syscon@14000 {
				compatible = "marvell,armada-3700-nb-pm",
					     "syscon";
				reg = <0x14000 0x60>;
			};

			comphy: phy@18300 {
				compatible = "marvell,comphy-a3700";
				reg = <0x18300 0x300>,
				      <0x1F000 0x400>,
				      <0x5C000 0x400>,
				      <0xe0178 0x8>;
				reg-names = "comphy",
					    "lane1_pcie_gbe",
					    "lane0_usb3_gbe",
					    "lane2_sata_usb3";
				#address-cells = <1>;
				#size-cells = <0>;
				clocks = <&xtalclk>;
				clock-names = "xtal";

				comphy0: phy@0 {
					reg = <0>;
					#phy-cells = <1>;
				};

				comphy1: phy@1 {
					reg = <1>;
					#phy-cells = <1>;
				};

				comphy2: phy@2 {
					reg = <2>;
					#phy-cells = <1>;
				};
			};

			pinctrl_sb: pinctrl@18800 {
				compatible = "marvell,armada3710-sb-pinctrl",
					     "syscon", "simple-mfd";
				reg = <0x18800 0x100>, <0x18C00 0x20>;
				/* MPP2[23:0] */
				gpiosb: gpio {
					#gpio-cells = <2>;
					gpio-ranges = <&pinctrl_sb 0 0 30>;
					gpio-controller;
					interrupt-controller;
					#interrupt-cells = <2>;
					interrupts =
					<GIC_SPI 160 IRQ_TYPE_LEVEL_HIGH>,
					<GIC_SPI 159 IRQ_TYPE_LEVEL_HIGH>,
					<GIC_SPI 158 IRQ_TYPE_LEVEL_HIGH>,
					<GIC_SPI 157 IRQ_TYPE_LEVEL_HIGH>,
					<GIC_SPI 156 IRQ_TYPE_LEVEL_HIGH>;
				};

				rgmii_pins: mii-pins {
					groups = "rgmii";
					function = "mii";
				};

				smi_pins: smi-pins {
					groups = "smi";
					function = "smi";
				};

				sdio_pins: sdio-pins {
					groups = "sdio_sb";
					function = "sdio";
				};

				pcie_reset_pins: pcie-reset-pins {
					groups = "pcie1"; /* this actually controls "pcie1_reset" */
					function = "gpio";
				};

				pcie_clkreq_pins: pcie-clkreq-pins {
					groups = "pcie1_clkreq";
					function = "pcie";
				};
			};

			eth0: ethernet@30000 {
				   compatible = "marvell,armada-3700-neta";
				   reg = <0x30000 0x4000>;
				   interrupts = <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>;
				   clocks = <&sb_periph_clk 8>;
				   status = "disabled";
			};

			mdio: mdio@32004 {
				#address-cells = <1>;
				#size-cells = <0>;
				compatible = "marvell,orion-mdio";
				reg = <0x32004 0x4>;
			};

			eth1: ethernet@40000 {
				compatible = "marvell,armada-3700-neta";
				reg = <0x40000 0x4000>;
				interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>;
				clocks = <&sb_periph_clk 7>;
				status = "disabled";
			};

			usb3: usb@58000 {
				compatible = "marvell,armada3700-xhci",
				"generic-xhci";
				reg = <0x58000 0x4000>;
				marvell,usb-misc-reg = <&usb32_syscon>;
				interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>;
				clocks = <&sb_periph_clk 12>;
				phys = <&comphy0 0>, <&usb2_utmi_otg_phy>;
				phy-names = "usb3-phy", "usb2-utmi-otg-phy";
				status = "disabled";
			};

			usb2_utmi_otg_phy: phy@5d000 {
				compatible = "marvell,a3700-utmi-otg-phy";
				reg = <0x5d000 0x800>;
				marvell,usb-misc-reg = <&usb32_syscon>;
				#phy-cells = <0>;
			};

			usb32_syscon: system-controller@5d800 {
				compatible = "marvell,armada-3700-usb2-host-device-misc",
				"syscon";
				reg = <0x5d800 0x800>;
			};

			usb2: usb@5e000 {
				compatible = "marvell,armada-3700-ehci";
				reg = <0x5e000 0x1000>;
				marvell,usb-misc-reg = <&usb2_syscon>;
				interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
				phys = <&usb2_utmi_host_phy>;
				phy-names = "usb2-utmi-host-phy";
				status = "disabled";
			};

			usb2_utmi_host_phy: phy@5f000 {
				compatible = "marvell,a3700-utmi-host-phy";
				reg = <0x5f000 0x800>;
				marvell,usb-misc-reg = <&usb2_syscon>;
				#phy-cells = <0>;
			};

			usb2_syscon: system-controller@5f800 {
				compatible = "marvell,armada-3700-usb2-host-misc",
				"syscon";
				reg = <0x5f800 0x800>;
			};

			xor@60900 {
				compatible = "marvell,armada-3700-xor";
				reg = <0x60900 0x100>,
				      <0x60b00 0x100>;

				xor10 {
					interrupts = <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>;
				};
				xor11 {
					interrupts = <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>;
				};
			};

			crypto: crypto@90000 {
				compatible = "inside-secure,safexcel-eip97ies";
				reg = <0x90000 0x20000>;
				interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>,
					     <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>,
					     <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>,
					     <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>,
					     <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>,
					     <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>;
				interrupt-names = "mem", "ring0", "ring1",
						  "ring2", "ring3", "eip";
				clocks = <&nb_periph_clk 15>;
			};

			rwtm: mailbox@b0000 {
				compatible = "marvell,armada-3700-rwtm-mailbox";
				reg = <0xb0000 0x100>;
				interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>;
				#mbox-cells = <1>;
			};

			sdhci1: sdhci@d0000 {
				compatible = "marvell,armada-3700-sdhci",
					     "marvell,sdhci-xenon";
				reg = <0xd0000 0x300>,
				      <0x1e808 0x4>;
				interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>;
				clocks = <&nb_periph_clk 0>;
				clock-names = "core";
				status = "disabled";
			};

			sdhci0: sdhci@d8000 {
				compatible = "marvell,armada-3700-sdhci",
					     "marvell,sdhci-xenon";
				reg = <0xd8000 0x300>,
				      <0x17808 0x4>;
				interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>;
				clocks = <&nb_periph_clk 0>;
				clock-names = "core";
				status = "disabled";
			};

			sata: sata@e0000 {
				compatible = "marvell,armada-3700-ahci";
				reg = <0xe0000 0x178>;
				interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>;
				clocks = <&nb_periph_clk 1>;
				phys = <&comphy2 0>;
				phy-names = "sata-phy";
				status = "disabled";
			};

			gic: interrupt-controller@1d00000 {
				compatible = "arm,gic-v3";
				#interrupt-cells = <3>;
				interrupt-controller;
				reg = <0x1d00000 0x10000>, /* GICD */
				      <0x1d40000 0x40000>, /* GICR */
				      <0x1d80000 0x2000>,  /* GICC */
				      <0x1d90000 0x2000>,  /* GICH */
				      <0x1da0000 0x20000>; /* GICV */
				interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
			};
		};

		pcie0: pcie@d0070000 {
			compatible = "marvell,armada-3700-pcie";
			device_type = "pci";
			status = "disabled";
			reg = <0 0xd0070000 0 0x20000>;
			#address-cells = <3>;
			#size-cells = <2>;
			bus-range = <0x00 0xff>;
			interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>;
			#interrupt-cells = <1>;
			msi-parent = <&pcie0>;
			msi-controller;
			/*
			 * The 128 MiB address range [0xe8000000-0xf0000000] is
			 * dedicated for PCIe and can be assigned to 8 windows
			 * with size a power of two. Use one 1 MiB window for
			 * IO at the end and the remaining seven windows
			 * (totaling 127 MiB) for MEM.
			 */
			ranges = <0x82000000 0 0xe8000000   0 0xe8000000   0 0x07f00000   /* Port 0 MEM */
				  0x81000000 0 0x00000000   0 0xeff00000   0 0x00100000>; /* Port 0 IO */
			interrupt-map-mask = <0 0 0 7>;
			interrupt-map = <0 0 0 1 &pcie_intc 0>,
					<0 0 0 2 &pcie_intc 1>,
					<0 0 0 3 &pcie_intc 2>,
					<0 0 0 4 &pcie_intc 3>;
			max-link-speed = <2>;
			phys = <&comphy1 0>;
			pcie_intc: interrupt-controller {
				interrupt-controller;
				#interrupt-cells = <1>;
			};
		};
	};

	firmware {
		armada-3700-rwtm {
			compatible = "marvell,armada-3700-rwtm-firmware";
			mboxes = <&rwtm 0>;
			status = "okay";
		};
	};
};
Commit	Line	Data
0934dddc	1	// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
850db82f SR	2	/*
	3	* Device Tree Include file for Marvell Armada 37xx family of SoCs.
	4	*
	5	* Copyright (C) 2016 Marvell
	6	*
	7	* Gregory CLEMENT <[email protected]>
	8	*
850db82f SR	9	*/
	10
	11	#include <dt-bindings/interrupt-controller/arm-gic.h>
	12
	13	/ {
	14	model = "Marvell Armada 37xx SoC";
	15	compatible = "marvell,armada3700";
	16	interrupt-parent = <&gic>;
	17	#address-cells = <2>;
	18	#size-cells = <2>;
	19
	20	aliases {
	21	serial0 = &uart0;
0934dddc T	22	serial1 = &uart1;
	23	};
	24
	25	reserved-memory {
	26	#address-cells = <2>;
	27	#size-cells = <2>;
	28	ranges;
	29
	30	/*
	31	* The PSCI firmware region depicted below is the default one
	32	* and should be updated by the bootloader.
	33	*/
	34	psci-area@4000000 {
	35	reg = <0 0x4000000 0 0x200000>;
	36	no-map;
	37	};
850db82f SR	38	};
	39
	40	cpus {
	41	#address-cells = <1>;
	42	#size-cells = <0>;
0934dddc	43	cpu0: cpu@0 {
850db82f	44	device_type = "cpu";
0934dddc	45	compatible = "arm,cortex-a53";
850db82f	46	reg = <0>;
0934dddc	47	clocks = <&nb_periph_clk 16>;
850db82f SR	48	enable-method = "psci";
	49	};
	50	};
	51
	52	psci {
	53	compatible = "arm,psci-0.2";
	54	method = "smc";
	55	};
	56
	57	timer {
	58	compatible = "arm,armv8-timer";
0934dddc T	59	interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_HIGH>,
	60	<GIC_PPI 14 IRQ_TYPE_LEVEL_HIGH>,
	61	<GIC_PPI 11 IRQ_TYPE_LEVEL_HIGH>,
	62	<GIC_PPI 10 IRQ_TYPE_LEVEL_HIGH>;
	63	};
	64
	65	pmu {
	66	compatible = "arm,armv8-pmuv3";
	67	interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_HIGH>;
850db82f SR	68	};
	69
	70	soc {
	71	compatible = "simple-bus";
	72	#address-cells = <2>;
	73	#size-cells = <2>;
	74	ranges;
	75
0934dddc	76	internal-regs@d0000000 {
850db82f SR	77	#address-cells = <1>;
	78	#size-cells = <1>;
	79	compatible = "simple-bus";
	80	/* 32M internal register @ 0xd000_0000 */
	81	ranges = <0x0 0x0 0xd0000000 0x2000000>;
	82
0934dddc T	83	wdt: watchdog@8300 {
	84	compatible = "marvell,armada-3700-wdt";
	85	reg = <0x8300 0x40>;
	86	marvell,system-controller = <&cpu_misc>;
	87	clocks = <&xtalclk>;
	88	};
	89
	90	cpu_misc: system-controller@d000 {
	91	compatible = "marvell,armada-3700-cpu-misc",
	92	"syscon";
	93	reg = <0xd000 0x1000>;
	94	};
	95
	96	spi0: spi@10600 {
	97	compatible = "marvell,armada-3700-spi";
	98	#address-cells = <1>;
	99	#size-cells = <0>;
	100	reg = <0x10600 0xA00>;
	101	clocks = <&nb_periph_clk 7>;
	102	interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>;
	103	num-cs = <4>;
	104	status = "disabled";
	105	};
	106
	107	i2c0: i2c@11000 {
	108	compatible = "marvell,armada-3700-i2c";
	109	reg = <0x11000 0x24>;
	110	#address-cells = <1>;
	111	#size-cells = <0>;
	112	clocks = <&nb_periph_clk 10>;
	113	interrupts = <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>;
	114	mrvl,i2c-fast-mode;
	115	status = "disabled";
	116	};
	117
	118	i2c1: i2c@11080 {
	119	compatible = "marvell,armada-3700-i2c";
	120	reg = <0x11080 0x24>;
	121	#address-cells = <1>;
	122	#size-cells = <0>;
	123	clocks = <&nb_periph_clk 9>;
	124	interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>;
	125	mrvl,i2c-fast-mode;
	126	status = "disabled";
	127	};
	128
	129	avs: avs@11500 {
	130	compatible = "marvell,armada-3700-avs",
	131	"syscon";
	132	reg = <0x11500 0x40>;
	133	};
	134
850db82f SR	135	uart0: serial@12000 {
850db82f SR	136	compatible = "marvell,armada-3700-uart";
0934dddc T	137	reg = <0x12000 0x18>;
	138	clocks = <&xtalclk>;
	139	interrupts =
	140	<GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>,
	141	<GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>,
	142	<GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
	143	interrupt-names = "uart-sum", "uart-tx", "uart-rx";
850db82f SR	144	status = "disabled";
	145	};
	146
0934dddc T	147	uart1: serial@12200 {
	148	compatible = "marvell,armada-3700-uart-ext";
	149	reg = <0x12200 0x30>;
	150	clocks = <&xtalclk>;
	151	interrupts =
	152	<GIC_SPI 30 IRQ_TYPE_EDGE_RISING>,
	153	<GIC_SPI 31 IRQ_TYPE_EDGE_RISING>;
	154	interrupt-names = "uart-tx", "uart-rx";
	155	status = "disabled";
2b69a673 MB	156	};
2b69a673 MB	157
82a248df	158	nb_periph_clk: nb-periph-clk@13000 {
0934dddc T	159	compatible = "marvell,armada-3700-periph-clock-nb",
0934dddc T	160	"syscon";
82a248df	161	reg = <0x13000 0x100>;
0934dddc T	162	clocks = <&tbg 0>, <&tbg 1>, <&tbg 2>,
0934dddc T	163	<&tbg 3>, <&xtalclk>;
82a248df MB	164	#clock-cells = <1>;
	165	};
	166
	167	sb_periph_clk: sb-periph-clk@18000 {
	168	compatible = "marvell,armada-3700-periph-clock-sb";
	169	reg = <0x18000 0x100>;
0934dddc T	170	clocks = <&tbg 0>, <&tbg 1>, <&tbg 2>,
0934dddc T	171	<&tbg 3>, <&xtalclk>;
82a248df MB	172	#clock-cells = <1>;
	173	};
	174
	175	tbg: tbg@13200 {
	176	compatible = "marvell,armada-3700-tbg-clock";
	177	reg = <0x13200 0x100>;
0934dddc	178	clocks = <&xtalclk>;
82a248df MB	179	#clock-cells = <1>;
	180	};
	181
0934dddc	182	pinctrl_nb: pinctrl@13800 {
5cb7b795	183	compatible = "marvell,armada3710-nb-pinctrl",
0934dddc	184	"syscon", "simple-mfd";
5cb7b795	185	reg = <0x13800 0x100>, <0x13C00 0x20>;
0934dddc T	186	/* MPP1[19:0] */
0934dddc T	187	gpionb: gpio {
5cb7b795 GC	188	#gpio-cells = <2>;
	189	gpio-ranges = <&pinctrl_nb 0 0 36>;
	190	gpio-controller;
0934dddc T	191	interrupt-controller;
0934dddc T	192	#interrupt-cells = <2>;
5cb7b795 GC	193	interrupts =
	194	<GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>,
	195	<GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>,
	196	<GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>,
	197	<GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>,
	198	<GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>,
	199	<GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>,
	200	<GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>,
	201	<GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>,
	202	<GIC_SPI 152 IRQ_TYPE_LEVEL_HIGH>,
	203	<GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>,
	204	<GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>,
	205	<GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>;
0934dddc	206	};
5cb7b795	207
0934dddc T	208	xtalclk: xtal-clk {
	209	compatible = "marvell,armada-3700-xtal-clock";
	210	clock-output-names = "xtal";
	211	#clock-cells = <0>;
5cb7b795	212	};
045504bb GC	213
	214	spi_quad_pins: spi-quad-pins {
	215	groups = "spi_quad";
	216	function = "spi";
	217	};
	218
0934dddc T	219	spi_cs1_pins: spi-cs1-pins {
	220	groups = "spi_cs1";
	221	function = "spi";
	222	};
	223
045504bb GC	224	i2c1_pins: i2c1-pins {
	225	groups = "i2c1";
	226	function = "i2c";
	227	};
	228
	229	i2c2_pins: i2c2-pins {
	230	groups = "i2c2";
	231	function = "i2c";
	232	};
	233
	234	uart1_pins: uart1-pins {
	235	groups = "uart1";
	236	function = "uart";
	237	};
	238
	239	uart2_pins: uart2-pins {
	240	groups = "uart2";
	241	function = "uart";
	242	};
4382e53e KM	243
	244	mmc_pins: mmc-pins {
	245	groups = "emmc_nb";
	246	function = "emmc";
	247	};
5cb7b795 GC	248	};
5cb7b795 GC	249
0934dddc T	250	nb_pm: syscon@14000 {
	251	compatible = "marvell,armada-3700-nb-pm",
	252	"syscon";
	253	reg = <0x14000 0x60>;
	254	};
	255
	256	comphy: phy@18300 {
	257	compatible = "marvell,comphy-a3700";
	258	reg = <0x18300 0x300>,
	259	<0x1F000 0x400>,
	260	<0x5C000 0x400>,
	261	<0xe0178 0x8>;
	262	reg-names = "comphy",
	263	"lane1_pcie_gbe",
	264	"lane0_usb3_gbe",
	265	"lane2_sata_usb3";
	266	#address-cells = <1>;
	267	#size-cells = <0>;
	268	clocks = <&xtalclk>;
	269	clock-names = "xtal";
	270
	271	comphy0: phy@0 {
	272	reg = <0>;
	273	#phy-cells = <1>;
	274	};
	275
	276	comphy1: phy@1 {
	277	reg = <1>;
	278	#phy-cells = <1>;
	279	};
	280
	281	comphy2: phy@2 {
	282	reg = <2>;
	283	#phy-cells = <1>;
	284	};
	285	};
	286
	287	pinctrl_sb: pinctrl@18800 {
5cb7b795	288	compatible = "marvell,armada3710-sb-pinctrl",
0934dddc	289	"syscon", "simple-mfd";
5cb7b795	290	reg = <0x18800 0x100>, <0x18C00 0x20>;
0934dddc T	291	/* MPP2[23:0] */
0934dddc T	292	gpiosb: gpio {
5cb7b795	293	#gpio-cells = <2>;
8aecbcd1	294	gpio-ranges = <&pinctrl_sb 0 0 30>;
5cb7b795	295	gpio-controller;
0934dddc T	296	interrupt-controller;
0934dddc T	297	#interrupt-cells = <2>;
5cb7b795 GC	298	interrupts =
	299	<GIC_SPI 160 IRQ_TYPE_LEVEL_HIGH>,
	300	<GIC_SPI 159 IRQ_TYPE_LEVEL_HIGH>,
	301	<GIC_SPI 158 IRQ_TYPE_LEVEL_HIGH>,
	302	<GIC_SPI 157 IRQ_TYPE_LEVEL_HIGH>,
	303	<GIC_SPI 156 IRQ_TYPE_LEVEL_HIGH>;
	304	};
045504bb GC	305
	306	rgmii_pins: mii-pins {
	307	groups = "rgmii";
	308	function = "mii";
	309	};
	310
30aecc02 KM	311	smi_pins: smi-pins {
	312	groups = "smi";
	313	function = "smi";
	314	};
	315
4382e53e KM	316	sdio_pins: sdio-pins {
	317	groups = "sdio_sb";
	318	function = "sdio";
	319	};
	320
0934dddc T	321	pcie_reset_pins: pcie-reset-pins {
0934dddc T	322	groups = "pcie1"; /* this actually controls "pcie1_reset" */
30aecc02	323	function = "gpio";
4382e53e	324	};
0934dddc T	325
	326	pcie_clkreq_pins: pcie-clkreq-pins {
	327	groups = "pcie1_clkreq";
	328	function = "pcie";
	329	};
	330	};
	331
	332	eth0: ethernet@30000 {
	333	compatible = "marvell,armada-3700-neta";
	334	reg = <0x30000 0x4000>;
	335	interrupts = <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>;
	336	clocks = <&sb_periph_clk 8>;
	337	status = "disabled";
	338	};
	339
	340	mdio: mdio@32004 {
	341	#address-cells = <1>;
	342	#size-cells = <0>;
	343	compatible = "marvell,orion-mdio";
	344	reg = <0x32004 0x4>;
	345	};
	346
	347	eth1: ethernet@40000 {
	348	compatible = "marvell,armada-3700-neta";
	349	reg = <0x40000 0x4000>;
	350	interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>;
	351	clocks = <&sb_periph_clk 7>;
	352	status = "disabled";
5cb7b795 GC	353	};
5cb7b795 GC	354
850db82f SR	355	usb3: usb@58000 {
	356	compatible = "marvell,armada3700-xhci",
	357	"generic-xhci";
	358	reg = <0x58000 0x4000>;
0934dddc T	359	marvell,usb-misc-reg = <&usb32_syscon>;
	360	interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>;
	361	clocks = <&sb_periph_clk 12>;
	362	phys = <&comphy0 0>, <&usb2_utmi_otg_phy>;
	363	phy-names = "usb3-phy", "usb2-utmi-otg-phy";
850db82f SR	364	status = "disabled";
	365	};
	366
0934dddc T	367	usb2_utmi_otg_phy: phy@5d000 {
	368	compatible = "marvell,a3700-utmi-otg-phy";
	369	reg = <0x5d000 0x800>;
	370	marvell,usb-misc-reg = <&usb32_syscon>;
	371	#phy-cells = <0>;
	372	};
	373
	374	usb32_syscon: system-controller@5d800 {
	375	compatible = "marvell,armada-3700-usb2-host-device-misc",
	376	"syscon";
	377	reg = <0x5d800 0x800>;
	378	};
	379
f733228a	380	usb2: usb@5e000 {
af6d0938	381	compatible = "marvell,armada-3700-ehci";
0934dddc T	382	reg = <0x5e000 0x1000>;
	383	marvell,usb-misc-reg = <&usb2_syscon>;
	384	interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
	385	phys = <&usb2_utmi_host_phy>;
	386	phy-names = "usb2-utmi-host-phy";
f733228a SR	387	status = "disabled";
	388	};
	389
0934dddc T	390	usb2_utmi_host_phy: phy@5f000 {
	391	compatible = "marvell,a3700-utmi-host-phy";
	392	reg = <0x5f000 0x800>;
	393	marvell,usb-misc-reg = <&usb2_syscon>;
	394	#phy-cells = <0>;
	395	};
	396
	397	usb2_syscon: system-controller@5f800 {
	398	compatible = "marvell,armada-3700-usb2-host-misc",
	399	"syscon";
	400	reg = <0x5f800 0x800>;
	401	};
	402
850db82f SR	403	xor@60900 {
850db82f SR	404	compatible = "marvell,armada-3700-xor";
0934dddc T	405	reg = <0x60900 0x100>,
0934dddc T	406	<0x60b00 0x100>;
850db82f SR	407
	408	xor10 {
	409	interrupts = <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>;
	410	};
	411	xor11 {
	412	interrupts = <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>;
	413	};
	414	};
	415
0934dddc T	416	crypto: crypto@90000 {
	417	compatible = "inside-secure,safexcel-eip97ies";
	418	reg = <0x90000 0x20000>;
	419	interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>,
	420	<GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>,
	421	<GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>,
	422	<GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>,
	423	<GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>,
	424	<GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>;
	425	interrupt-names = "mem", "ring0", "ring1",
	426	"ring2", "ring3", "eip";
	427	clocks = <&nb_periph_clk 15>;
	428	};
	429
	430	rwtm: mailbox@b0000 {
	431	compatible = "marvell,armada-3700-rwtm-mailbox";
	432	reg = <0xb0000 0x100>;
	433	interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>;
	434	#mbox-cells = <1>;
	435	};
	436
9dde7a09	437	sdhci1: sdhci@d0000 {
cbe0ece8	438	compatible = "marvell,armada-3700-sdhci",
0934dddc T	439	"marvell,sdhci-xenon";
	440	reg = <0xd0000 0x300>,
	441	<0x1e808 0x4>;
	442	interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>;
	443	clocks = <&nb_periph_clk 0>;
	444	clock-names = "core";
cbe0ece8 SR	445	status = "disabled";
	446	};
	447
9dde7a09	448	sdhci0: sdhci@d8000 {
cbe0ece8	449	compatible = "marvell,armada-3700-sdhci",
0934dddc T	450	"marvell,sdhci-xenon";
	451	reg = <0xd8000 0x300>,
	452	<0x17808 0x4>;
	453	interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>;
	454	clocks = <&nb_periph_clk 0>;
	455	clock-names = "core";
cbe0ece8 SR	456	status = "disabled";
	457	};
	458
850db82f SR	459	sata: sata@e0000 {
850db82f SR	460	compatible = "marvell,armada-3700-ahci";
0934dddc	461	reg = <0xe0000 0x178>;
850db82f	462	interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>;
0934dddc T	463	clocks = <&nb_periph_clk 1>;
	464	phys = <&comphy2 0>;
	465	phy-names = "sata-phy";
850db82f SR	466	status = "disabled";
	467	};
	468
	469	gic: interrupt-controller@1d00000 {
	470	compatible = "arm,gic-v3";
	471	#interrupt-cells = <3>;
	472	interrupt-controller;
	473	reg = <0x1d00000 0x10000>, /* GICD */
0934dddc T	474	<0x1d40000 0x40000>, /* GICR */
	475	<0x1d80000 0x2000>, /* GICC */
	476	<0x1d90000 0x2000>, /* GICH */
	477	<0x1da0000 0x20000>; /* GICV */
	478	interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
56d53956	479	};
850db82f	480	};
9734104f WD	481
9734104f WD	482	pcie0: pcie@d0070000 {
a544d65f	483	compatible = "marvell,armada-3700-pcie";
0934dddc T	484	device_type = "pci";
0934dddc T	485	status = "disabled";
9734104f WD	486	reg = <0 0xd0070000 0 0x20000>;
	487	#address-cells = <3>;
	488	#size-cells = <2>;
0934dddc T	489	bus-range = <0x00 0xff>;
	490	interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>;
	491	#interrupt-cells = <1>;
	492	msi-parent = <&pcie0>;
	493	msi-controller;
079b35a2 T	494	/*
	495	* The 128 MiB address range [0xe8000000-0xf0000000] is
	496	* dedicated for PCIe and can be assigned to 8 windows
646a1522	497	* with size a power of two. Use one 1 MiB window for
079b35a2 T	498	* IO at the end and the remaining seven windows
	499	* (totaling 127 MiB) for MEM.
	500	*/
0934dddc	501	ranges = <0x82000000 0 0xe8000000 0 0xe8000000 0 0x07f00000 /* Port 0 MEM */
037bb6e2	502	0x81000000 0 0x00000000 0 0xeff00000 0 0x00100000>; /* Port 0 IO */
0934dddc T	503	interrupt-map-mask = <0 0 0 7>;
	504	interrupt-map = <0 0 0 1 &pcie_intc 0>,
	505	<0 0 0 2 &pcie_intc 1>,
	506	<0 0 0 3 &pcie_intc 2>,
	507	<0 0 0 4 &pcie_intc 3>;
	508	max-link-speed = <2>;
	509	phys = <&comphy1 0>;
	510	pcie_intc: interrupt-controller {
	511	interrupt-controller;
	512	#interrupt-cells = <1>;
	513	};
	514	};
	515	};
	516
	517	firmware {
	518	armada-3700-rwtm {
	519	compatible = "marvell,armada-3700-rwtm-firmware";
	520	mboxes = <&rwtm 0>;
	521	status = "okay";
9734104f	522	};
850db82f SR	523	};
850db82f SR	524	};