[J-u-boot.git] / include / configs / pf5200.h

/*
 * (C) Copyright 2003-2004
 * Wolfgang Denk, DENX Software Engineering, [email protected].
 *
 * See file CREDITS for list of people who contributed to this
 * project.
 *
 * This program is free software; you can redistribute it and/or
 * modify it under the terms of the GNU General Public License as
 * published by the Free Software Foundation; either version 2 of
 * the License, or (at your option) any later version.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
 * GNU General Public License for more details.
 *
 * You should have received a copy of the GNU General Public License
 * along with this program; if not, write to the Free Software
 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
 * MA 02111-1307 USA
 */

/*************************************************************************
 * (c) 2005 esd gmbh Hannover
 *
 *
 * from IceCube.h file
 * by Reinhard Arlt [email protected]
 *
 *************************************************************************/

#ifndef __CONFIG_H
#define __CONFIG_H

/*
 * High Level Configuration Options
 * (easy to change)
 */

#define CONFIG_MPC5200		1	/* This is an MPC5xxx CPU */
#define CONFIG_MPC5xxx		1	/* This is an MPC5xxx CPU */
#define CONFIG_ICECUBE		1	/* ... on IceCube board */
#define CONFIG_PF5200		1	/* ... on PF5200  board */
#define CONFIG_MPC5200_DDR	1	/* ... use DDR RAM	*/

#define CONFIG_SYS_MPC5XXX_CLKIN	33000000	/* ... running at 33.000000MHz */

#define BOOTFLAG_COLD		0x01	/* Normal Power-On: Boot from FLASH  */
#define BOOTFLAG_WARM		0x02	/* Software reboot	     */

#define CONFIG_HIGH_BATS	1	/* High BATs supported */
/*
 * Serial console configuration
 */
#define CONFIG_PSC_CONSOLE	1	/* console is on PSC1 */
#if 0				/* test-only */
#define CONFIG_BAUDRATE		115200	/* ... at 115200 bps */
#else
#define CONFIG_BAUDRATE		9600	/* ... at 115200 bps */
#endif
#define CONFIG_SYS_BAUDRATE_TABLE	{ 9600, 19200, 38400, 57600, 115200, 230400 }

#ifdef CONFIG_MPC5200		/* MPC5100 PCI is not supported yet. */
/*
 * PCI Mapping:
 * 0x40000000 - 0x4fffffff - PCI Memory
 * 0x50000000 - 0x50ffffff - PCI IO Space
 */
#define CONFIG_PCI		1
#define CONFIG_PCI_PNP		1
#define CONFIG_PCI_SCAN_SHOW	1
#define CONFIG_PCIAUTO_SKIP_HOST_BRIDGE	1

#define CONFIG_PCI_MEM_BUS	0x40000000
#define CONFIG_PCI_MEM_PHYS	CONFIG_PCI_MEM_BUS
#define CONFIG_PCI_MEM_SIZE	0x10000000

#define CONFIG_PCI_IO_BUS	0x50000000
#define CONFIG_PCI_IO_PHYS	CONFIG_PCI_IO_BUS
#define CONFIG_PCI_IO_SIZE	0x01000000

#define CONFIG_MII		1
#if 0				/* test-only !!! */
#define CONFIG_NET_MULTI	1
#define CONFIG_EEPRO100		1
#define CONFIG_SYS_RX_ETH_BUFFER	8	/* use 8 rx buffer on eepro100	*/
#define CONFIG_NS8382X		1
#endif
#endif

/* Partitions */
#define CONFIG_MAC_PARTITION
#define CONFIG_DOS_PARTITION

/* USB */
#if 0
#define CONFIG_USB_OHCI
#define CONFIG_USB_STORAGE
#endif


/*
 * BOOTP options
 */
#define CONFIG_BOOTP_BOOTFILESIZE
#define CONFIG_BOOTP_BOOTPATH
#define CONFIG_BOOTP_GATEWAY
#define CONFIG_BOOTP_HOSTNAME


/*
 * Command line configuration.
 */
#include <config_cmd_default.h>

#define CONFIG_CMD_BSP
#define CONFIG_CMD_EEPROM
#define CONFIG_CMD_ELF
#define CONFIG_CMD_FAT
#define CONFIG_CMD_I2C
#define CONFIG_CMD_IDE

#ifdef CONFIG_MPC5200
#define CONFIG_CMD_PCI
#endif


#if (TEXT_BASE == 0xFF000000)	/* Boot low with 16 MB Flash */
#   define CONFIG_SYS_LOWBOOT		1
#   define CONFIG_SYS_LOWBOOT16	1
#endif
#if (TEXT_BASE == 0xFF800000)	/* Boot low with  8 MB Flash */
#   define CONFIG_SYS_LOWBOOT		1
#   define CONFIG_SYS_LOWBOOT08	1
#endif

/*
 * Autobooting
 */
#define CONFIG_BOOTDELAY	3	/* autoboot after 5 seconds */

#define CONFIG_PREBOOT	"echo;"	\
	"echo Welcome to ParaFinder pf5200;" \
	"echo"

#undef	CONFIG_BOOTARGS

#define	CONFIG_EXTRA_ENV_SETTINGS \
	"netdev=eth0\0" \
	"flash_vxworks0=run ata_vxworks_args;setenv loadaddr ff000000;bootvx\0" \
	"flash_vxworks1=run ata_vxworks_args;setenv loadaddr ff200000:bootvx\0" \
	"net_vxworks=phypower 1;sleep 2;tftp ${loadaddr} ${image};run vxworks_args;bootvx\0" \
	"vxworks_args=setenv bootargs fec(0,0)${host}:${image} h=${serverip} e=${ipaddr} g=${gatewayip} u=${user} ${pass} tn=${target} s=${script}\0" \
	"ata_vxworks_args=setenv bootargs /ata0/vxWorks h=${serverip} e=${ipaddr} g=${gatewayip} u=${user} ${pass} tn=${target} s=${script} o=fec0 \0" \
	"loadaddr=01000000\0" \
	"serverip=192.168.2.99\0" \
	"gatewayip=10.0.0.79\0" \
	"user=mu\0" \
	"target=pf5200.esd\0" \
	"script=pf5200.bat\0" \
	"image=/tftpboot/vxWorks_pf5200\0" \
	"ipaddr=10.0.13.196\0" \
	"netmask=255.255.0.0\0" \
	""

#define CONFIG_BOOTCOMMAND	"run flash_vxworks0"

#if defined(CONFIG_MPC5200)
/*
 * IPB Bus clocking configuration.
 */
#undef CONFIG_SYS_IPBCLK_EQUALS_XLBCLK		/* define for 133MHz speed */
#endif
/*
 * I2C configuration
 */
#define CONFIG_HARD_I2C		1	/* I2C with hardware support */
#define CONFIG_SYS_I2C_MODULE		2	/* Select I2C module #1 or #2 */

#define CONFIG_SYS_I2C_SPEED		86000	/* 100 kHz */
#define CONFIG_SYS_I2C_SLAVE		0x7F

/*
 * EEPROM configuration
 */
#define CONFIG_SYS_I2C_EEPROM_ADDR		0x50	/* 1010000x */
#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN		2
#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS	5
#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS	20
#define CONFIG_SYS_I2C_MULTI_EEPROMS		1
/*
 * Flash configuration
 */
#define CONFIG_SYS_FLASH_BASE		0xFE000000
#define CONFIG_SYS_FLASH_SIZE		0x02000000
#define CONFIG_ENV_ADDR		(CONFIG_SYS_FLASH_BASE + 0x00000000)
#define CONFIG_SYS_MAX_FLASH_BANKS	1	/* max num of memory banks	*/
#define CONFIG_SYS_MAX_FLASH_SECT	512

#define CONFIG_SYS_FLASH_ERASE_TOUT	240000	/* Flash Erase Timeout (in ms)	*/
#define CONFIG_SYS_FLASH_WRITE_TOUT	500	/* Flash Write Timeout (in ms)	*/

/*
 * Environment settings
 */
#if 1				/* test-only */
#define CONFIG_ENV_IS_IN_FLASH
#define CONFIG_ENV_SIZE		0x10000
#define CONFIG_ENV_SECT_SIZE	0x10000
#define CONFIG_ENV_OVERWRITE	1
#else
#define CONFIG_ENV_IS_IN_EEPROM	1	/* use EEPROM for environment vars */
#define CONFIG_ENV_OFFSET		0x0000	/* environment starts at the beginning of the EEPROM */
#define CONFIG_ENV_SIZE		0x0400	/* 8192 bytes may be used for env vars */
				   /* total size of a CAT24WC32 is 8192 bytes */
#define CONFIG_ENV_OVERWRITE	1
#endif

/*
 * Memory map
 */
#define CONFIG_SYS_MBAR		0xF0000000
#define CONFIG_SYS_SDRAM_BASE		0x00000000
#define CONFIG_SYS_DEFAULT_MBAR	0x80000000

/* Use SRAM until RAM will be available */
#define CONFIG_SYS_INIT_RAM_ADDR	MPC5XXX_SRAM
#define CONFIG_SYS_INIT_RAM_END	MPC5XXX_SRAM_SIZE	/* End of used area in DPRAM */

#define CONFIG_SYS_GBL_DATA_SIZE	128	/* size in bytes reserved for initial data */
#define CONFIG_SYS_GBL_DATA_OFFSET	(CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE)
#define CONFIG_SYS_INIT_SP_OFFSET	CONFIG_SYS_GBL_DATA_OFFSET

#define CONFIG_SYS_MONITOR_BASE    TEXT_BASE
#if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE)
#   define CONFIG_SYS_RAMBOOT		1
#endif

#define CONFIG_SYS_MONITOR_LEN		(192 << 10)	/* Reserve 192 kB for Monitor	*/
#define CONFIG_SYS_MALLOC_LEN		(128 << 10)	/* Reserve 128 kB for malloc()	*/
#define CONFIG_SYS_BOOTMAPSZ		(8 << 20)	/* Initial Memory map for Linux */

/*
 * Ethernet configuration
 */
#define CONFIG_MPC5xxx_FEC	1
/*
 * Define CONFIG_FEC_10MBIT to force FEC at 10Mb
 */
/* #define CONFIG_FEC_10MBIT 1 */
#define CONFIG_PHY_ADDR		0x00
#define CONFIG_UDP_CHECKSUM	1

/*
 * GPIO configuration
 */
#define CONFIG_SYS_GPS_PORT_CONFIG	0x01052444

/*
 * Miscellaneous configurable options
 */
#define CONFIG_SYS_LONGHELP		/* undef to save memory	    */
#define CONFIG_SYS_PROMPT		"=> "	/* Monitor Command Prompt   */
#if defined(CONFIG_CMD_KGDB)
#define CONFIG_SYS_CBSIZE		1024	/* Console I/O Buffer Size  */
#else
#define CONFIG_SYS_CBSIZE		256	/* Console I/O Buffer Size  */
#endif
#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16)	/* Print Buffer Size */
#define CONFIG_SYS_MAXARGS		16	/* max number of command args	*/
#define CONFIG_SYS_BARGSIZE		CONFIG_SYS_CBSIZE	/* Boot Argument Buffer Size	*/

#define CONFIG_SYS_MEMTEST_START	0x00100000	/* memtest works on */
#define CONFIG_SYS_MEMTEST_END		0x00f00000	/* 1 ... 15 MB in DRAM	*/

#define CONFIG_SYS_LOAD_ADDR		0x100000	/* default load address */

#define CONFIG_SYS_HZ			1000	/* decrementer freq: 1 ms ticks */

#define CONFIG_SYS_VXWORKS_MAC_PTR	0x00000000	/* Pass Ethernet MAC to VxWorks */

#define CONFIG_SYS_CACHELINE_SIZE	32	/* For MPC5xxx CPUs */
#if defined(CONFIG_CMD_KGDB)
#  define CONFIG_SYS_CACHELINE_SHIFT	5	/* log base 2 of the above value */
#endif

/*
 * Various low-level settings
 */
#if defined(CONFIG_MPC5200)
#define CONFIG_SYS_HID0_INIT		HID0_ICE | HID0_ICFI
#define CONFIG_SYS_HID0_FINAL		HID0_ICE
#else
#define CONFIG_SYS_HID0_INIT		0
#define CONFIG_SYS_HID0_FINAL		0
#endif

#define CONFIG_SYS_BOOTCS_START	CONFIG_SYS_FLASH_BASE
#define CONFIG_SYS_BOOTCS_SIZE		CONFIG_SYS_FLASH_SIZE
#define CONFIG_SYS_BOOTCS_CFG		0x0004DD00

#define CONFIG_SYS_CS0_START		CONFIG_SYS_FLASH_BASE
#define CONFIG_SYS_CS0_SIZE		CONFIG_SYS_FLASH_SIZE

#define CONFIG_SYS_CS1_START		0xfd000000
#define CONFIG_SYS_CS1_SIZE		0x00010000
#define CONFIG_SYS_CS1_CFG		0x10101410

#define CONFIG_SYS_CS_BURST		0x00000000
#define CONFIG_SYS_CS_DEADCYCLE	0x33333333

#define CONFIG_SYS_RESET_ADDRESS	0xff000000

/*-----------------------------------------------------------------------
 * USB stuff
 *-----------------------------------------------------------------------
 */
#define CONFIG_USB_CLOCK	0x0001BBBB
#define CONFIG_USB_CONFIG	0x00001000

/*-----------------------------------------------------------------------
 * IDE/ATA stuff Supports IDE harddisk
 *-----------------------------------------------------------------------
 */

#undef	CONFIG_IDE_8xx_PCCARD	/* Use IDE with PC Card Adapter */

#undef	CONFIG_IDE_8xx_DIRECT	/* Direct IDE	 not supported	*/
#undef	CONFIG_IDE_LED		/* LED	 for ide not supported	*/

#define	CONFIG_IDE_RESET	/* reset for ide supported	*/
#define CONFIG_IDE_PREINIT

#define CONFIG_SYS_IDE_MAXBUS		1	/* max. 1 IDE bus		*/
#define CONFIG_SYS_IDE_MAXDEVICE	1	/* max. 1 drive per IDE bus	*/

#define CONFIG_SYS_ATA_IDE0_OFFSET	0x0000

#define CONFIG_SYS_ATA_BASE_ADDR	MPC5XXX_ATA

/* Offset for data I/O			*/
#define CONFIG_SYS_ATA_DATA_OFFSET	(0x0060)

/* Offset for normal register accesses	*/
#define CONFIG_SYS_ATA_REG_OFFSET	(CONFIG_SYS_ATA_DATA_OFFSET)

/* Offset for alternate registers	*/
#define CONFIG_SYS_ATA_ALT_OFFSET	(0x005C)

/* Interval between registers						     */
#define CONFIG_SYS_ATA_STRIDE		4

/*-----------------------------------------------------------------------
 * CPLD stuff
 */
#define CONFIG_SYS_FPGA_XC95XL		1	/* using Xilinx XC95XL CPLD	 */
#define CONFIG_SYS_FPGA_MAX_SIZE	32*1024	/* 32kByte is enough for CPLD	 */

/* CPLD program pin configuration */
#define CONFIG_SYS_FPGA_PRG		0x20000000	/* JTAG TMS pin (ppc output)	       */
#define CONFIG_SYS_FPGA_CLK		0x10000000	/* JTAG TCK pin (ppc output)	       */
#define CONFIG_SYS_FPGA_DATA		0x20000000	/* JTAG TDO->TDI data pin (ppc output) */
#define CONFIG_SYS_FPGA_DONE		0x10000000	/* JTAG TDI->TDO pin (ppc input)       */

#define JTAG_GPIO_ADDR_TMS	(CONFIG_SYS_MBAR + 0xB10)	/* JTAG TMS pin (GPS data out value reg.)      */
#define JTAG_GPIO_ADDR_TCK	(CONFIG_SYS_MBAR + 0xC0C)	/* JTAG TCK pin (GPW data out value reg.)      */
#define JTAG_GPIO_ADDR_TDI	(CONFIG_SYS_MBAR + 0xC0C)	/* JTAG TDO->TDI pin (GPW data out value reg.) */
#define JTAG_GPIO_ADDR_TDO	(CONFIG_SYS_MBAR + 0xB14)	/* JTAG TDI->TDO pin (GPS data in value reg.)  */

#define JTAG_GPIO_ADDR_CFG	(CONFIG_SYS_MBAR + 0xB00)
#define JTAG_GPIO_CFG_SET	0x00000000
#define JTAG_GPIO_CFG_RESET	0x00F00000

#define JTAG_GPIO_ADDR_EN_TMS	(CONFIG_SYS_MBAR + 0xB04)
#define JTAG_GPIO_TMS_EN_SET	0x20000000	/* Enable for GPIO */
#define JTAG_GPIO_TMS_EN_RESET	0x00000000
#define JTAG_GPIO_ADDR_DDR_TMS	(CONFIG_SYS_MBAR + 0xB0C)
#define JTAG_GPIO_TMS_DDR_SET	0x20000000	/* Set as output   */
#define JTAG_GPIO_TMS_DDR_RESET 0x00000000

#define JTAG_GPIO_ADDR_EN_TCK	(CONFIG_SYS_MBAR + 0xC00)
#define JTAG_GPIO_TCK_EN_SET	0x20000000	/* Enable for GPIO */
#define JTAG_GPIO_TCK_EN_RESET	0x00000000
#define JTAG_GPIO_ADDR_DDR_TCK	(CONFIG_SYS_MBAR + 0xC08)
#define JTAG_GPIO_TCK_DDR_SET	0x20000000	/* Set as output   */
#define JTAG_GPIO_TCK_DDR_RESET 0x00000000

#define JTAG_GPIO_ADDR_EN_TDI	(CONFIG_SYS_MBAR + 0xC00)
#define JTAG_GPIO_TDI_EN_SET	0x10000000	/* Enable as GPIO  */
#define JTAG_GPIO_TDI_EN_RESET	0x00000000
#define JTAG_GPIO_ADDR_DDR_TDI	(CONFIG_SYS_MBAR + 0xC08)
#define JTAG_GPIO_TDI_DDR_SET	0x10000000	/* Set as output   */
#define JTAG_GPIO_TDI_DDR_RESET 0x00000000

#define JTAG_GPIO_ADDR_EN_TDO	(CONFIG_SYS_MBAR + 0xB04)
#define JTAG_GPIO_TDO_EN_SET	0x10000000	/* Enable as GPIO  */
#define JTAG_GPIO_TDO_EN_RESET	0x00000000
#define JTAG_GPIO_ADDR_DDR_TDO	(CONFIG_SYS_MBAR + 0xB0C)
#define JTAG_GPIO_TDO_DDR_SET	0x00000000
#define JTAG_GPIO_TDO_DDR_RESET 0x10000000	/* Set as input	   */

#endif				/* __CONFIG_H */
Commit	Line	Data
5e4b3361 SR	1	/*
	2	* (C) Copyright 2003-2004
	3	* Wolfgang Denk, DENX Software Engineering, [email protected].
	4	*
	5	* See file CREDITS for list of people who contributed to this
	6	* project.
	7	*
	8	* This program is free software; you can redistribute it and/or
	9	* modify it under the terms of the GNU General Public License as
	10	* published by the Free Software Foundation; either version 2 of
	11	* the License, or (at your option) any later version.
	12	*
	13	* This program is distributed in the hope that it will be useful,
	14	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	15	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	16	* GNU General Public License for more details.
	17	*
	18	* You should have received a copy of the GNU General Public License
	19	* along with this program; if not, write to the Free Software
	20	* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
	21	* MA 02111-1307 USA
	22	*/
	23
	24	/*************************************************************************
	25	* (c) 2005 esd gmbh Hannover
	26	*
	27	*
	28	* from IceCube.h file
	29	* by Reinhard Arlt [email protected]
	30	*
	31	*************************************************************************/
	32
	33	#ifndef __CONFIG_H
	34	#define __CONFIG_H
	35
	36	/*
	37	* High Level Configuration Options
	38	* (easy to change)
	39	*/
	40
	41	#define CONFIG_MPC5200 1 /* This is an MPC5xxx CPU */
	42	#define CONFIG_MPC5xxx 1 /* This is an MPC5xxx CPU */
	43	#define CONFIG_ICECUBE 1 /* ... on IceCube board */
	44	#define CONFIG_PF5200 1 /* ... on PF5200 board */
	45	#define CONFIG_MPC5200_DDR 1 /* ... use DDR RAM */
	46
6d0f6bcf	47	#define CONFIG_SYS_MPC5XXX_CLKIN 33000000 /* ... running at 33.000000MHz */
5e4b3361 SR	48
	49	#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */
	50	#define BOOTFLAG_WARM 0x02 /* Software reboot */
	51
31d82672	52	#define CONFIG_HIGH_BATS 1 /* High BATs supported */
5e4b3361 SR	53	/*
	54	* Serial console configuration
	55	*/
	56	#define CONFIG_PSC_CONSOLE 1 /* console is on PSC1 */
	57	#if 0 /* test-only */
	58	#define CONFIG_BAUDRATE 115200 /* ... at 115200 bps */
	59	#else
	60	#define CONFIG_BAUDRATE 9600 /* ... at 115200 bps */
	61	#endif
6d0f6bcf	62	#define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200, 230400 }
5e4b3361 SR	63
	64	#ifdef CONFIG_MPC5200 /* MPC5100 PCI is not supported yet. */
	65	/*
	66	* PCI Mapping:
	67	* 0x40000000 - 0x4fffffff - PCI Memory
	68	* 0x50000000 - 0x50ffffff - PCI IO Space
	69	*/
	70	#define CONFIG_PCI 1
	71	#define CONFIG_PCI_PNP 1
	72	#define CONFIG_PCI_SCAN_SHOW 1
f33fca22	73	#define CONFIG_PCIAUTO_SKIP_HOST_BRIDGE 1
5e4b3361 SR	74
	75	#define CONFIG_PCI_MEM_BUS 0x40000000
	76	#define CONFIG_PCI_MEM_PHYS CONFIG_PCI_MEM_BUS
	77	#define CONFIG_PCI_MEM_SIZE 0x10000000
	78
	79	#define CONFIG_PCI_IO_BUS 0x50000000
	80	#define CONFIG_PCI_IO_PHYS CONFIG_PCI_IO_BUS
	81	#define CONFIG_PCI_IO_SIZE 0x01000000
	82
63ff004c	83	#define CONFIG_MII 1
5e4b3361 SR	84	#if 0 /* test-only !!! */
	85	#define CONFIG_NET_MULTI 1
	86	#define CONFIG_EEPRO100 1
6d0f6bcf	87	#define CONFIG_SYS_RX_ETH_BUFFER 8 /* use 8 rx buffer on eepro100 */
5e4b3361 SR	88	#define CONFIG_NS8382X 1
5e4b3361 SR	89	#endif
5e4b3361 SR	90	#endif
	91
	92	/* Partitions */
	93	#define CONFIG_MAC_PARTITION
	94	#define CONFIG_DOS_PARTITION
	95
	96	/* USB */
	97	#if 0
	98	#define CONFIG_USB_OHCI
5e4b3361	99	#define CONFIG_USB_STORAGE
5e4b3361 SR	100	#endif
5e4b3361 SR	101
d794cfef	102
079a136c JL	103	/*
	104	* BOOTP options
	105	*/
	106	#define CONFIG_BOOTP_BOOTFILESIZE
	107	#define CONFIG_BOOTP_BOOTPATH
	108	#define CONFIG_BOOTP_GATEWAY
	109	#define CONFIG_BOOTP_HOSTNAME
	110
	111
5e4b3361	112	/*
d794cfef	113	* Command line configuration.
5e4b3361	114	*/
d794cfef JL	115	#include <config_cmd_default.h>
	116
	117	#define CONFIG_CMD_BSP
d794cfef JL	118	#define CONFIG_CMD_EEPROM
	119	#define CONFIG_CMD_ELF
	120	#define CONFIG_CMD_FAT
	121	#define CONFIG_CMD_I2C
	122	#define CONFIG_CMD_IDE
	123
079a136c JL	124	#ifdef CONFIG_MPC5200
	125	#define CONFIG_CMD_PCI
	126	#endif
	127
5e4b3361 SR	128
5e4b3361 SR	129	#if (TEXT_BASE == 0xFF000000) /* Boot low with 16 MB Flash */
6d0f6bcf JCPV	130	# define CONFIG_SYS_LOWBOOT 1
6d0f6bcf JCPV	131	# define CONFIG_SYS_LOWBOOT16 1
5e4b3361 SR	132	#endif
5e4b3361 SR	133	#if (TEXT_BASE == 0xFF800000) /* Boot low with 8 MB Flash */
6d0f6bcf JCPV	134	# define CONFIG_SYS_LOWBOOT 1
6d0f6bcf JCPV	135	# define CONFIG_SYS_LOWBOOT08 1
5e4b3361 SR	136	#endif
	137
	138	/*
	139	* Autobooting
	140	*/
	141	#define CONFIG_BOOTDELAY 3 /* autoboot after 5 seconds */
	142
	143	#define CONFIG_PREBOOT "echo;" \
	144	"echo Welcome to ParaFinder pf5200;" \
	145	"echo"
	146
	147	#undef CONFIG_BOOTARGS
	148
	149	#define CONFIG_EXTRA_ENV_SETTINGS \
	150	"netdev=eth0\0" \
	151	"flash_vxworks0=run ata_vxworks_args;setenv loadaddr ff000000;bootvx\0" \
	152	"flash_vxworks1=run ata_vxworks_args;setenv loadaddr ff200000:bootvx\0" \
fe126d8b WD	153	"net_vxworks=phypower 1;sleep 2;tftp ${loadaddr} ${image};run vxworks_args;bootvx\0" \
	154	"vxworks_args=setenv bootargs fec(0,0)${host}:${image} h=${serverip} e=${ipaddr} g=${gatewayip} u=${user} ${pass} tn=${target} s=${script}\0" \
	155	"ata_vxworks_args=setenv bootargs /ata0/vxWorks h=${serverip} e=${ipaddr} g=${gatewayip} u=${user} ${pass} tn=${target} s=${script} o=fec0 \0" \
5e4b3361 SR	156	"loadaddr=01000000\0" \
	157	"serverip=192.168.2.99\0" \
	158	"gatewayip=10.0.0.79\0" \
	159	"user=mu\0" \
	160	"target=pf5200.esd\0" \
	161	"script=pf5200.bat\0" \
	162	"image=/tftpboot/vxWorks_pf5200\0" \
	163	"ipaddr=10.0.13.196\0" \
	164	"netmask=255.255.0.0\0" \
	165	""
	166
	167	#define CONFIG_BOOTCOMMAND "run flash_vxworks0"
	168
	169	#if defined(CONFIG_MPC5200)
	170	/*
	171	* IPB Bus clocking configuration.
	172	*/
6d0f6bcf	173	#undef CONFIG_SYS_IPBCLK_EQUALS_XLBCLK /* define for 133MHz speed */
5e4b3361 SR	174	#endif
	175	/*
	176	* I2C configuration
	177	*/
	178	#define CONFIG_HARD_I2C 1 /* I2C with hardware support */
6d0f6bcf	179	#define CONFIG_SYS_I2C_MODULE 2 /* Select I2C module #1 or #2 */
5e4b3361	180
6d0f6bcf JCPV	181	#define CONFIG_SYS_I2C_SPEED 86000 /* 100 kHz */
6d0f6bcf JCPV	182	#define CONFIG_SYS_I2C_SLAVE 0x7F
5e4b3361 SR	183
	184	/*
	185	* EEPROM configuration
	186	*/
6d0f6bcf JCPV	187	#define CONFIG_SYS_I2C_EEPROM_ADDR 0x50 /* 1010000x */
	188	#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2
	189	#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 5
	190	#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 20
	191	#define CONFIG_SYS_I2C_MULTI_EEPROMS 1
5e4b3361 SR	192	/*
	193	* Flash configuration
	194	*/
6d0f6bcf JCPV	195	#define CONFIG_SYS_FLASH_BASE 0xFE000000
	196	#define CONFIG_SYS_FLASH_SIZE 0x02000000
	197	#define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + 0x00000000)
	198	#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max num of memory banks */
	199	#define CONFIG_SYS_MAX_FLASH_SECT 512
5e4b3361	200
6d0f6bcf JCPV	201	#define CONFIG_SYS_FLASH_ERASE_TOUT 240000 /* Flash Erase Timeout (in ms) */
6d0f6bcf JCPV	202	#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (in ms) */
5e4b3361 SR	203
	204	/*
	205	* Environment settings
	206	*/
	207	#if 1 /* test-only */
5a1aceb0	208	#define CONFIG_ENV_IS_IN_FLASH
0e8d1586 JCPV	209	#define CONFIG_ENV_SIZE 0x10000
0e8d1586 JCPV	210	#define CONFIG_ENV_SECT_SIZE 0x10000
5e4b3361 SR	211	#define CONFIG_ENV_OVERWRITE 1
5e4b3361 SR	212	#else
bb1f8b4f	213	#define CONFIG_ENV_IS_IN_EEPROM 1 /* use EEPROM for environment vars */
0e8d1586 JCPV	214	#define CONFIG_ENV_OFFSET 0x0000 /* environment starts at the beginning of the EEPROM */
0e8d1586 JCPV	215	#define CONFIG_ENV_SIZE 0x0400 /* 8192 bytes may be used for env vars */
5e4b3361 SR	216	/* total size of a CAT24WC32 is 8192 bytes */
	217	#define CONFIG_ENV_OVERWRITE 1
	218	#endif
	219
	220	/*
	221	* Memory map
	222	*/
6d0f6bcf JCPV	223	#define CONFIG_SYS_MBAR 0xF0000000
	224	#define CONFIG_SYS_SDRAM_BASE 0x00000000
	225	#define CONFIG_SYS_DEFAULT_MBAR 0x80000000
5e4b3361 SR	226
5e4b3361 SR	227	/* Use SRAM until RAM will be available */
6d0f6bcf JCPV	228	#define CONFIG_SYS_INIT_RAM_ADDR MPC5XXX_SRAM
6d0f6bcf JCPV	229	#define CONFIG_SYS_INIT_RAM_END MPC5XXX_SRAM_SIZE /* End of used area in DPRAM */
5e4b3361	230
6d0f6bcf JCPV	231	#define CONFIG_SYS_GBL_DATA_SIZE 128 /* size in bytes reserved for initial data */
	232	#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE)
	233	#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
5e4b3361	234
6d0f6bcf JCPV	235	#define CONFIG_SYS_MONITOR_BASE TEXT_BASE
	236	#if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE)
	237	# define CONFIG_SYS_RAMBOOT 1
5e4b3361 SR	238	#endif
5e4b3361 SR	239
6d0f6bcf JCPV	240	#define CONFIG_SYS_MONITOR_LEN (192 << 10) /* Reserve 192 kB for Monitor */
	241	#define CONFIG_SYS_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */
	242	#define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
5e4b3361 SR	243
	244	/*
	245	* Ethernet configuration
	246	*/
	247	#define CONFIG_MPC5xxx_FEC 1
	248	/*
	249	* Define CONFIG_FEC_10MBIT to force FEC at 10Mb
	250	*/
	251	/* #define CONFIG_FEC_10MBIT 1 */
	252	#define CONFIG_PHY_ADDR 0x00
	253	#define CONFIG_UDP_CHECKSUM 1
	254
	255	/*
	256	* GPIO configuration
	257	*/
6d0f6bcf	258	#define CONFIG_SYS_GPS_PORT_CONFIG 0x01052444
5e4b3361 SR	259
	260	/*
	261	* Miscellaneous configurable options
	262	*/
6d0f6bcf JCPV	263	#define CONFIG_SYS_LONGHELP /* undef to save memory */
6d0f6bcf JCPV	264	#define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */
d794cfef	265	#if defined(CONFIG_CMD_KGDB)
6d0f6bcf	266	#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
5e4b3361	267	#else
6d0f6bcf	268	#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
5e4b3361	269	#endif
6d0f6bcf JCPV	270	#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
	271	#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
	272	#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
5e4b3361	273
6d0f6bcf JCPV	274	#define CONFIG_SYS_MEMTEST_START 0x00100000 /* memtest works on */
6d0f6bcf JCPV	275	#define CONFIG_SYS_MEMTEST_END 0x00f00000 /* 1 ... 15 MB in DRAM */
5e4b3361	276
6d0f6bcf	277	#define CONFIG_SYS_LOAD_ADDR 0x100000 /* default load address */
5e4b3361	278
6d0f6bcf	279	#define CONFIG_SYS_HZ 1000 /* decrementer freq: 1 ms ticks */
5e4b3361	280
6d0f6bcf	281	#define CONFIG_SYS_VXWORKS_MAC_PTR 0x00000000 /* Pass Ethernet MAC to VxWorks */
5e4b3361	282
6d0f6bcf	283	#define CONFIG_SYS_CACHELINE_SIZE 32 /* For MPC5xxx CPUs */
d794cfef	284	#if defined(CONFIG_CMD_KGDB)
6d0f6bcf	285	# define CONFIG_SYS_CACHELINE_SHIFT 5 /* log base 2 of the above value */
d794cfef JL	286	#endif
d794cfef JL	287
5e4b3361 SR	288	/*
	289	* Various low-level settings
	290	*/
	291	#if defined(CONFIG_MPC5200)
6d0f6bcf JCPV	292	#define CONFIG_SYS_HID0_INIT HID0_ICE \| HID0_ICFI
6d0f6bcf JCPV	293	#define CONFIG_SYS_HID0_FINAL HID0_ICE
5e4b3361	294	#else
6d0f6bcf JCPV	295	#define CONFIG_SYS_HID0_INIT 0
6d0f6bcf JCPV	296	#define CONFIG_SYS_HID0_FINAL 0
5e4b3361 SR	297	#endif
5e4b3361 SR	298
6d0f6bcf JCPV	299	#define CONFIG_SYS_BOOTCS_START CONFIG_SYS_FLASH_BASE
	300	#define CONFIG_SYS_BOOTCS_SIZE CONFIG_SYS_FLASH_SIZE
	301	#define CONFIG_SYS_BOOTCS_CFG 0x0004DD00
5e4b3361	302
6d0f6bcf JCPV	303	#define CONFIG_SYS_CS0_START CONFIG_SYS_FLASH_BASE
6d0f6bcf JCPV	304	#define CONFIG_SYS_CS0_SIZE CONFIG_SYS_FLASH_SIZE
5e4b3361	305
6d0f6bcf JCPV	306	#define CONFIG_SYS_CS1_START 0xfd000000
	307	#define CONFIG_SYS_CS1_SIZE 0x00010000
	308	#define CONFIG_SYS_CS1_CFG 0x10101410
5e4b3361	309
6d0f6bcf JCPV	310	#define CONFIG_SYS_CS_BURST 0x00000000
6d0f6bcf JCPV	311	#define CONFIG_SYS_CS_DEADCYCLE 0x33333333
5e4b3361	312
6d0f6bcf	313	#define CONFIG_SYS_RESET_ADDRESS 0xff000000
5e4b3361 SR	314
	315	/*-----------------------------------------------------------------------
	316	* USB stuff
	317	*-----------------------------------------------------------------------
	318	*/
	319	#define CONFIG_USB_CLOCK 0x0001BBBB
	320	#define CONFIG_USB_CONFIG 0x00001000
	321
	322	/*-----------------------------------------------------------------------
	323	* IDE/ATA stuff Supports IDE harddisk
	324	*-----------------------------------------------------------------------
	325	*/
	326
	327	#undef CONFIG_IDE_8xx_PCCARD /* Use IDE with PC Card Adapter */
	328
	329	#undef CONFIG_IDE_8xx_DIRECT /* Direct IDE not supported */
	330	#undef CONFIG_IDE_LED /* LED for ide not supported */
	331
	332	#define CONFIG_IDE_RESET /* reset for ide supported */
	333	#define CONFIG_IDE_PREINIT
	334
6d0f6bcf JCPV	335	#define CONFIG_SYS_IDE_MAXBUS 1 /* max. 1 IDE bus */
6d0f6bcf JCPV	336	#define CONFIG_SYS_IDE_MAXDEVICE 1 /* max. 1 drive per IDE bus */
5e4b3361	337
6d0f6bcf	338	#define CONFIG_SYS_ATA_IDE0_OFFSET 0x0000
5e4b3361	339
6d0f6bcf	340	#define CONFIG_SYS_ATA_BASE_ADDR MPC5XXX_ATA
5e4b3361 SR	341
5e4b3361 SR	342	/* Offset for data I/O */
6d0f6bcf	343	#define CONFIG_SYS_ATA_DATA_OFFSET (0x0060)
5e4b3361 SR	344
5e4b3361 SR	345	/* Offset for normal register accesses */
6d0f6bcf	346	#define CONFIG_SYS_ATA_REG_OFFSET (CONFIG_SYS_ATA_DATA_OFFSET)
5e4b3361 SR	347
5e4b3361 SR	348	/* Offset for alternate registers */
6d0f6bcf	349	#define CONFIG_SYS_ATA_ALT_OFFSET (0x005C)
5e4b3361 SR	350
5e4b3361 SR	351	/* Interval between registers */
6d0f6bcf	352	#define CONFIG_SYS_ATA_STRIDE 4
5e4b3361 SR	353
	354	/*-----------------------------------------------------------------------
	355	* CPLD stuff
	356	*/
6d0f6bcf JCPV	357	#define CONFIG_SYS_FPGA_XC95XL 1 /* using Xilinx XC95XL CPLD */
6d0f6bcf JCPV	358	#define CONFIG_SYS_FPGA_MAX_SIZE 321024 / 32kByte is enough for CPLD */
5e4b3361 SR	359
5e4b3361 SR	360	/* CPLD program pin configuration */
6d0f6bcf JCPV	361	#define CONFIG_SYS_FPGA_PRG 0x20000000 /* JTAG TMS pin (ppc output) */
	362	#define CONFIG_SYS_FPGA_CLK 0x10000000 /* JTAG TCK pin (ppc output) */
	363	#define CONFIG_SYS_FPGA_DATA 0x20000000 /* JTAG TDO->TDI data pin (ppc output) */
	364	#define CONFIG_SYS_FPGA_DONE 0x10000000 /* JTAG TDI->TDO pin (ppc input) */
5e4b3361	365
6d0f6bcf JCPV	366	#define JTAG_GPIO_ADDR_TMS (CONFIG_SYS_MBAR + 0xB10) /* JTAG TMS pin (GPS data out value reg.) */
	367	#define JTAG_GPIO_ADDR_TCK (CONFIG_SYS_MBAR + 0xC0C) /* JTAG TCK pin (GPW data out value reg.) */
	368	#define JTAG_GPIO_ADDR_TDI (CONFIG_SYS_MBAR + 0xC0C) /* JTAG TDO->TDI pin (GPW data out value reg.) */
	369	#define JTAG_GPIO_ADDR_TDO (CONFIG_SYS_MBAR + 0xB14) /* JTAG TDI->TDO pin (GPS data in value reg.) */
5e4b3361	370
6d0f6bcf	371	#define JTAG_GPIO_ADDR_CFG (CONFIG_SYS_MBAR + 0xB00)
5e4b3361 SR	372	#define JTAG_GPIO_CFG_SET 0x00000000
	373	#define JTAG_GPIO_CFG_RESET 0x00F00000
	374
6d0f6bcf	375	#define JTAG_GPIO_ADDR_EN_TMS (CONFIG_SYS_MBAR + 0xB04)
5e4b3361 SR	376	#define JTAG_GPIO_TMS_EN_SET 0x20000000 /* Enable for GPIO */
5e4b3361 SR	377	#define JTAG_GPIO_TMS_EN_RESET 0x00000000
6d0f6bcf	378	#define JTAG_GPIO_ADDR_DDR_TMS (CONFIG_SYS_MBAR + 0xB0C)
5e4b3361 SR	379	#define JTAG_GPIO_TMS_DDR_SET 0x20000000 /* Set as output */
	380	#define JTAG_GPIO_TMS_DDR_RESET 0x00000000
	381
6d0f6bcf	382	#define JTAG_GPIO_ADDR_EN_TCK (CONFIG_SYS_MBAR + 0xC00)
5e4b3361 SR	383	#define JTAG_GPIO_TCK_EN_SET 0x20000000 /* Enable for GPIO */
5e4b3361 SR	384	#define JTAG_GPIO_TCK_EN_RESET 0x00000000
6d0f6bcf	385	#define JTAG_GPIO_ADDR_DDR_TCK (CONFIG_SYS_MBAR + 0xC08)
5e4b3361 SR	386	#define JTAG_GPIO_TCK_DDR_SET 0x20000000 /* Set as output */
	387	#define JTAG_GPIO_TCK_DDR_RESET 0x00000000
	388
6d0f6bcf	389	#define JTAG_GPIO_ADDR_EN_TDI (CONFIG_SYS_MBAR + 0xC00)
5e4b3361 SR	390	#define JTAG_GPIO_TDI_EN_SET 0x10000000 /* Enable as GPIO */
5e4b3361 SR	391	#define JTAG_GPIO_TDI_EN_RESET 0x00000000
6d0f6bcf	392	#define JTAG_GPIO_ADDR_DDR_TDI (CONFIG_SYS_MBAR + 0xC08)
5e4b3361 SR	393	#define JTAG_GPIO_TDI_DDR_SET 0x10000000 /* Set as output */
	394	#define JTAG_GPIO_TDI_DDR_RESET 0x00000000
	395
6d0f6bcf	396	#define JTAG_GPIO_ADDR_EN_TDO (CONFIG_SYS_MBAR + 0xB04)
5e4b3361 SR	397	#define JTAG_GPIO_TDO_EN_SET 0x10000000 /* Enable as GPIO */
5e4b3361 SR	398	#define JTAG_GPIO_TDO_EN_RESET 0x00000000
6d0f6bcf	399	#define JTAG_GPIO_ADDR_DDR_TDO (CONFIG_SYS_MBAR + 0xB0C)
5e4b3361 SR	400	#define JTAG_GPIO_TDO_DDR_SET 0x00000000
	401	#define JTAG_GPIO_TDO_DDR_RESET 0x10000000 /* Set as input */
	402
	403	#endif /* __CONFIG_H */