[J-u-boot.git] / include / configs / actux1.h

/*
 * (C) Copyright 2007
 * Michael Schwingen, [email protected]
 *
 * Configuration settings for the AcTux-1 board.
 *
 * See file CREDITS for list of people who contributed to this
 * project.
 *
 * This program is free software; you can redistribute it and/or
 * modify it under the terms of the GNU General Public License as
 * published by the Free Software Foundation; either version 2 of
 * the License, or (at your option) any later version.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
 * GNU General Public License for more details.
 *
 * You should have received a copy of the GNU General Public License
 * along with this program; if not, write to the Free Software
 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
 * MA 02111-1307 USA
 */

#ifndef __CONFIG_H
#define __CONFIG_H

/* 1: modified board with 32MB DRAM */
#define CONFIG_ACTUX1_32MB		0
/* 1: 2*2MB FLASH (standard) */
#define CONFIG_ACTUX1_FLASH2X2		1
/* 1: 1*8MB FLASH (upgraded boards) */
#define CONFIG_ACTUX1_FLASH1X8		0

#define CONFIG_IXP425			1
#define CONFIG_ACTUX1			1

#define CONFIG_DISPLAY_CPUINFO		1
#define CONFIG_DISPLAY_BOARDINFO	1

#define CONFIG_SYS_IXP425_CONSOLE		IXP425_UART2
#define CONFIG_BAUDRATE			115200
#define CONFIG_BOOTDELAY		3
#define CONFIG_ZERO_BOOTDELAY_CHECK	/* check for keypress on bootdelay==0 */

/***************************************************************
 * U-boot generic defines start here.
 ***************************************************************/
#undef CONFIG_USE_IRQ

/*
 * Size of malloc() pool
 */
#define CONFIG_SYS_MALLOC_LEN			(CONFIG_ENV_SIZE + 128*1024)
/* size in bytes reserved for initial data */
#define CONFIG_SYS_GBL_DATA_SIZE		128

/* allow to overwrite serial and ethaddr */
#define CONFIG_ENV_OVERWRITE

/* Command line configuration. */
#include <config_cmd_default.h>

#define CONFIG_CMD_ELF
#undef CONFIG_CMD_PCI
#undef CONFIG_PCI

#define CONFIG_BOOTCOMMAND		"run boot_flash"
/* enable passing of ATAGs */
#define CONFIG_CMDLINE_TAG		1
#define CONFIG_SETUP_MEMORY_TAGS	1
#define CONFIG_INITRD_TAG		1
#define CONFIG_REVISION_TAG		1

#if defined(CONFIG_CMD_KGDB)
# define CONFIG_KGDB_BAUDRATE		230400
/* which serial port to use */
# define CONFIG_KGDB_SER_INDEX		1
#endif

/* Miscellaneous configurable options */
#define CONFIG_SYS_LONGHELP
#define CONFIG_SYS_PROMPT			"=> "
/* Console I/O Buffer Size */
#define CONFIG_SYS_CBSIZE			256
/* Print Buffer Size */
#define CONFIG_SYS_PBSIZE			(CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16)
/* max number of command args */
#define CONFIG_SYS_MAXARGS			16
/* Boot Argument Buffer Size */
#define CONFIG_SYS_BARGSIZE			CONFIG_SYS_CBSIZE

#define CONFIG_SYS_MEMTEST_START		0x00400000
#define CONFIG_SYS_MEMTEST_END			0x00800000

/* everything, incl board info, in Hz */
#undef  CONFIG_SYS_CLKS_IN_HZ
/* spec says 66.666 MHz, but it appears to be 33 */
#define CONFIG_SYS_HZ				3333333

/* default load address */
#define CONFIG_SYS_LOAD_ADDR			0x00010000

/* valid baudrates */
#define CONFIG_SYS_BAUDRATE_TABLE		{ 9600, 19200, 38400, 57600,	\
					  115200, 230400 }
#define CONFIG_SERIAL_RTS_ACTIVE	1

/*
 * Stack sizes
 * The stack sizes are set up in start.S using the settings below
 */
#define CONFIG_STACKSIZE		(128*1024)	/* regular stack */
#ifdef CONFIG_USE_IRQ
# define CONFIG_STACKSIZE_IRQ		(4*1024)	/* IRQ stack */
# define CONFIG_STACKSIZE_FIQ		(4*1024)	/* FIQ stack */
#endif

/* Expansion bus settings */
#define CONFIG_SYS_EXP_CS0			0xbd113842

/* SDRAM settings */
#define CONFIG_NR_DRAM_BANKS		1
#define PHYS_SDRAM_1			0x00000000
#define CONFIG_SYS_DRAM_BASE			0x00000000

#if CONFIG_ACTUX1_32MB
# define CONFIG_SYS_SDR_CONFIG			0x18
# define PHYS_SDRAM_1_SIZE		0x02000000
# define CONFIG_SYS_SDRAM_REFRESH_CNT		0x81a
# define CONFIG_SYS_SDR_MODE_CONFIG		0x1
# define CONFIG_SYS_DRAM_SIZE			0x02000000
#else /* 16MB SDRAM */
# define CONFIG_SYS_SDR_CONFIG			0x3A
# define PHYS_SDRAM_1_SIZE		0x01000000
# define CONFIG_SYS_SDRAM_REFRESH_CNT		0x81a
# define CONFIG_SYS_SDR_MODE_CONFIG		0x1
# define CONFIG_SYS_DRAM_SIZE			0x01000000
#endif

/* FLASH organization */
#if CONFIG_ACTUX1_FLASH2X2
# define CONFIG_SYS_MAX_FLASH_BANKS		2
/* max number of sectors on one chip */
# define CONFIG_SYS_MAX_FLASH_SECT		40
# define PHYS_FLASH_1			0x50000000
# define PHYS_FLASH_2			0x50200000
# define CONFIG_SYS_FLASH_BANKS_LIST		{ PHYS_FLASH_1, PHYS_FLASH_2 }
#endif
#if CONFIG_ACTUX1_FLASH1X8
# define CONFIG_SYS_MAX_FLASH_BANKS		1
/* max number of sectors on one chip */
# define CONFIG_SYS_MAX_FLASH_SECT		140
# define PHYS_FLASH_1			0x50000000
# define CONFIG_SYS_FLASH_BANKS_LIST		{ PHYS_FLASH_1 }
#endif

#define CONFIG_SYS_FLASH_BASE			PHYS_FLASH_1
#define CONFIG_SYS_MONITOR_BASE		PHYS_FLASH_1
#define CONFIG_SYS_MONITOR_LEN			(256 << 10)

/* Use common CFI driver */
#define CONFIG_SYS_FLASH_CFI
#define CONFIG_FLASH_CFI_DRIVER
/* no byte writes on IXP4xx */
#define CONFIG_SYS_FLASH_CFI_WIDTH		FLASH_CFI_16BIT
/* print 'E' for empty sector on flinfo */
#define CONFIG_SYS_FLASH_EMPTY_INFO

/* Ethernet */

/* include IXP4xx NPE support */
#define CONFIG_IXP4XX_NPE		1
/* use separate flash sector with ucode images */
#define CONFIG_IXP4XX_NPE_EXT_UCODE_BASE	0x50040000
#define CONFIG_NET_MULTI		1
/* NPE0 PHY address */
#define	CONFIG_PHY_ADDR			0
/* MII PHY management */
#define CONFIG_MII			1
/* Number of ethernet rx buffers & descriptors */
#define CONFIG_SYS_RX_ETH_BUFFER		16
#define CONFIG_RESET_PHY_R		1

#define CONFIG_CMD_DHCP
#define CONFIG_CMD_NET
#define CONFIG_CMD_MII
#define CONFIG_CMD_PING
#undef  CONFIG_CMD_NFS

/* BOOTP options */
#define CONFIG_BOOTP_BOOTFILESIZE
#define CONFIG_BOOTP_BOOTPATH
#define CONFIG_BOOTP_GATEWAY
#define CONFIG_BOOTP_HOSTNAME

/* Cache Configuration */
#define CONFIG_SYS_CACHELINE_SIZE		32

/*
 * environment organization:
 * one flash sector, embedded in uboot area (bottom bootblock flash)
 */
#define	CONFIG_ENV_IS_IN_FLASH		1
#define CONFIG_ENV_SIZE			0x2000
#define CONFIG_ENV_ADDR			(PHYS_FLASH_1 + 0x4000)
#define CONFIG_SYS_USE_PPCENV			1

#define CONFIG_EXTRA_ENV_SETTINGS \
	"mtd=IXP4XX-Flash.0:256k(uboot),64k(ucode),1152k(linux),-(root)\0" \
	"kerneladdr=50050000\0"						\
	"rootaddr=50170000\0"						\
	"loadaddr=10000\0"						\
	"updateboot_ser=mw.b 10000 ff 40000;"				\
	" loady ${loadaddr};"						\
	" run eraseboot writeboot\0"					\
	"updateboot_net=mw.b 10000 ff 40000;"				\
	" tftp ${loadaddr} u-boot.bin;"					\
	" run eraseboot writeboot\0"					\
	"eraseboot=protect off 50000000 50003fff;"			\
	" protect off 50006000 5003ffff;"				\
	" erase 50000000 50003fff;"					\
	" erase 50006000 5003ffff\0"					\
	"writeboot=cp.b 10000 50000000 4000;"				\
	" cp.b 16000 50006000 3a000\0"					\
	"eraseenv=protect off 50004000 50005fff;"			\
	" erase 50004000 50005fff\0"					\
	"updateroot=tftp ${loadaddr} ${rootfile};"			\
	" era ${rootaddr} +${filesize};"				\
	" cp.b ${loadaddr} ${rootaddr} ${filesize}\0"			\
	"updatekern=tftp ${loadaddr} ${kernelfile};"			\
	" era ${kerneladdr} +${filesize};"				\
	" cp.b ${loadaddr} ${kerneladdr} ${filesize}\0"			\
	"flashargs=setenv bootargs mtdparts=${mtd} root=/dev/mtdblock3"	\
	" rootfstype=squashfs,jffs2 init=/etc/preinit\0"		\
	"netargs=setenv bootargs mtdparts=${mtd} root=/dev/mtdblock3"	\
	" rootfstype=squashfs,jffs2 init=/etc/preinit\0"		\
	"addtty=setenv bootargs ${bootargs} console=ttyS0,${baudrate}\0" \
	"addeth=setenv bootargs ${bootargs} ethaddr=${ethaddr}\0"	\
	"boot_flash=run flashargs addtty addeth;"			\
	" bootm ${kerneladdr}\0"					\
	"boot_net=run netargs addtty addeth;"				\
	" tftpboot ${loadaddr} ${kernelfile};"				\
	" bootm\0"

#endif /* __CONFIG_H */
Commit	Line	Data
ea99e8f0 MS	1	/*
	2	* (C) Copyright 2007
	3	* Michael Schwingen, [email protected]
	4	*
	5	* Configuration settings for the AcTux-1 board.
	6	*
	7	* See file CREDITS for list of people who contributed to this
	8	* project.
	9	*
	10	* This program is free software; you can redistribute it and/or
	11	* modify it under the terms of the GNU General Public License as
	12	* published by the Free Software Foundation; either version 2 of
	13	* the License, or (at your option) any later version.
	14	*
	15	* This program is distributed in the hope that it will be useful,
	16	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	17	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	18	* GNU General Public License for more details.
	19	*
	20	* You should have received a copy of the GNU General Public License
	21	* along with this program; if not, write to the Free Software
	22	* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
	23	* MA 02111-1307 USA
	24	*/
	25
	26	#ifndef __CONFIG_H
	27	#define __CONFIG_H
	28
	29	/* 1: modified board with 32MB DRAM */
	30	#define CONFIG_ACTUX1_32MB 0
	31	/* 1: 22MB FLASH (standard) /
	32	#define CONFIG_ACTUX1_FLASH2X2 1
	33	/* 1: 18MB FLASH (upgraded boards) /
	34	#define CONFIG_ACTUX1_FLASH1X8 0
	35
	36	#define CONFIG_IXP425 1
	37	#define CONFIG_ACTUX1 1
	38
	39	#define CONFIG_DISPLAY_CPUINFO 1
	40	#define CONFIG_DISPLAY_BOARDINFO 1
	41
6d0f6bcf	42	#define CONFIG_SYS_IXP425_CONSOLE IXP425_UART2
ea99e8f0 MS	43	#define CONFIG_BAUDRATE 115200
	44	#define CONFIG_BOOTDELAY 3
	45	#define CONFIG_ZERO_BOOTDELAY_CHECK /* check for keypress on bootdelay==0 */
	46
	47	/***************************************************************
	48	* U-boot generic defines start here.
	49	***************************************************************/
	50	#undef CONFIG_USE_IRQ
	51
	52	/*
	53	* Size of malloc() pool
	54	*/
6d0f6bcf	55	#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + 128*1024)
ea99e8f0	56	/* size in bytes reserved for initial data */
6d0f6bcf	57	#define CONFIG_SYS_GBL_DATA_SIZE 128
ea99e8f0 MS	58
	59	/* allow to overwrite serial and ethaddr */
	60	#define CONFIG_ENV_OVERWRITE
	61
	62	/* Command line configuration. */
	63	#include <config_cmd_default.h>
	64
	65	#define CONFIG_CMD_ELF
	66	#undef CONFIG_CMD_PCI
	67	#undef CONFIG_PCI
	68
	69	#define CONFIG_BOOTCOMMAND "run boot_flash"
	70	/* enable passing of ATAGs */
	71	#define CONFIG_CMDLINE_TAG 1
	72	#define CONFIG_SETUP_MEMORY_TAGS 1
	73	#define CONFIG_INITRD_TAG 1
	74	#define CONFIG_REVISION_TAG 1
	75
	76	#if defined(CONFIG_CMD_KGDB)
	77	# define CONFIG_KGDB_BAUDRATE 230400
	78	/* which serial port to use */
	79	# define CONFIG_KGDB_SER_INDEX 1
	80	#endif
	81
	82	/* Miscellaneous configurable options */
6d0f6bcf JCPV	83	#define CONFIG_SYS_LONGHELP
6d0f6bcf JCPV	84	#define CONFIG_SYS_PROMPT "=> "
ea99e8f0	85	/* Console I/O Buffer Size */
6d0f6bcf	86	#define CONFIG_SYS_CBSIZE 256
ea99e8f0	87	/* Print Buffer Size */
6d0f6bcf	88	#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16)
ea99e8f0	89	/* max number of command args */
6d0f6bcf	90	#define CONFIG_SYS_MAXARGS 16
ea99e8f0	91	/* Boot Argument Buffer Size */
6d0f6bcf	92	#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE
ea99e8f0	93
6d0f6bcf JCPV	94	#define CONFIG_SYS_MEMTEST_START 0x00400000
6d0f6bcf JCPV	95	#define CONFIG_SYS_MEMTEST_END 0x00800000
ea99e8f0 MS	96
ea99e8f0 MS	97	/* everything, incl board info, in Hz */
6d0f6bcf	98	#undef CONFIG_SYS_CLKS_IN_HZ
ea99e8f0	99	/* spec says 66.666 MHz, but it appears to be 33 */
6d0f6bcf	100	#define CONFIG_SYS_HZ 3333333
ea99e8f0 MS	101
ea99e8f0 MS	102	/* default load address */
6d0f6bcf	103	#define CONFIG_SYS_LOAD_ADDR 0x00010000
ea99e8f0 MS	104
ea99e8f0 MS	105	/* valid baudrates */
6d0f6bcf	106	#define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, \
ea99e8f0 MS	107	115200, 230400 }
	108	#define CONFIG_SERIAL_RTS_ACTIVE 1
	109
	110	/*
	111	* Stack sizes
	112	* The stack sizes are set up in start.S using the settings below
	113	*/
	114	#define CONFIG_STACKSIZE (1281024) / regular stack */
	115	#ifdef CONFIG_USE_IRQ
	116	# define CONFIG_STACKSIZE_IRQ (41024) / IRQ stack */
	117	# define CONFIG_STACKSIZE_FIQ (41024) / FIQ stack */
	118	#endif
	119
	120	/* Expansion bus settings */
6d0f6bcf	121	#define CONFIG_SYS_EXP_CS0 0xbd113842
ea99e8f0 MS	122
	123	/* SDRAM settings */
	124	#define CONFIG_NR_DRAM_BANKS 1
	125	#define PHYS_SDRAM_1 0x00000000
6d0f6bcf	126	#define CONFIG_SYS_DRAM_BASE 0x00000000
ea99e8f0 MS	127
ea99e8f0 MS	128	#if CONFIG_ACTUX1_32MB
6d0f6bcf	129	# define CONFIG_SYS_SDR_CONFIG 0x18
ea99e8f0	130	# define PHYS_SDRAM_1_SIZE 0x02000000
6d0f6bcf JCPV	131	# define CONFIG_SYS_SDRAM_REFRESH_CNT 0x81a
	132	# define CONFIG_SYS_SDR_MODE_CONFIG 0x1
	133	# define CONFIG_SYS_DRAM_SIZE 0x02000000
ea99e8f0	134	#else /* 16MB SDRAM */
6d0f6bcf	135	# define CONFIG_SYS_SDR_CONFIG 0x3A
ea99e8f0	136	# define PHYS_SDRAM_1_SIZE 0x01000000
6d0f6bcf JCPV	137	# define CONFIG_SYS_SDRAM_REFRESH_CNT 0x81a
	138	# define CONFIG_SYS_SDR_MODE_CONFIG 0x1
	139	# define CONFIG_SYS_DRAM_SIZE 0x01000000
ea99e8f0 MS	140	#endif
	141
	142	/* FLASH organization */
	143	#if CONFIG_ACTUX1_FLASH2X2
6d0f6bcf	144	# define CONFIG_SYS_MAX_FLASH_BANKS 2
ea99e8f0	145	/* max number of sectors on one chip */
6d0f6bcf	146	# define CONFIG_SYS_MAX_FLASH_SECT 40
ea99e8f0 MS	147	# define PHYS_FLASH_1 0x50000000
ea99e8f0 MS	148	# define PHYS_FLASH_2 0x50200000
6d0f6bcf	149	# define CONFIG_SYS_FLASH_BANKS_LIST { PHYS_FLASH_1, PHYS_FLASH_2 }
ea99e8f0 MS	150	#endif
ea99e8f0 MS	151	#if CONFIG_ACTUX1_FLASH1X8
6d0f6bcf	152	# define CONFIG_SYS_MAX_FLASH_BANKS 1
ea99e8f0	153	/* max number of sectors on one chip */
6d0f6bcf	154	# define CONFIG_SYS_MAX_FLASH_SECT 140
ea99e8f0	155	# define PHYS_FLASH_1 0x50000000
6d0f6bcf	156	# define CONFIG_SYS_FLASH_BANKS_LIST { PHYS_FLASH_1 }
ea99e8f0 MS	157	#endif
ea99e8f0 MS	158
6d0f6bcf JCPV	159	#define CONFIG_SYS_FLASH_BASE PHYS_FLASH_1
	160	#define CONFIG_SYS_MONITOR_BASE PHYS_FLASH_1
	161	#define CONFIG_SYS_MONITOR_LEN (256 << 10)
ea99e8f0 MS	162
ea99e8f0 MS	163	/* Use common CFI driver */
6d0f6bcf	164	#define CONFIG_SYS_FLASH_CFI
00b1883a	165	#define CONFIG_FLASH_CFI_DRIVER
ea99e8f0	166	/* no byte writes on IXP4xx */
6d0f6bcf	167	#define CONFIG_SYS_FLASH_CFI_WIDTH FLASH_CFI_16BIT
ea99e8f0	168	/* print 'E' for empty sector on flinfo */
6d0f6bcf	169	#define CONFIG_SYS_FLASH_EMPTY_INFO
ea99e8f0 MS	170
	171	/* Ethernet */
	172
	173	/* include IXP4xx NPE support */
	174	#define CONFIG_IXP4XX_NPE 1
	175	/* use separate flash sector with ucode images */
	176	#define CONFIG_IXP4XX_NPE_EXT_UCODE_BASE 0x50040000
	177	#define CONFIG_NET_MULTI 1
	178	/* NPE0 PHY address */
	179	#define CONFIG_PHY_ADDR 0
	180	/* MII PHY management */
	181	#define CONFIG_MII 1
	182	/* Number of ethernet rx buffers & descriptors */
6d0f6bcf	183	#define CONFIG_SYS_RX_ETH_BUFFER 16
ea99e8f0 MS	184	#define CONFIG_RESET_PHY_R 1
	185
	186	#define CONFIG_CMD_DHCP
	187	#define CONFIG_CMD_NET
	188	#define CONFIG_CMD_MII
	189	#define CONFIG_CMD_PING
	190	#undef CONFIG_CMD_NFS
	191
	192	/* BOOTP options */
	193	#define CONFIG_BOOTP_BOOTFILESIZE
	194	#define CONFIG_BOOTP_BOOTPATH
	195	#define CONFIG_BOOTP_GATEWAY
	196	#define CONFIG_BOOTP_HOSTNAME
	197
	198	/* Cache Configuration */
6d0f6bcf	199	#define CONFIG_SYS_CACHELINE_SIZE 32
ea99e8f0 MS	200
	201	/*
	202	* environment organization:
	203	* one flash sector, embedded in uboot area (bottom bootblock flash)
	204	*/
5a1aceb0	205	#define CONFIG_ENV_IS_IN_FLASH 1
0e8d1586 JCPV	206	#define CONFIG_ENV_SIZE 0x2000
0e8d1586 JCPV	207	#define CONFIG_ENV_ADDR (PHYS_FLASH_1 + 0x4000)
6d0f6bcf	208	#define CONFIG_SYS_USE_PPCENV 1
ea99e8f0 MS	209
	210	#define CONFIG_EXTRA_ENV_SETTINGS \
	211	"mtd=IXP4XX-Flash.0:256k(uboot),64k(ucode),1152k(linux),-(root)\0" \
	212	"kerneladdr=50050000\0" \
	213	"rootaddr=50170000\0" \
	214	"loadaddr=10000\0" \
	215	"updateboot_ser=mw.b 10000 ff 40000;" \
	216	" loady ${loadaddr};" \
	217	" run eraseboot writeboot\0" \
	218	"updateboot_net=mw.b 10000 ff 40000;" \
	219	" tftp ${loadaddr} u-boot.bin;" \
	220	" run eraseboot writeboot\0" \
	221	"eraseboot=protect off 50000000 50003fff;" \
	222	" protect off 50006000 5003ffff;" \
	223	" erase 50000000 50003fff;" \
	224	" erase 50006000 5003ffff\0" \
	225	"writeboot=cp.b 10000 50000000 4000;" \
	226	" cp.b 16000 50006000 3a000\0" \
	227	"eraseenv=protect off 50004000 50005fff;" \
	228	" erase 50004000 50005fff\0" \
	229	"updateroot=tftp ${loadaddr} ${rootfile};" \
	230	" era ${rootaddr} +${filesize};" \
	231	" cp.b ${loadaddr} ${rootaddr} ${filesize}\0" \
	232	"updatekern=tftp ${loadaddr} ${kernelfile};" \
	233	" era ${kerneladdr} +${filesize};" \
	234	" cp.b ${loadaddr} ${kerneladdr} ${filesize}\0" \
	235	"flashargs=setenv bootargs mtdparts=${mtd} root=/dev/mtdblock3" \
	236	" rootfstype=squashfs,jffs2 init=/etc/preinit\0" \
	237	"netargs=setenv bootargs mtdparts=${mtd} root=/dev/mtdblock3" \
	238	" rootfstype=squashfs,jffs2 init=/etc/preinit\0" \
	239	"addtty=setenv bootargs ${bootargs} console=ttyS0,${baudrate}\0" \
	240	"addeth=setenv bootargs ${bootargs} ethaddr=${ethaddr}\0" \
	241	"boot_flash=run flashargs addtty addeth;" \
	242	" bootm ${kerneladdr}\0" \
	243	"boot_net=run netargs addtty addeth;" \
	244	" tftpboot ${loadaddr} ${kernelfile};" \
	245	" bootm\0"
	246
	247	#endif /* __CONFIG_H */