[J-u-boot.git] / arch / arm / mach-stm32mp / Kconfig

if ARCH_STM32MP

config SPL
	select SPL_BOARD_INIT
	select SPL_CLK
	select SPL_DM
	select SPL_DM_SEQ_ALIAS
	select SPL_DRIVERS_MISC
	select SPL_FRAMEWORK
	select SPL_GPIO
	select SPL_LIBCOMMON_SUPPORT
	select SPL_LIBGENERIC_SUPPORT
	select SPL_OF_CONTROL
	select SPL_OF_TRANSLATE
	select SPL_PINCTRL
	select SPL_REGMAP
	select SPL_DM_RESET
	select SPL_SERIAL
	select SPL_SYSCON
	select SPL_WATCHDOG if WATCHDOG
	imply BOOTSTAGE_STASH if SPL_BOOTSTAGE
	imply SPL_BOOTSTAGE if BOOTSTAGE
	imply SPL_DISPLAY_PRINT
	imply SPL_LIBDISK_SUPPORT
	imply SPL_SPI_LOAD if SPL_SPI

config SYS_SOC
	default "stm32mp"

config SYS_MALLOC_LEN
	default 0x2000000

config ENV_SIZE
	default 0x2000

choice
	prompt "Select STMicroelectronics STM32MPxxx Soc"
	default STM32MP15x

config STM32MP13x
	bool "Support STMicroelectronics STM32MP13x Soc"
	select ARM_SMCCC
	select CPU_V7A
	select CPU_V7_HAS_NONSEC
	select CPU_V7_HAS_VIRT
	select OF_BOARD
	select OF_BOARD_SETUP
	select PINCTRL_STM32
	select STM32_RCC
	select STM32_RESET
	select STM32_SERIAL
	select SYS_ARCH_TIMER
	imply CMD_NVEDIT_INFO
	help
		support of STMicroelectronics SOC STM32MP13x family
		STMicroelectronics MPU with core ARMv7

config STM32MP15x
	bool "Support STMicroelectronics STM32MP15x Soc"
	select ARCH_SUPPORT_PSCI
	select BINMAN
	select CPU_V7A
	select CPU_V7_HAS_NONSEC
	select CPU_V7_HAS_VIRT
	select OF_BOARD if TFABOOT
	select OF_BOARD_SETUP
	select PINCTRL_STM32
	select STM32_RCC
	select STM32_RESET
	select STM32_SERIAL
	select SUPPORT_SPL
	select SYS_ARCH_TIMER
	imply CMD_NVEDIT_INFO
	help
		support of STMicroelectronics SOC STM32MP15x family
		STM32MP157, STM32MP153 or STM32MP151
		STMicroelectronics MPU with core ARMv7
		dual core A7 for STM32MP157/3, monocore for STM32MP151
endchoice

config NR_DRAM_BANKS
	default 1

config DDR_CACHEABLE_SIZE
	hex "Size of the DDR marked cacheable in pre-reloc stage"
	default 0x40000000
	help
		Define the size of the DDR marked as cacheable in U-Boot
		pre-reloc stage.
		This option can be useful to avoid speculatif access
		to secured area of DDR used by TF-A or OP-TEE before U-Boot
		initialization.
		The areas marked "no-map" in device tree should be located
		before this limit: STM32_DDR_BASE + DDR_CACHEABLE_SIZE.

config SYS_MMCSD_RAW_MODE_U_BOOT_PARTITION_MMC2
	hex "Partition on MMC2 to use to load U-Boot from"
	depends on SYS_MMCSD_RAW_MODE_U_BOOT_USE_PARTITION
	default 1
	help
	  Partition on the second MMC to load U-Boot from when the MMC is being
	  used in raw mode

config STM32_ETZPC
	bool "STM32 Extended TrustZone Protection"
	depends on STM32MP15x || STM32MP13x
	default y
	imply BOOTP_SERVERIP
	help
	  Say y to enable STM32 Extended TrustZone Protection

config STM32_ECDSA_VERIFY
	bool "STM32 ECDSA verification via the ROM API"
	depends on SPL_ECDSA_VERIFY
	default y
	help
	  Say y to enable the uclass driver for ECDSA verification using the
	  ROM API provided on STM32MP.
	  The ROM API is only available during SPL for now.

config CMD_STM32KEY
	bool "command stm32key to fuse public key hash"
	help
		fuse public key hash in corresponding fuse used to authenticate
		binary.
		This command is used to evaluate the secure boot on stm32mp SOC,
		it is deactivated by default in real products.

source "arch/arm/mach-stm32mp/Kconfig.13x"
source "arch/arm/mach-stm32mp/Kconfig.15x"

source "arch/arm/mach-stm32mp/cmd_stm32prog/Kconfig"
endif
Commit	Line	Data
2514c2d0 PD	1	if ARCH_STM32MP
	2
	3	config SPL
97f7e39d	4	select SPL_BOARD_INIT
2514c2d0 PD	5	select SPL_CLK
	6	select SPL_DM
	7	select SPL_DM_SEQ_ALIAS
9ca00684	8	select SPL_DRIVERS_MISC
2514c2d0	9	select SPL_FRAMEWORK
83061dbd	10	select SPL_GPIO
2514c2d0 PD	11	select SPL_LIBCOMMON_SUPPORT
	12	select SPL_LIBGENERIC_SUPPORT
	13	select SPL_OF_CONTROL
	14	select SPL_OF_TRANSLATE
	15	select SPL_PINCTRL
	16	select SPL_REGMAP
bfc6bae8	17	select SPL_DM_RESET
2a736066	18	select SPL_SERIAL
2514c2d0	19	select SPL_SYSCON
078111b9	20	select SPL_WATCHDOG if WATCHDOG
27a986d4 PD	21	imply BOOTSTAGE_STASH if SPL_BOOTSTAGE
27a986d4 PD	22	imply SPL_BOOTSTAGE if BOOTSTAGE
006ea189	23	imply SPL_DISPLAY_PRINT
2514c2d0	24	imply SPL_LIBDISK_SUPPORT
ea2ca7e1	25	imply SPL_SPI_LOAD if SPL_SPI
2514c2d0 PD	26
	27	config SYS_SOC
	28	default "stm32mp"
	29
ef84dddd PD	30	config SYS_MALLOC_LEN
	31	default 0x2000000
	32
579a3e7b	33	config ENV_SIZE
1538e1a6	34	default 0x2000
579a3e7b	35
647d319c PD	36	choice
	37	prompt "Select STMicroelectronics STM32MPxxx Soc"
	38	default STM32MP15x
	39
960debbe PD	40	config STM32MP13x
	41	bool "Support STMicroelectronics STM32MP13x Soc"
	42	select ARM_SMCCC
	43	select CPU_V7A
	44	select CPU_V7_HAS_NONSEC
	45	select CPU_V7_HAS_VIRT
	46	select OF_BOARD
	47	select OF_BOARD_SETUP
	48	select PINCTRL_STM32
	49	select STM32_RCC
	50	select STM32_RESET
	51	select STM32_SERIAL
	52	select SYS_ARCH_TIMER
	53	imply CMD_NVEDIT_INFO
	54	help
	55	support of STMicroelectronics SOC STM32MP13x family
	56	STMicroelectronics MPU with core ARMv7
	57
84625488 PD	58	config STM32MP15x
84625488 PD	59	bool "Support STMicroelectronics STM32MP15x Soc"
17aeb589	60	select ARCH_SUPPORT_PSCI
5564b4cd	61	select BINMAN
acf15001	62	select CPU_V7A
17aeb589	63	select CPU_V7_HAS_NONSEC
41c79775	64	select CPU_V7_HAS_VIRT
22c0815e	65	select OF_BOARD if TFABOOT
e81f8d16	66	select OF_BOARD_SETUP
2514c2d0	67	select PINCTRL_STM32
d090cbab	68	select STM32_RCC
2514c2d0	69	select STM32_RESET
16a07223	70	select STM32_SERIAL
2ff0866b	71	select SUPPORT_SPL
7842b6a9	72	select SYS_ARCH_TIMER
c16cba88	73	imply CMD_NVEDIT_INFO
84625488 PD	74	help
	75	support of STMicroelectronics SOC STM32MP15x family
	76	STM32MP157, STM32MP153 or STM32MP151
	77	STMicroelectronics MPU with core ARMv7
	78	dual core A7 for STM32MP157/3, monocore for STM32MP151
647d319c PD	79	endchoice
647d319c PD	80
45ccdb6f PD	81	config NR_DRAM_BANKS
	82	default 1
	83
67f9f11f PD	84	config DDR_CACHEABLE_SIZE
67f9f11f PD	85	hex "Size of the DDR marked cacheable in pre-reloc stage"
67f9f11f PD	86	default 0x40000000
	87	help
	88	Define the size of the DDR marked as cacheable in U-Boot
	89	pre-reloc stage.
	90	This option can be useful to avoid speculatif access
	91	to secured area of DDR used by TF-A or OP-TEE before U-Boot
	92	initialization.
	93	The areas marked "no-map" in device tree should be located
	94	before this limit: STM32_DDR_BASE + DDR_CACHEABLE_SIZE.
	95
11dfd1a3 PD	96	config SYS_MMCSD_RAW_MODE_U_BOOT_PARTITION_MMC2
	97	hex "Partition on MMC2 to use to load U-Boot from"
	98	depends on SYS_MMCSD_RAW_MODE_U_BOOT_USE_PARTITION
	99	default 1
	100	help
	101	Partition on the second MMC to load U-Boot from when the MMC is being
	102	used in raw mode
	103
c60f3b35 PD	104	config STM32_ETZPC
c60f3b35 PD	105	bool "STM32 Extended TrustZone Protection"
960debbe	106	depends on STM32MP15x \|\| STM32MP13x
c60f3b35	107	default y
d3877fba	108	imply BOOTP_SERVERIP
c60f3b35 PD	109	help
	110	Say y to enable STM32 Extended TrustZone Protection
	111
ee870859 AG	112	config STM32_ECDSA_VERIFY
	113	bool "STM32 ECDSA verification via the ROM API"
	114	depends on SPL_ECDSA_VERIFY
	115	default y
	116	help
	117	Say y to enable the uclass driver for ECDSA verification using the
	118	ROM API provided on STM32MP.
	119	The ROM API is only available during SPL for now.
	120
f4cb5d69 PD	121	config CMD_STM32KEY
f4cb5d69 PD	122	bool "command stm32key to fuse public key hash"
f4cb5d69 PD	123	help
	124	fuse public key hash in corresponding fuse used to authenticate
	125	binary.
3a994811 PD	126	This command is used to evaluate the secure boot on stm32mp SOC,
3a994811 PD	127	it is deactivated by default in real products.
f4cb5d69	128
960debbe	129	source "arch/arm/mach-stm32mp/Kconfig.13x"
d8b78fd6	130	source "arch/arm/mach-stm32mp/Kconfig.15x"
320d2663	131
2dc22166	132	source "arch/arm/mach-stm32mp/cmd_stm32prog/Kconfig"
2514c2d0	133	endif