[J-u-boot.git] / drivers / rtc / ds1306.c

// SPDX-License-Identifier: GPL-2.0+
/*
 * (C) Copyright 2002 SIXNET, [email protected].
 *
 * (C) Copyright 2004, Li-Pro.Net <www.li-pro.net>
 * Stephan Linz <[email protected]>
 */

/*
 * Date & Time support for DS1306 RTC using SPI:
 *
 *    - SXNI855T:    it uses its own soft SPI here in this file
 *    - all other:   use the external spi_xfer() function
 *                   (see include/spi.h)
 */

#include <common.h>
#include <command.h>
#include <rtc.h>
#include <spi.h>
#include <linux/delay.h>

#define	RTC_SECONDS		0x00
#define	RTC_MINUTES		0x01
#define	RTC_HOURS		0x02
#define	RTC_DAY_OF_WEEK		0x03
#define	RTC_DATE_OF_MONTH	0x04
#define	RTC_MONTH		0x05
#define	RTC_YEAR		0x06

#define	RTC_SECONDS_ALARM0	0x07
#define	RTC_MINUTES_ALARM0	0x08
#define	RTC_HOURS_ALARM0	0x09
#define	RTC_DAY_OF_WEEK_ALARM0	0x0a

#define	RTC_SECONDS_ALARM1	0x0b
#define	RTC_MINUTES_ALARM1	0x0c
#define	RTC_HOURS_ALARM1	0x0d
#define	RTC_DAY_OF_WEEK_ALARM1	0x0e

#define	RTC_CONTROL		0x0f
#define	RTC_STATUS		0x10
#define	RTC_TRICKLE_CHARGER	0x11

#define	RTC_USER_RAM_BASE	0x20

/* ************************************************************************* */
#ifdef CONFIG_SXNI855T		/* !!! SHOULD BE CHANGED TO NEW CODE !!! */

static void soft_spi_send (unsigned char n);
static unsigned char soft_spi_read (void);
static void init_spi (void);

/*-----------------------------------------------------------------------
 * Definitions
 */

#define	PB_SPISCK	0x00000002	/* PB 30 */
#define PB_SPIMOSI	0x00000004	/* PB 29 */
#define PB_SPIMISO	0x00000008	/* PB 28 */
#define PB_SPI_CE	0x00010000	/* PB 15 */

/* ------------------------------------------------------------------------- */

/* read clock time from DS1306 and return it in *tmp */
int rtc_get (struct rtc_time *tmp)
{
	volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR;
	unsigned char spi_byte;	/* Data Byte */

	init_spi ();		/* set port B for software SPI */

	/* Now we can enable the DS1306 RTC */
	immap->im_cpm.cp_pbdat |= PB_SPI_CE;
	udelay(10);

	/* Shift out the address (0) of the time in the Clock Chip */
	soft_spi_send (0);

	/* Put the clock readings into the rtc_time structure */
	tmp->tm_sec = bcd2bin (soft_spi_read ());	/* Read seconds */
	tmp->tm_min = bcd2bin (soft_spi_read ());	/* Read minutes */

	/* Hours are trickier */
	spi_byte = soft_spi_read ();	/* Read Hours into temporary value */
	if (spi_byte & 0x40) {
		/* 12 hour mode bit is set (time is in 1-12 format) */
		if (spi_byte & 0x20) {
			/* since PM we add 11 to get 0-23 for hours */
			tmp->tm_hour = (bcd2bin (spi_byte & 0x1F)) + 11;
		} else {
			/* since AM we subtract 1 to get 0-23 for hours */
			tmp->tm_hour = (bcd2bin (spi_byte & 0x1F)) - 1;
		}
	} else {
		/* Otherwise, 0-23 hour format */
		tmp->tm_hour = (bcd2bin (spi_byte & 0x3F));
	}

	soft_spi_read ();	/* Read and discard Day of week */
	tmp->tm_mday = bcd2bin (soft_spi_read ());	/* Read Day of the Month */
	tmp->tm_mon = bcd2bin (soft_spi_read ());	/* Read Month */

	/* Read Year and convert to this century */
	tmp->tm_year = bcd2bin (soft_spi_read ()) + 2000;

	/* Now we can disable the DS1306 RTC */
	immap->im_cpm.cp_pbdat &= ~PB_SPI_CE;	/* Disable DS1306 Chip */
	udelay(10);

	rtc_calc_weekday(tmp);	/* Determine the day of week */

	debug ("Get DATE: %4d-%02d-%02d (wday=%d)  TIME: %2d:%02d:%02d\n",
	       tmp->tm_year, tmp->tm_mon, tmp->tm_mday, tmp->tm_wday,
	       tmp->tm_hour, tmp->tm_min, tmp->tm_sec);

	return 0;
}

/* ------------------------------------------------------------------------- */

/* set clock time in DS1306 RTC and in MPC8xx RTC */
int rtc_set (struct rtc_time *tmp)
{
	volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR;

	init_spi ();		/* set port B for software SPI */

	/* Now we can enable the DS1306 RTC */
	immap->im_cpm.cp_pbdat |= PB_SPI_CE;	/* Enable DS1306 Chip */
	udelay(10);

	/* First disable write protect in the clock chip control register */
	soft_spi_send (0x8F);	/* send address of the control register */
	soft_spi_send (0x00);	/* send control register contents */

	/* Now disable the DS1306 to terminate the write */
	immap->im_cpm.cp_pbdat &= ~PB_SPI_CE;
	udelay(10);

	/* Now enable the DS1306 to initiate a new write */
	immap->im_cpm.cp_pbdat |= PB_SPI_CE;
	udelay(10);

	/* Next, send the address of the clock time write registers */
	soft_spi_send (0x80);	/* send address of the first time register */

	/* Use Burst Mode to send all of the time data to the clock */
	bin2bcd (tmp->tm_sec);
	soft_spi_send (bin2bcd (tmp->tm_sec));	/* Send Seconds */
	soft_spi_send (bin2bcd (tmp->tm_min));	/* Send Minutes */
	soft_spi_send (bin2bcd (tmp->tm_hour));	/* Send Hour */
	soft_spi_send (bin2bcd (tmp->tm_wday));	/* Send Day of the Week */
	soft_spi_send (bin2bcd (tmp->tm_mday));	/* Send Day of Month */
	soft_spi_send (bin2bcd (tmp->tm_mon));	/* Send Month */
	soft_spi_send (bin2bcd (tmp->tm_year - 2000));	/* Send Year */

	/* Now we can disable the Clock chip to terminate the burst write */
	immap->im_cpm.cp_pbdat &= ~PB_SPI_CE;	/* Disable DS1306 Chip */
	udelay(10);

	/* Now we can enable the Clock chip to initiate a new write */
	immap->im_cpm.cp_pbdat |= PB_SPI_CE;	/* Enable DS1306 Chip */
	udelay(10);

	/* First we Enable write protect in the clock chip control register */
	soft_spi_send (0x8F);	/* send address of the control register */
	soft_spi_send (0x40);	/* send out Control Register contents */

	/* Now disable the DS1306 */
	immap->im_cpm.cp_pbdat &= ~PB_SPI_CE;	/*  Disable DS1306 Chip */
	udelay(10);

	/* Set standard MPC8xx clock to the same time so Linux will
	 * see the time even if it doesn't have a DS1306 clock driver.
	 * This helps with experimenting with standard kernels.
	 */
	{
		ulong tim;

		tim = rtc_mktime(tmp);

		immap->im_sitk.sitk_rtck = KAPWR_KEY;
		immap->im_sit.sit_rtc = tim;
	}

	debug ("Set DATE: %4d-%02d-%02d (wday=%d)  TIME: %2d:%02d:%02d\n",
	       tmp->tm_year, tmp->tm_mon, tmp->tm_mday, tmp->tm_wday,
	       tmp->tm_hour, tmp->tm_min, tmp->tm_sec);

	return 0;
}

/* ------------------------------------------------------------------------- */

/* Initialize Port B for software SPI */
static void init_spi (void)
{
	volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR;

	/* Force output pins to begin at logic 0 */
	immap->im_cpm.cp_pbdat &= ~(PB_SPI_CE | PB_SPIMOSI | PB_SPISCK);

	/* Set these 3 signals as outputs */
	immap->im_cpm.cp_pbdir |= (PB_SPIMOSI | PB_SPI_CE | PB_SPISCK);

	immap->im_cpm.cp_pbdir &= ~PB_SPIMISO;	/* Make MISO pin an input */
	udelay(10);
}

/* ------------------------------------------------------------------------- */

/* NOTE: soft_spi_send() assumes that the I/O lines are configured already */
static void soft_spi_send (unsigned char n)
{
	volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR;
	unsigned char bitpos;	/* bit position to receive */
	unsigned char i;	/* Loop Control */

	/* bit position to send, start with most significant bit */
	bitpos = 0x80;

	/* Send 8 bits to software SPI */
	for (i = 0; i < 8; i++) {	/* Loop for 8 bits */
		immap->im_cpm.cp_pbdat |= PB_SPISCK;	/* Raise SCK */

		if (n & bitpos)
			immap->im_cpm.cp_pbdat |= PB_SPIMOSI;	/* Set MOSI to 1 */
		else
			immap->im_cpm.cp_pbdat &= ~PB_SPIMOSI;	/* Set MOSI to 0 */
		udelay(10);

		immap->im_cpm.cp_pbdat &= ~PB_SPISCK;	/* Lower SCK */
		udelay(10);

		bitpos >>= 1;	/* Shift for next bit position */
	}
}

/* ------------------------------------------------------------------------- */

/* NOTE: soft_spi_read() assumes that the I/O lines are configured already */
static unsigned char soft_spi_read (void)
{
	volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR;

	unsigned char spi_byte = 0;	/* Return value, assume success */
	unsigned char bitpos;	/* bit position to receive */
	unsigned char i;	/* Loop Control */

	/* bit position to receive, start with most significant bit */
	bitpos = 0x80;

	/* Read 8 bits here */
	for (i = 0; i < 8; i++) {	/* Do 8 bits in loop */
		immap->im_cpm.cp_pbdat |= PB_SPISCK;	/* Raise SCK */
		udelay(10);
		if (immap->im_cpm.cp_pbdat & PB_SPIMISO)	/* Get a bit of data */
			spi_byte |= bitpos;	/* Set data accordingly */
		immap->im_cpm.cp_pbdat &= ~PB_SPISCK;	/* Lower SCK */
		udelay(10);
		bitpos >>= 1;	/* Shift for next bit position */
	}

	return spi_byte;	/* Return the byte read */
}

/* ------------------------------------------------------------------------- */

void rtc_reset (void)
{
	return;			/* nothing to do */
}

#else  /* not CONFIG_SXNI855T */
/* ************************************************************************* */

static unsigned char rtc_read (unsigned char reg);
static void rtc_write (unsigned char reg, unsigned char val);

static struct spi_slave *slave;

/* read clock time from DS1306 and return it in *tmp */
int rtc_get (struct rtc_time *tmp)
{
	unsigned char sec, min, hour, mday, wday, mon, year;

	/*
	 * Assuming Vcc = 2.0V (lowest speed)
	 *
	 * REVISIT: If we add an rtc_init() function we can do this
	 * step just once.
	 */
	if (!slave) {
		slave = spi_setup_slave(0, CONFIG_SYS_SPI_RTC_DEVID, 600000,
				SPI_MODE_3 | SPI_CS_HIGH);
		if (!slave)
			return;
	}

	if (spi_claim_bus(slave))
		return;

	sec = rtc_read (RTC_SECONDS);
	min = rtc_read (RTC_MINUTES);
	hour = rtc_read (RTC_HOURS);
	mday = rtc_read (RTC_DATE_OF_MONTH);
	wday = rtc_read (RTC_DAY_OF_WEEK);
	mon = rtc_read (RTC_MONTH);
	year = rtc_read (RTC_YEAR);

	spi_release_bus(slave);

	debug ("Get RTC year: %02x mon: %02x mday: %02x wday: %02x "
	       "hr: %02x min: %02x sec: %02x\n",
	       year, mon, mday, wday, hour, min, sec);
	debug ("Alarms[0]: wday: %02x hour: %02x min: %02x sec: %02x\n",
	       rtc_read (RTC_DAY_OF_WEEK_ALARM0),
	       rtc_read (RTC_HOURS_ALARM0),
	       rtc_read (RTC_MINUTES_ALARM0), rtc_read (RTC_SECONDS_ALARM0));
	debug ("Alarms[1]: wday: %02x hour: %02x min: %02x sec: %02x\n",
	       rtc_read (RTC_DAY_OF_WEEK_ALARM1),
	       rtc_read (RTC_HOURS_ALARM1),
	       rtc_read (RTC_MINUTES_ALARM1), rtc_read (RTC_SECONDS_ALARM1));

	tmp->tm_sec = bcd2bin (sec & 0x7F);	/* convert Seconds */
	tmp->tm_min = bcd2bin (min & 0x7F);	/* convert Minutes */

	/* convert Hours */
	tmp->tm_hour = (hour & 0x40)
		? ((hour & 0x20)	/* 12 hour mode */
		   ? bcd2bin (hour & 0x1F) + 11	/* PM */
		   : bcd2bin (hour & 0x1F) - 1	/* AM */
		)
		: bcd2bin (hour & 0x3F);	/* 24 hour mode */

	tmp->tm_mday = bcd2bin (mday & 0x3F);	/* convert Day of the Month */
	tmp->tm_mon = bcd2bin (mon & 0x1F);	/* convert Month */
	tmp->tm_year = bcd2bin (year) + 2000;	/* convert Year */
	tmp->tm_wday = bcd2bin (wday & 0x07) - 1;	/* convert Day of the Week */
	tmp->tm_yday = 0;
	tmp->tm_isdst = 0;

	debug ("Get DATE: %4d-%02d-%02d (wday=%d)  TIME: %2d:%02d:%02d\n",
	       tmp->tm_year, tmp->tm_mon, tmp->tm_mday, tmp->tm_wday,
	       tmp->tm_hour, tmp->tm_min, tmp->tm_sec);

	return 0;
}

/* ------------------------------------------------------------------------- */

/* set clock time from *tmp in DS1306 RTC */
int rtc_set (struct rtc_time *tmp)
{
	/* Assuming Vcc = 2.0V (lowest speed) */
	if (!slave) {
		slave = spi_setup_slave(0, CONFIG_SYS_SPI_RTC_DEVID, 600000,
				SPI_MODE_3 | SPI_CS_HIGH);
		if (!slave)
			return;
	}

	if (spi_claim_bus(slave))
		return;

	debug ("Set DATE: %4d-%02d-%02d (wday=%d)  TIME: %2d:%02d:%02d\n",
	       tmp->tm_year, tmp->tm_mon, tmp->tm_mday, tmp->tm_wday,
	       tmp->tm_hour, tmp->tm_min, tmp->tm_sec);

	rtc_write (RTC_SECONDS, bin2bcd (tmp->tm_sec));
	rtc_write (RTC_MINUTES, bin2bcd (tmp->tm_min));
	rtc_write (RTC_HOURS, bin2bcd (tmp->tm_hour));
	rtc_write (RTC_DAY_OF_WEEK, bin2bcd (tmp->tm_wday + 1));
	rtc_write (RTC_DATE_OF_MONTH, bin2bcd (tmp->tm_mday));
	rtc_write (RTC_MONTH, bin2bcd (tmp->tm_mon));
	rtc_write (RTC_YEAR, bin2bcd (tmp->tm_year - 2000));

	spi_release_bus(slave);
}

/* ------------------------------------------------------------------------- */

/* reset the DS1306 */
void rtc_reset (void)
{
	/* Assuming Vcc = 2.0V (lowest speed) */
	if (!slave) {
		slave = spi_setup_slave(0, CONFIG_SYS_SPI_RTC_DEVID, 600000,
				SPI_MODE_3 | SPI_CS_HIGH);
		if (!slave)
			return;
	}

	if (spi_claim_bus(slave))
		return;

	/* clear the control register */
	rtc_write (RTC_CONTROL, 0x00);	/* 1st step: reset WP */
	rtc_write (RTC_CONTROL, 0x00);	/* 2nd step: reset 1Hz, AIE1, AIE0 */

	/* reset all alarms */
	rtc_write (RTC_SECONDS_ALARM0, 0x00);
	rtc_write (RTC_SECONDS_ALARM1, 0x00);
	rtc_write (RTC_MINUTES_ALARM0, 0x00);
	rtc_write (RTC_MINUTES_ALARM1, 0x00);
	rtc_write (RTC_HOURS_ALARM0, 0x00);
	rtc_write (RTC_HOURS_ALARM1, 0x00);
	rtc_write (RTC_DAY_OF_WEEK_ALARM0, 0x00);
	rtc_write (RTC_DAY_OF_WEEK_ALARM1, 0x00);

	spi_release_bus(slave);
}

/* ------------------------------------------------------------------------- */

static unsigned char rtc_read (unsigned char reg)
{
	int ret;

	ret = spi_w8r8(slave, reg);
	return ret < 0 ? 0 : ret;
}

/* ------------------------------------------------------------------------- */

static void rtc_write (unsigned char reg, unsigned char val)
{
	unsigned char dout[2];	/* SPI Output Data Bytes */
	unsigned char din[2];	/* SPI Input Data Bytes */

	dout[0] = 0x80 | reg;
	dout[1] = val;

	spi_xfer (slave, 16, dout, din, SPI_XFER_BEGIN | SPI_XFER_END);
}

#endif /* end of code exclusion (see #ifdef CONFIG_SXNI855T above) */
Commit	Line	Data
83d290c5	1	// SPDX-License-Identifier: GPL-2.0+
affae2bf WD	2	/*
	3	* (C) Copyright 2002 SIXNET, [email protected].
	4	*
ec4c544b WD	5	* (C) Copyright 2004, Li-Pro.Net <www.li-pro.net>
ec4c544b WD	6	* Stephan Linz <[email protected]>
affae2bf WD	7	*/
	8
	9	/*
ec4c544b WD	10	* Date & Time support for DS1306 RTC using SPI:
	11	*
	12	* - SXNI855T: it uses its own soft SPI here in this file
	13	* - all other: use the external spi_xfer() function
	14	* (see include/spi.h)
affae2bf WD	15	*/
	16
	17	#include <common.h>
	18	#include <command.h>
	19	#include <rtc.h>
ec4c544b	20	#include <spi.h>
c05ed00a	21	#include <linux/delay.h>
affae2bf	22
ec4c544b WD	23	#define RTC_SECONDS 0x00
	24	#define RTC_MINUTES 0x01
	25	#define RTC_HOURS 0x02
	26	#define RTC_DAY_OF_WEEK 0x03
	27	#define RTC_DATE_OF_MONTH 0x04
	28	#define RTC_MONTH 0x05
	29	#define RTC_YEAR 0x06
	30
	31	#define RTC_SECONDS_ALARM0 0x07
	32	#define RTC_MINUTES_ALARM0 0x08
	33	#define RTC_HOURS_ALARM0 0x09
	34	#define RTC_DAY_OF_WEEK_ALARM0 0x0a
	35
	36	#define RTC_SECONDS_ALARM1 0x0b
	37	#define RTC_MINUTES_ALARM1 0x0c
	38	#define RTC_HOURS_ALARM1 0x0d
	39	#define RTC_DAY_OF_WEEK_ALARM1 0x0e
	40
	41	#define RTC_CONTROL 0x0f
	42	#define RTC_STATUS 0x10
	43	#define RTC_TRICKLE_CHARGER 0x11
	44
	45	#define RTC_USER_RAM_BASE 0x20
	46
ec4c544b WD	47	/* ************************************************************************* */
	48	#ifdef CONFIG_SXNI855T /* !!! SHOULD BE CHANGED TO NEW CODE !!! */
	49
	50	static void soft_spi_send (unsigned char n);
	51	static unsigned char soft_spi_read (void);
	52	static void init_spi (void);
affae2bf WD	53
	54	/*-----------------------------------------------------------------------
	55	* Definitions
	56	*/
	57
	58	#define PB_SPISCK 0x00000002 /* PB 30 */
	59	#define PB_SPIMOSI 0x00000004 /* PB 29 */
	60	#define PB_SPIMISO 0x00000008 /* PB 28 */
	61	#define PB_SPI_CE 0x00010000 /* PB 15 */
	62
	63	/* ------------------------------------------------------------------------- */
	64
	65	/* read clock time from DS1306 and return it in tmp /
b73a19e1	66	int rtc_get (struct rtc_time *tmp)
affae2bf	67	{
6d0f6bcf	68	volatile immap_t immap = (immap_t ) CONFIG_SYS_IMMR;
ec4c544b WD	69	unsigned char spi_byte; /* Data Byte */
	70
	71	init_spi (); /* set port B for software SPI */
	72
	73	/* Now we can enable the DS1306 RTC */
	74	immap->im_cpm.cp_pbdat \|= PB_SPI_CE;
07e11146	75	udelay(10);
ec4c544b WD	76
	77	/* Shift out the address (0) of the time in the Clock Chip */
	78	soft_spi_send (0);
	79
	80	/* Put the clock readings into the rtc_time structure */
	81	tmp->tm_sec = bcd2bin (soft_spi_read ()); /* Read seconds */
	82	tmp->tm_min = bcd2bin (soft_spi_read ()); /* Read minutes */
	83
	84	/* Hours are trickier */
	85	spi_byte = soft_spi_read (); /* Read Hours into temporary value */
	86	if (spi_byte & 0x40) {
	87	/* 12 hour mode bit is set (time is in 1-12 format) */
	88	if (spi_byte & 0x20) {
	89	/* since PM we add 11 to get 0-23 for hours */
	90	tmp->tm_hour = (bcd2bin (spi_byte & 0x1F)) + 11;
	91	} else {
	92	/* since AM we subtract 1 to get 0-23 for hours */
	93	tmp->tm_hour = (bcd2bin (spi_byte & 0x1F)) - 1;
	94	}
	95	} else {
	96	/* Otherwise, 0-23 hour format */
	97	tmp->tm_hour = (bcd2bin (spi_byte & 0x3F));
	98	}
affae2bf	99
ec4c544b WD	100	soft_spi_read (); /* Read and discard Day of week */
	101	tmp->tm_mday = bcd2bin (soft_spi_read ()); /* Read Day of the Month */
	102	tmp->tm_mon = bcd2bin (soft_spi_read ()); /* Read Month */
affae2bf	103
ec4c544b WD	104	/* Read Year and convert to this century */
ec4c544b WD	105	tmp->tm_year = bcd2bin (soft_spi_read ()) + 2000;
affae2bf	106
ec4c544b WD	107	/* Now we can disable the DS1306 RTC */
ec4c544b WD	108	immap->im_cpm.cp_pbdat &= ~PB_SPI_CE; /* Disable DS1306 Chip */
07e11146	109	udelay(10);
affae2bf	110
199e87c3	111	rtc_calc_weekday(tmp); /* Determine the day of week */
affae2bf	112
ec4c544b WD	113	debug ("Get DATE: %4d-%02d-%02d (wday=%d) TIME: %2d:%02d:%02d\n",
	114	tmp->tm_year, tmp->tm_mon, tmp->tm_mday, tmp->tm_wday,
	115	tmp->tm_hour, tmp->tm_min, tmp->tm_sec);
b73a19e1 YT	116
b73a19e1 YT	117	return 0;
ec4c544b WD	118	}
	119
	120	/* ------------------------------------------------------------------------- */
	121
	122	/* set clock time in DS1306 RTC and in MPC8xx RTC */
d1e23194	123	int rtc_set (struct rtc_time *tmp)
ec4c544b	124	{
6d0f6bcf	125	volatile immap_t immap = (immap_t ) CONFIG_SYS_IMMR;
ec4c544b WD	126
	127	init_spi (); /* set port B for software SPI */
	128
	129	/* Now we can enable the DS1306 RTC */
	130	immap->im_cpm.cp_pbdat \|= PB_SPI_CE; /* Enable DS1306 Chip */
07e11146	131	udelay(10);
ec4c544b WD	132
	133	/* First disable write protect in the clock chip control register */
	134	soft_spi_send (0x8F); /* send address of the control register */
	135	soft_spi_send (0x00); /* send control register contents */
	136
	137	/* Now disable the DS1306 to terminate the write */
	138	immap->im_cpm.cp_pbdat &= ~PB_SPI_CE;
07e11146	139	udelay(10);
ec4c544b WD	140
	141	/* Now enable the DS1306 to initiate a new write */
	142	immap->im_cpm.cp_pbdat \|= PB_SPI_CE;
07e11146	143	udelay(10);
ec4c544b WD	144
	145	/* Next, send the address of the clock time write registers */
	146	soft_spi_send (0x80); /* send address of the first time register */
	147
	148	/* Use Burst Mode to send all of the time data to the clock */
	149	bin2bcd (tmp->tm_sec);
	150	soft_spi_send (bin2bcd (tmp->tm_sec)); /* Send Seconds */
	151	soft_spi_send (bin2bcd (tmp->tm_min)); /* Send Minutes */
	152	soft_spi_send (bin2bcd (tmp->tm_hour)); /* Send Hour */
	153	soft_spi_send (bin2bcd (tmp->tm_wday)); /* Send Day of the Week */
	154	soft_spi_send (bin2bcd (tmp->tm_mday)); /* Send Day of Month */
	155	soft_spi_send (bin2bcd (tmp->tm_mon)); /* Send Month */
	156	soft_spi_send (bin2bcd (tmp->tm_year - 2000)); /* Send Year */
	157
	158	/* Now we can disable the Clock chip to terminate the burst write */
	159	immap->im_cpm.cp_pbdat &= ~PB_SPI_CE; /* Disable DS1306 Chip */
07e11146	160	udelay(10);
ec4c544b WD	161
	162	/* Now we can enable the Clock chip to initiate a new write */
	163	immap->im_cpm.cp_pbdat \|= PB_SPI_CE; /* Enable DS1306 Chip */
07e11146	164	udelay(10);
ec4c544b WD	165
	166	/* First we Enable write protect in the clock chip control register */
	167	soft_spi_send (0x8F); /* send address of the control register */
	168	soft_spi_send (0x40); /* send out Control Register contents */
	169
	170	/* Now disable the DS1306 */
	171	immap->im_cpm.cp_pbdat &= ~PB_SPI_CE; /* Disable DS1306 Chip */
07e11146	172	udelay(10);
ec4c544b WD	173
	174	/* Set standard MPC8xx clock to the same time so Linux will
	175	* see the time even if it doesn't have a DS1306 clock driver.
	176	* This helps with experimenting with standard kernels.
	177	*/
	178	{
	179	ulong tim;
	180
71420983	181	tim = rtc_mktime(tmp);
ec4c544b WD	182
	183	immap->im_sitk.sitk_rtck = KAPWR_KEY;
	184	immap->im_sit.sit_rtc = tim;
affae2bf	185	}
affae2bf	186
ec4c544b WD	187	debug ("Set DATE: %4d-%02d-%02d (wday=%d) TIME: %2d:%02d:%02d\n",
	188	tmp->tm_year, tmp->tm_mon, tmp->tm_mday, tmp->tm_wday,
	189	tmp->tm_hour, tmp->tm_min, tmp->tm_sec);
d1e23194 JCPV	190
d1e23194 JCPV	191	return 0;
ec4c544b	192	}
affae2bf	193
ec4c544b	194	/* ------------------------------------------------------------------------- */
affae2bf	195
ec4c544b WD	196	/* Initialize Port B for software SPI */
	197	static void init_spi (void)
	198	{
6d0f6bcf	199	volatile immap_t immap = (immap_t ) CONFIG_SYS_IMMR;
affae2bf	200
ec4c544b WD	201	/* Force output pins to begin at logic 0 */
ec4c544b WD	202	immap->im_cpm.cp_pbdat &= ~(PB_SPI_CE \| PB_SPIMOSI \| PB_SPISCK);
affae2bf	203
ec4c544b WD	204	/* Set these 3 signals as outputs */
	205	immap->im_cpm.cp_pbdir \|= (PB_SPIMOSI \| PB_SPI_CE \| PB_SPISCK);
	206
	207	immap->im_cpm.cp_pbdir &= ~PB_SPIMISO; /* Make MISO pin an input */
07e11146	208	udelay(10);
affae2bf WD	209	}
	210
	211	/* ------------------------------------------------------------------------- */
	212
ec4c544b WD	213	/* NOTE: soft_spi_send() assumes that the I/O lines are configured already */
ec4c544b WD	214	static void soft_spi_send (unsigned char n)
affae2bf	215	{
6d0f6bcf	216	volatile immap_t immap = (immap_t ) CONFIG_SYS_IMMR;
ec4c544b WD	217	unsigned char bitpos; /* bit position to receive */
	218	unsigned char i; /* Loop Control */
	219
	220	/* bit position to send, start with most significant bit */
	221	bitpos = 0x80;
	222
	223	/* Send 8 bits to software SPI */
	224	for (i = 0; i < 8; i++) { /* Loop for 8 bits */
	225	immap->im_cpm.cp_pbdat \|= PB_SPISCK; /* Raise SCK */
	226
	227	if (n & bitpos)
	228	immap->im_cpm.cp_pbdat \|= PB_SPIMOSI; /* Set MOSI to 1 */
	229	else
	230	immap->im_cpm.cp_pbdat &= ~PB_SPIMOSI; /* Set MOSI to 0 */
07e11146	231	udelay(10);
ec4c544b WD	232
ec4c544b WD	233	immap->im_cpm.cp_pbdat &= ~PB_SPISCK; /* Lower SCK */
07e11146	234	udelay(10);
ec4c544b WD	235
	236	bitpos >>= 1; /* Shift for next bit position */
	237	}
affae2bf WD	238	}
	239
	240	/* ------------------------------------------------------------------------- */
	241
ec4c544b WD	242	/* NOTE: soft_spi_read() assumes that the I/O lines are configured already */
ec4c544b WD	243	static unsigned char soft_spi_read (void)
affae2bf	244	{
6d0f6bcf	245	volatile immap_t immap = (immap_t ) CONFIG_SYS_IMMR;
ec4c544b WD	246
	247	unsigned char spi_byte = 0; /* Return value, assume success */
	248	unsigned char bitpos; /* bit position to receive */
	249	unsigned char i; /* Loop Control */
	250
	251	/* bit position to receive, start with most significant bit */
	252	bitpos = 0x80;
	253
	254	/* Read 8 bits here */
	255	for (i = 0; i < 8; i++) { /* Do 8 bits in loop */
	256	immap->im_cpm.cp_pbdat \|= PB_SPISCK; /* Raise SCK */
07e11146	257	udelay(10);
ec4c544b WD	258	if (immap->im_cpm.cp_pbdat & PB_SPIMISO) /* Get a bit of data */
	259	spi_byte \|= bitpos; /* Set data accordingly */
	260	immap->im_cpm.cp_pbdat &= ~PB_SPISCK; /* Lower SCK */
07e11146	261	udelay(10);
ec4c544b WD	262	bitpos >>= 1; /* Shift for next bit position */
	263	}
	264
	265	return spi_byte; /* Return the byte read */
affae2bf WD	266	}
	267
	268	/* ------------------------------------------------------------------------- */
	269
ec4c544b	270	void rtc_reset (void)
affae2bf	271	{
ec4c544b WD	272	return; /* nothing to do */
	273	}
	274
	275	#else /* not CONFIG_SXNI855T */
	276	/* ************************************************************************* */
	277
3f85ce27 WD	278	static unsigned char rtc_read (unsigned char reg);
	279	static void rtc_write (unsigned char reg, unsigned char val);
	280
d255bb0e HS	281	static struct spi_slave *slave;
d255bb0e HS	282
ec4c544b	283	/* read clock time from DS1306 and return it in tmp /
b73a19e1	284	int rtc_get (struct rtc_time *tmp)
ec4c544b WD	285	{
	286	unsigned char sec, min, hour, mday, wday, mon, year;
	287
d255bb0e HS	288	/*
	289	* Assuming Vcc = 2.0V (lowest speed)
	290	*
	291	* REVISIT: If we add an rtc_init() function we can do this
	292	* step just once.
	293	*/
	294	if (!slave) {
6d0f6bcf	295	slave = spi_setup_slave(0, CONFIG_SYS_SPI_RTC_DEVID, 600000,
d255bb0e HS	296	SPI_MODE_3 \| SPI_CS_HIGH);
	297	if (!slave)
	298	return;
	299	}
	300
	301	if (spi_claim_bus(slave))
	302	return;
	303
ec4c544b WD	304	sec = rtc_read (RTC_SECONDS);
	305	min = rtc_read (RTC_MINUTES);
	306	hour = rtc_read (RTC_HOURS);
	307	mday = rtc_read (RTC_DATE_OF_MONTH);
	308	wday = rtc_read (RTC_DAY_OF_WEEK);
	309	mon = rtc_read (RTC_MONTH);
	310	year = rtc_read (RTC_YEAR);
	311
d255bb0e HS	312	spi_release_bus(slave);
d255bb0e HS	313
ec4c544b WD	314	debug ("Get RTC year: %02x mon: %02x mday: %02x wday: %02x "
	315	"hr: %02x min: %02x sec: %02x\n",
	316	year, mon, mday, wday, hour, min, sec);
	317	debug ("Alarms[0]: wday: %02x hour: %02x min: %02x sec: %02x\n",
	318	rtc_read (RTC_DAY_OF_WEEK_ALARM0),
	319	rtc_read (RTC_HOURS_ALARM0),
	320	rtc_read (RTC_MINUTES_ALARM0), rtc_read (RTC_SECONDS_ALARM0));
	321	debug ("Alarms[1]: wday: %02x hour: %02x min: %02x sec: %02x\n",
	322	rtc_read (RTC_DAY_OF_WEEK_ALARM1),
	323	rtc_read (RTC_HOURS_ALARM1),
	324	rtc_read (RTC_MINUTES_ALARM1), rtc_read (RTC_SECONDS_ALARM1));
	325
	326	tmp->tm_sec = bcd2bin (sec & 0x7F); /* convert Seconds */
	327	tmp->tm_min = bcd2bin (min & 0x7F); /* convert Minutes */
	328
	329	/* convert Hours */
	330	tmp->tm_hour = (hour & 0x40)
	331	? ((hour & 0x20) /* 12 hour mode */
	332	? bcd2bin (hour & 0x1F) + 11 /* PM */
	333	: bcd2bin (hour & 0x1F) - 1 /* AM */
	334	)
	335	: bcd2bin (hour & 0x3F); /* 24 hour mode */
	336
	337	tmp->tm_mday = bcd2bin (mday & 0x3F); /* convert Day of the Month */
	338	tmp->tm_mon = bcd2bin (mon & 0x1F); /* convert Month */
	339	tmp->tm_year = bcd2bin (year) + 2000; /* convert Year */
	340	tmp->tm_wday = bcd2bin (wday & 0x07) - 1; /* convert Day of the Week */
	341	tmp->tm_yday = 0;
	342	tmp->tm_isdst = 0;
	343
	344	debug ("Get DATE: %4d-%02d-%02d (wday=%d) TIME: %2d:%02d:%02d\n",
	345	tmp->tm_year, tmp->tm_mon, tmp->tm_mday, tmp->tm_wday,
	346	tmp->tm_hour, tmp->tm_min, tmp->tm_sec);
b73a19e1 YT	347
b73a19e1 YT	348	return 0;
affae2bf WD	349	}
	350
	351	/* ------------------------------------------------------------------------- */
	352
ec4c544b	353	/* set clock time from tmp in DS1306 RTC /
d1e23194	354	int rtc_set (struct rtc_time *tmp)
affae2bf	355	{
d255bb0e HS	356	/* Assuming Vcc = 2.0V (lowest speed) */
d255bb0e HS	357	if (!slave) {
6d0f6bcf	358	slave = spi_setup_slave(0, CONFIG_SYS_SPI_RTC_DEVID, 600000,
d255bb0e HS	359	SPI_MODE_3 \| SPI_CS_HIGH);
	360	if (!slave)
	361	return;
	362	}
	363
	364	if (spi_claim_bus(slave))
	365	return;
	366
ec4c544b WD	367	debug ("Set DATE: %4d-%02d-%02d (wday=%d) TIME: %2d:%02d:%02d\n",
	368	tmp->tm_year, tmp->tm_mon, tmp->tm_mday, tmp->tm_wday,
	369	tmp->tm_hour, tmp->tm_min, tmp->tm_sec);
	370
ec4c544b	371	rtc_write (RTC_SECONDS, bin2bcd (tmp->tm_sec));
da4849fb WD	372	rtc_write (RTC_MINUTES, bin2bcd (tmp->tm_min));
	373	rtc_write (RTC_HOURS, bin2bcd (tmp->tm_hour));
	374	rtc_write (RTC_DAY_OF_WEEK, bin2bcd (tmp->tm_wday + 1));
	375	rtc_write (RTC_DATE_OF_MONTH, bin2bcd (tmp->tm_mday));
	376	rtc_write (RTC_MONTH, bin2bcd (tmp->tm_mon));
	377	rtc_write (RTC_YEAR, bin2bcd (tmp->tm_year - 2000));
d255bb0e HS	378
d255bb0e HS	379	spi_release_bus(slave);
affae2bf WD	380	}
	381
	382	/* ------------------------------------------------------------------------- */
	383
ec4c544b WD	384	/* reset the DS1306 */
	385	void rtc_reset (void)
	386	{
d255bb0e HS	387	/* Assuming Vcc = 2.0V (lowest speed) */
d255bb0e HS	388	if (!slave) {
6d0f6bcf	389	slave = spi_setup_slave(0, CONFIG_SYS_SPI_RTC_DEVID, 600000,
d255bb0e HS	390	SPI_MODE_3 \| SPI_CS_HIGH);
	391	if (!slave)
	392	return;
	393	}
	394
	395	if (spi_claim_bus(slave))
	396	return;
	397
ec4c544b WD	398	/* clear the control register */
	399	rtc_write (RTC_CONTROL, 0x00); /* 1st step: reset WP */
	400	rtc_write (RTC_CONTROL, 0x00); /* 2nd step: reset 1Hz, AIE1, AIE0 */
	401
	402	/* reset all alarms */
	403	rtc_write (RTC_SECONDS_ALARM0, 0x00);
	404	rtc_write (RTC_SECONDS_ALARM1, 0x00);
	405	rtc_write (RTC_MINUTES_ALARM0, 0x00);
	406	rtc_write (RTC_MINUTES_ALARM1, 0x00);
	407	rtc_write (RTC_HOURS_ALARM0, 0x00);
	408	rtc_write (RTC_HOURS_ALARM1, 0x00);
	409	rtc_write (RTC_DAY_OF_WEEK_ALARM0, 0x00);
	410	rtc_write (RTC_DAY_OF_WEEK_ALARM1, 0x00);
d255bb0e HS	411
d255bb0e HS	412	spi_release_bus(slave);
ec4c544b WD	413	}
	414
	415	/* ------------------------------------------------------------------------- */
affae2bf	416
ec4c544b WD	417	static unsigned char rtc_read (unsigned char reg)
ec4c544b WD	418	{
d255bb0e	419	int ret;
affae2bf	420
d255bb0e HS	421	ret = spi_w8r8(slave, reg);
d255bb0e HS	422	return ret < 0 ? 0 : ret;
affae2bf WD	423	}
	424
	425	/* ------------------------------------------------------------------------- */
	426
ec4c544b	427	static void rtc_write (unsigned char reg, unsigned char val)
affae2bf	428	{
ec4c544b WD	429	unsigned char dout[2]; /* SPI Output Data Bytes */
ec4c544b WD	430	unsigned char din[2]; /* SPI Input Data Bytes */
affae2bf	431
ec4c544b WD	432	dout[0] = 0x80 \| reg;
ec4c544b WD	433	dout[1] = val;
affae2bf	434
d255bb0e	435	spi_xfer (slave, 16, dout, din, SPI_XFER_BEGIN \| SPI_XFER_END);
ec4c544b	436	}
affae2bf	437
ec4c544b	438	#endif /* end of code exclusion (see #ifdef CONFIG_SXNI855T above) */