[J-u-boot.git] / drivers / rtc / abx80x.c

// SPDX-License-Identifier: GPL-2.0
/*
 * A driver for the I2C members of the Abracon AB x8xx RTC family,
 * and compatible: AB 1805 and AB 0805
 *
 * Copyright 2014-2015 Macq S.A.
 * Copyright 2020 Linaro
 *
 * Author: Philippe De Muyter <[email protected]>
 * Author: Alexandre Belloni <[email protected]>
 * Author: Ying-Chun Liu (PaulLiu) <[email protected]>
 *
 */

#include <common.h>
#include <dm.h>
#include <i2c.h>
#include <rtc.h>
#include <log.h>
#include <linux/bitfield.h>

#define ABX8XX_REG_HTH		0x00
#define ABX8XX_REG_SC		0x01
#define ABX8XX_REG_MN		0x02
#define ABX8XX_REG_HR		0x03
#define ABX8XX_REG_DA		0x04
#define ABX8XX_REG_MO		0x05
#define ABX8XX_REG_YR		0x06
#define ABX8XX_REG_WD		0x07

#define ABX8XX_REG_AHTH		0x08
#define ABX8XX_REG_ASC		0x09
#define ABX8XX_REG_AMN		0x0a
#define ABX8XX_REG_AHR		0x0b
#define ABX8XX_REG_ADA		0x0c
#define ABX8XX_REG_AMO		0x0d
#define ABX8XX_REG_AWD		0x0e

#define ABX8XX_REG_STATUS	0x0f
#define ABX8XX_STATUS_AF	BIT(2)
#define ABX8XX_STATUS_BLF	BIT(4)
#define ABX8XX_STATUS_WDT	BIT(6)

#define ABX8XX_REG_CTRL1	0x10
#define ABX8XX_CTRL_WRITE	BIT(0)
#define ABX8XX_CTRL_ARST	BIT(2)
#define ABX8XX_CTRL_12_24	BIT(6)

#define ABX8XX_REG_CTRL2	0x11
#define ABX8XX_CTRL2_RSVD	BIT(5)

#define ABX8XX_REG_IRQ		0x12
#define ABX8XX_IRQ_AIE		BIT(2)
#define ABX8XX_IRQ_IM_1_4	(0x3 << 5)

#define ABX8XX_REG_CD_TIMER_CTL	0x18

#define ABX8XX_REG_OSC		0x1c
#define ABX8XX_OSC_FOS		BIT(3)
#define ABX8XX_OSC_BOS		BIT(4)
#define ABX8XX_OSC_ACAL_512	BIT(5)
#define ABX8XX_OSC_ACAL_1024	BIT(6)

#define ABX8XX_OSC_OSEL		BIT(7)

#define ABX8XX_REG_OSS		0x1d
#define ABX8XX_OSS_OF		BIT(1)
#define ABX8XX_OSS_OMODE	BIT(4)

#define ABX8XX_REG_WDT		0x1b
#define ABX8XX_WDT_WDS		BIT(7)
#define ABX8XX_WDT_BMB_MASK	0x7c
#define ABX8XX_WDT_BMB_SHIFT	2
#define ABX8XX_WDT_MAX_TIME	(ABX8XX_WDT_BMB_MASK >> ABX8XX_WDT_BMB_SHIFT)
#define ABX8XX_WDT_WRB_MASK	0x03
#define ABX8XX_WDT_WRB_1HZ	0x02

#define ABX8XX_REG_CFG_KEY	0x1f
#define ABX8XX_CFG_KEY_OSC	0xa1
#define ABX8XX_CFG_KEY_MISC	0x9d

#define ABX8XX_REG_ID0		0x28

#define ABX8XX_REG_OUT_CTRL	0x30
#define ABX8XX_OUT_CTRL_EXDS	BIT(4)

#define ABX8XX_REG_TRICKLE	0x20
#define ABX8XX_TRICKLE_CHARGE_ENABLE	0xa0
#define ABX8XX_TRICKLE_STANDARD_DIODE	0x8
#define ABX8XX_TRICKLE_SCHOTTKY_DIODE	0x4

#define ABX8XX_REG_EXTRAM	0x3f
#define ABX8XX_EXTRAM_XADS	GENMASK(1, 0)

#define ABX8XX_SRAM_BASE	0x40
#define ABX8XX_SRAM_WIN_SIZE	0x40U
#define ABX8XX_RAM_SIZE		256

#define RAM_ADDR_LOWER		GENMASK(5, 0)
#define RAM_ADDR_UPPER		GENMASK(7, 6)

static u8 trickle_resistors[] = {0, 3, 6, 11};

enum abx80x_chip {AB0801, AB0803, AB0804, AB0805,
	AB1801, AB1803, AB1804, AB1805, RV1805, ABX80X};

struct abx80x_cap {
	u16 pn;
	bool has_tc;
	bool has_wdog;
};

static struct abx80x_cap abx80x_caps[] = {
	[AB0801] = {.pn = 0x0801},
	[AB0803] = {.pn = 0x0803},
	[AB0804] = {.pn = 0x0804, .has_tc = true, .has_wdog = true},
	[AB0805] = {.pn = 0x0805, .has_tc = true, .has_wdog = true},
	[AB1801] = {.pn = 0x1801},
	[AB1803] = {.pn = 0x1803},
	[AB1804] = {.pn = 0x1804, .has_tc = true, .has_wdog = true},
	[AB1805] = {.pn = 0x1805, .has_tc = true, .has_wdog = true},
	[RV1805] = {.pn = 0x1805, .has_tc = true, .has_wdog = true},
	[ABX80X] = {.pn = 0}
};

static int abx80x_rtc_xfer(struct udevice *dev, unsigned int offset,
			   u8 *val, unsigned int bytes, bool write)
{
	int ret;

	if (offset + bytes > ABX8XX_RAM_SIZE)
		return -EINVAL;

	while (bytes) {
		u8 extram, reg, len, lower, upper;

		lower = FIELD_GET(RAM_ADDR_LOWER, offset);
		upper = FIELD_GET(RAM_ADDR_UPPER, offset);
		extram = FIELD_PREP(ABX8XX_EXTRAM_XADS, upper);
		reg = ABX8XX_SRAM_BASE + lower;
		len = min(lower + bytes, ABX8XX_SRAM_WIN_SIZE) - lower;

		ret = dm_i2c_reg_write(dev, ABX8XX_REG_EXTRAM, extram);
		if (ret)
			return ret;

		if (write)
			ret = dm_i2c_write(dev, reg, val, len);
		else
			ret = dm_i2c_read(dev, reg, val, len);
		if (ret)
			return ret;

		offset += len;
		val += len;
		bytes -= len;
	}

	return 0;
}

static int abx80x_rtc_read(struct udevice *dev, unsigned int offset, u8 *val,
			   unsigned int bytes)
{
	return abx80x_rtc_xfer(dev, offset, val, bytes, false);
}

static int abx80x_rtc_write(struct udevice *dev, unsigned int offset,
			    const u8 *val, unsigned int bytes)
{
	return abx80x_rtc_xfer(dev, offset, (u8 *)val, bytes, true);
}

static int abx80x_is_rc_mode(struct udevice *dev)
{
	int flags = 0;

	flags =  dm_i2c_reg_read(dev, ABX8XX_REG_OSS);
	if (flags < 0) {
		log_err("Failed to read autocalibration attribute\n");
		return flags;
	}

	return (flags & ABX8XX_OSS_OMODE) ? 1 : 0;
}

static int abx80x_enable_trickle_charger(struct udevice *dev, u8 trickle_cfg)
{
	int err;

	/*
	 * Write the configuration key register to enable access to the Trickle
	 * register
	 */
	err = dm_i2c_reg_write(dev, ABX8XX_REG_CFG_KEY, ABX8XX_CFG_KEY_MISC);
	if (err < 0) {
		log_err("Unable to write configuration key\n");
		return -EIO;
	}

	err = dm_i2c_reg_write(dev, ABX8XX_REG_TRICKLE,
			       ABX8XX_TRICKLE_CHARGE_ENABLE | trickle_cfg);
	if (err < 0) {
		log_err("Unable to write trickle register\n");
		return -EIO;
	}

	return 0;
}

static int abx80x_rtc_read_time(struct udevice *dev, struct rtc_time *tm)
{
	unsigned char buf[8];
	int err, flags, rc_mode = 0;

	/* Read the Oscillator Failure only in XT mode */
	rc_mode = abx80x_is_rc_mode(dev);
	if (rc_mode < 0)
		return rc_mode;

	if (!rc_mode) {
		flags = dm_i2c_reg_read(dev, ABX8XX_REG_OSS);
		if (flags < 0) {
			log_err("Unable to read oscillator status.\n");
			return flags;
		}

		if (flags & ABX8XX_OSS_OF)
			log_debug("Oscillator fail, data is not accurate.\n");
	}

	err = dm_i2c_read(dev, ABX8XX_REG_HTH,
			  buf, sizeof(buf));
	if (err < 0) {
		log_err("Unable to read date\n");
		return -EIO;
	}

	tm->tm_sec = bcd2bin(buf[ABX8XX_REG_SC] & 0x7F);
	tm->tm_min = bcd2bin(buf[ABX8XX_REG_MN] & 0x7F);
	tm->tm_hour = bcd2bin(buf[ABX8XX_REG_HR] & 0x3F);
	tm->tm_wday = buf[ABX8XX_REG_WD] & 0x7;
	tm->tm_mday = bcd2bin(buf[ABX8XX_REG_DA] & 0x3F);
	tm->tm_mon = bcd2bin(buf[ABX8XX_REG_MO] & 0x1F);
	tm->tm_year = bcd2bin(buf[ABX8XX_REG_YR]) + 2000;

	return 0;
}

static int abx80x_rtc_set_time(struct udevice *dev, const struct rtc_time *tm)
{
	unsigned char buf[8];
	int err, flags;

	if (tm->tm_year < 2000)
		return -EINVAL;

	buf[ABX8XX_REG_HTH] = 0;
	buf[ABX8XX_REG_SC] = bin2bcd(tm->tm_sec);
	buf[ABX8XX_REG_MN] = bin2bcd(tm->tm_min);
	buf[ABX8XX_REG_HR] = bin2bcd(tm->tm_hour);
	buf[ABX8XX_REG_DA] = bin2bcd(tm->tm_mday);
	buf[ABX8XX_REG_MO] = bin2bcd(tm->tm_mon);
	buf[ABX8XX_REG_YR] = bin2bcd(tm->tm_year - 2000);
	buf[ABX8XX_REG_WD] = tm->tm_wday;

	err = dm_i2c_write(dev, ABX8XX_REG_HTH,
			   buf, sizeof(buf));
	if (err < 0) {
		log_err("Unable to write to date registers\n");
		return -EIO;
	}

	/* Clear the OF bit of Oscillator Status Register */
	flags = dm_i2c_reg_read(dev, ABX8XX_REG_OSS);
	if (flags < 0) {
		log_err("Unable to read oscillator status.\n");
		return flags;
	}

	err = dm_i2c_reg_write(dev, ABX8XX_REG_OSS,
			       flags & ~ABX8XX_OSS_OF);
	if (err < 0) {
		log_err("Unable to write oscillator status register\n");
		return err;
	}

	return 0;
}

static int abx80x_rtc_set_autocalibration(struct udevice *dev,
					  int autocalibration)
{
	int retval, flags = 0;

	if (autocalibration != 0 && autocalibration != 1024 &&
	    autocalibration != 512) {
		log_err("autocalibration value outside permitted range\n");
		return -EINVAL;
	}

	flags = dm_i2c_reg_read(dev, ABX8XX_REG_OSC);
	if (flags < 0)
		return flags;

	if (autocalibration == 0) {
		flags &= ~(ABX8XX_OSC_ACAL_512 | ABX8XX_OSC_ACAL_1024);
	} else if (autocalibration == 1024) {
		/* 1024 autocalibration is 0x10 */
		flags |= ABX8XX_OSC_ACAL_1024;
		flags &= ~(ABX8XX_OSC_ACAL_512);
	} else {
		/* 512 autocalibration is 0x11 */
		flags |= (ABX8XX_OSC_ACAL_1024 | ABX8XX_OSC_ACAL_512);
	}

	/* Unlock write access to Oscillator Control Register */
	retval = dm_i2c_reg_write(dev, ABX8XX_REG_CFG_KEY,
				  ABX8XX_CFG_KEY_OSC);
	if (retval < 0) {
		log_err("Failed to write CONFIG_KEY register\n");
		return retval;
	}

	retval = dm_i2c_reg_write(dev, ABX8XX_REG_OSC, flags);

	return retval;
}

static int abx80x_rtc_get_autocalibration(struct udevice *dev)
{
	int flags = 0, autocalibration;

	flags =  dm_i2c_reg_read(dev, ABX8XX_REG_OSC);
	if (flags < 0)
		return flags;

	if (flags & ABX8XX_OSC_ACAL_512)
		autocalibration = 512;
	else if (flags & ABX8XX_OSC_ACAL_1024)
		autocalibration = 1024;
	else
		autocalibration = 0;

	return autocalibration;
}

static struct rtc_time default_tm = { 0, 0, 0, 1, 1, 2000, 6, 0, 0 };

static int abx80x_rtc_reset(struct udevice *dev)
{
	int ret = 0;

	int autocalib = abx80x_rtc_get_autocalibration(dev);

	if (autocalib != 0)
		abx80x_rtc_set_autocalibration(dev, 0);

	ret = abx80x_rtc_set_time(dev, &default_tm);
	if (ret != 0) {
		log_err("cannot set time to default_tm. error %d\n", ret);
		return ret;
	}

	return ret;
}

static const struct rtc_ops abx80x_rtc_ops = {
	.get	= abx80x_rtc_read_time,
	.set	= abx80x_rtc_set_time,
	.reset	= abx80x_rtc_reset,
	.read	= abx80x_rtc_read,
	.write	= abx80x_rtc_write,
};

static int abx80x_dt_trickle_cfg(struct udevice *dev)
{
	const char *diode;
	int trickle_cfg = 0;
	int i, ret = 0;
	u32 tmp;

	diode = ofnode_read_string(dev_ofnode(dev), "abracon,tc-diode");
	if (!diode)
		return ret;

	if (!strcmp(diode, "standard")) {
		trickle_cfg |= ABX8XX_TRICKLE_STANDARD_DIODE;
	} else if (!strcmp(diode, "schottky")) {
		trickle_cfg |= ABX8XX_TRICKLE_SCHOTTKY_DIODE;
	} else {
		log_err("Invalid tc-diode value: %s\n", diode);
		return -EINVAL;
	}

	ret = ofnode_read_u32(dev_ofnode(dev), "abracon,tc-resistor", &tmp);
	if (ret)
		return ret;

	for (i = 0; i < sizeof(trickle_resistors); i++)
		if (trickle_resistors[i] == tmp)
			break;

	if (i == sizeof(trickle_resistors)) {
		log_err("Invalid tc-resistor value: %u\n", tmp);
		return -EINVAL;
	}

	return (trickle_cfg | i);
}

static int abx80x_probe(struct udevice *dev)
{
	int i, data, err, trickle_cfg = -EINVAL;
	unsigned char buf[7];
	unsigned int part = dev->driver_data;
	unsigned int partnumber;
	unsigned int majrev, minrev;
	unsigned int lot;
	unsigned int wafer;
	unsigned int uid;

	err = dm_i2c_read(dev, ABX8XX_REG_ID0, buf, sizeof(buf));
	if (err < 0) {
		log_err("Unable to read partnumber\n");
		return -EIO;
	}

	partnumber = (buf[0] << 8) | buf[1];
	majrev = buf[2] >> 3;
	minrev = buf[2] & 0x7;
	lot = ((buf[4] & 0x80) << 2) | ((buf[6] & 0x80) << 1) | buf[3];
	uid = ((buf[4] & 0x7f) << 8) | buf[5];
	wafer = (buf[6] & 0x7c) >> 2;
	log_debug("model %04x, revision %u.%u, lot %x, wafer %x, uid %x\n",
		  partnumber, majrev, minrev, lot, wafer, uid);

	data = dm_i2c_reg_read(dev, ABX8XX_REG_CTRL1);
	if (data < 0) {
		log_err("Unable to read control register\n");
		return -EIO;
	}

	err = dm_i2c_reg_write(dev, ABX8XX_REG_CTRL1,
			       ((data & ~(ABX8XX_CTRL_12_24 |
					  ABX8XX_CTRL_ARST)) |
				ABX8XX_CTRL_WRITE));
	if (err < 0) {
		log_err("Unable to write control register\n");
		return -EIO;
	}

	/* Configure RV1805 specifics */
	if (part == RV1805) {
		/*
		 * Avoid accidentally entering test mode. This can happen
		 * on the RV1805 in case the reserved bit 5 in control2
		 * register is set. RV-1805-C3 datasheet indicates that
		 * the bit should be cleared in section 11h - Control2.
		 */
		data = dm_i2c_reg_read(dev, ABX8XX_REG_CTRL2);
		if (data < 0) {
			log_err("Unable to read control2 register\n");
			return -EIO;
		}

		err = dm_i2c_reg_write(dev, ABX8XX_REG_CTRL2,
				       data & ~ABX8XX_CTRL2_RSVD);
		if (err < 0) {
			log_err("Unable to write control2 register\n");
			return -EIO;
		}

		/*
		 * Avoid extra power leakage. The RV1805 uses smaller
		 * 10pin package and the EXTI input is not present.
		 * Disable it to avoid leakage.
		 */
		data = dm_i2c_reg_read(dev, ABX8XX_REG_OUT_CTRL);
		if (data < 0) {
			log_err("Unable to read output control register\n");
			return -EIO;
		}

		/*
		 * Write the configuration key register to enable access to
		 * the config2 register
		 */
		err = dm_i2c_reg_write(dev, ABX8XX_REG_CFG_KEY,
				       ABX8XX_CFG_KEY_MISC);
		if (err < 0) {
			log_err("Unable to write configuration key\n");
			return -EIO;
		}

		err = dm_i2c_reg_write(dev, ABX8XX_REG_OUT_CTRL,
				       data | ABX8XX_OUT_CTRL_EXDS);
		if (err < 0) {
			log_err("Unable to write output control register\n");
			return -EIO;
		}
	}

	/* part autodetection */
	if (part == ABX80X) {
		for (i = 0; abx80x_caps[i].pn; i++)
			if (partnumber == abx80x_caps[i].pn)
				break;
		if (abx80x_caps[i].pn == 0) {
			log_err("Unknown part: %04x\n", partnumber);
			return -EINVAL;
		}
		part = i;
	}

	if (partnumber != abx80x_caps[part].pn) {
		log_err("partnumber mismatch %04x != %04x\n",
			partnumber, abx80x_caps[part].pn);
		return -EINVAL;
	}

	if (abx80x_caps[part].has_tc)
		trickle_cfg = abx80x_dt_trickle_cfg(dev);

	if (trickle_cfg > 0) {
		log_debug("Enabling trickle charger: %02x\n", trickle_cfg);
		abx80x_enable_trickle_charger(dev, trickle_cfg);
	}

	err = dm_i2c_reg_write(dev, ABX8XX_REG_CD_TIMER_CTL, BIT(2));
	if (err)
		return err;

	return 0;
}

static const struct udevice_id abx80x_of_match[] = {
	{
		.compatible = "abracon,abx80x",
		.data = ABX80X
	},
	{
		.compatible = "abracon,ab0801",
		.data = AB0801
	},
	{
		.compatible = "abracon,ab0803",
		.data = AB0803
	},
	{
		.compatible = "abracon,ab0804",
		.data = AB0804
	},
	{
		.compatible = "abracon,ab0805",
		.data = AB0805
	},
	{
		.compatible = "abracon,ab1801",
		.data = AB1801
	},
	{
		.compatible = "abracon,ab1803",
		.data = AB1803
	},
	{
		.compatible = "abracon,ab1804",
		.data = AB1804
	},
	{
		.compatible = "abracon,ab1805",
		.data = AB1805
	},
	{
		.compatible = "microcrystal,rv1805",
		.data = RV1805
	},
	{ }
};

U_BOOT_DRIVER(abx80x_rtc) = {
	.name	= "rtc-abx80x",
	.id     = UCLASS_RTC,
	.probe		= abx80x_probe,
	.of_match = abx80x_of_match,
	.ops = &abx80x_rtc_ops,
};
Commit	Line	Data
8d612ccd YCLP	1	// SPDX-License-Identifier: GPL-2.0
	2	/*
	3	* A driver for the I2C members of the Abracon AB x8xx RTC family,
	4	* and compatible: AB 1805 and AB 0805
	5	*
	6	* Copyright 2014-2015 Macq S.A.
	7	* Copyright 2020 Linaro
	8	*
	9	* Author: Philippe De Muyter <[email protected]>
	10	* Author: Alexandre Belloni <[email protected]>
	11	* Author: Ying-Chun Liu (PaulLiu) <[email protected]>
	12	*
	13	*/
	14
	15	#include <common.h>
	16	#include <dm.h>
	17	#include <i2c.h>
	18	#include <rtc.h>
	19	#include <log.h>
546795b5	20	#include <linux/bitfield.h>
8d612ccd YCLP	21
	22	#define ABX8XX_REG_HTH 0x00
	23	#define ABX8XX_REG_SC 0x01
	24	#define ABX8XX_REG_MN 0x02
	25	#define ABX8XX_REG_HR 0x03
	26	#define ABX8XX_REG_DA 0x04
	27	#define ABX8XX_REG_MO 0x05
	28	#define ABX8XX_REG_YR 0x06
	29	#define ABX8XX_REG_WD 0x07
	30
	31	#define ABX8XX_REG_AHTH 0x08
	32	#define ABX8XX_REG_ASC 0x09
	33	#define ABX8XX_REG_AMN 0x0a
	34	#define ABX8XX_REG_AHR 0x0b
	35	#define ABX8XX_REG_ADA 0x0c
	36	#define ABX8XX_REG_AMO 0x0d
	37	#define ABX8XX_REG_AWD 0x0e
	38
	39	#define ABX8XX_REG_STATUS 0x0f
	40	#define ABX8XX_STATUS_AF BIT(2)
	41	#define ABX8XX_STATUS_BLF BIT(4)
	42	#define ABX8XX_STATUS_WDT BIT(6)
	43
	44	#define ABX8XX_REG_CTRL1 0x10
	45	#define ABX8XX_CTRL_WRITE BIT(0)
	46	#define ABX8XX_CTRL_ARST BIT(2)
	47	#define ABX8XX_CTRL_12_24 BIT(6)
	48
	49	#define ABX8XX_REG_CTRL2 0x11
	50	#define ABX8XX_CTRL2_RSVD BIT(5)
	51
	52	#define ABX8XX_REG_IRQ 0x12
	53	#define ABX8XX_IRQ_AIE BIT(2)
	54	#define ABX8XX_IRQ_IM_1_4 (0x3 << 5)
	55
	56	#define ABX8XX_REG_CD_TIMER_CTL 0x18
	57
	58	#define ABX8XX_REG_OSC 0x1c
	59	#define ABX8XX_OSC_FOS BIT(3)
	60	#define ABX8XX_OSC_BOS BIT(4)
	61	#define ABX8XX_OSC_ACAL_512 BIT(5)
	62	#define ABX8XX_OSC_ACAL_1024 BIT(6)
	63
	64	#define ABX8XX_OSC_OSEL BIT(7)
	65
	66	#define ABX8XX_REG_OSS 0x1d
	67	#define ABX8XX_OSS_OF BIT(1)
	68	#define ABX8XX_OSS_OMODE BIT(4)
	69
	70	#define ABX8XX_REG_WDT 0x1b
	71	#define ABX8XX_WDT_WDS BIT(7)
	72	#define ABX8XX_WDT_BMB_MASK 0x7c
	73	#define ABX8XX_WDT_BMB_SHIFT 2
	74	#define ABX8XX_WDT_MAX_TIME (ABX8XX_WDT_BMB_MASK >> ABX8XX_WDT_BMB_SHIFT)
	75	#define ABX8XX_WDT_WRB_MASK 0x03
	76	#define ABX8XX_WDT_WRB_1HZ 0x02
	77
	78	#define ABX8XX_REG_CFG_KEY 0x1f
	79	#define ABX8XX_CFG_KEY_OSC 0xa1
	80	#define ABX8XX_CFG_KEY_MISC 0x9d
	81
	82	#define ABX8XX_REG_ID0 0x28
	83
	84	#define ABX8XX_REG_OUT_CTRL 0x30
85	#define ABX8XX_OUT_CTRL_EXDS BIT(4)
86
87	#define ABX8XX_REG_TRICKLE 0x20
88	#define ABX8XX_TRICKLE_CHARGE_ENABLE 0xa0
89	#define ABX8XX_TRICKLE_STANDARD_DIODE 0x8
90	#define ABX8XX_TRICKLE_SCHOTTKY_DIODE 0x4
91
546795b5 SA	92	#define ABX8XX_REG_EXTRAM 0x3f
	93	#define ABX8XX_EXTRAM_XADS GENMASK(1, 0)
	94
	95	#define ABX8XX_SRAM_BASE 0x40
	96	#define ABX8XX_SRAM_WIN_SIZE 0x40U
	97	#define ABX8XX_RAM_SIZE 256
	98
	99	#define RAM_ADDR_LOWER GENMASK(5, 0)
	100	#define RAM_ADDR_UPPER GENMASK(7, 6)
	101
8d612ccd YCLP	102	static u8 trickle_resistors[] = {0, 3, 6, 11};
	103
	104	enum abx80x_chip {AB0801, AB0803, AB0804, AB0805,
	105	AB1801, AB1803, AB1804, AB1805, RV1805, ABX80X};
	106
	107	struct abx80x_cap {
	108	u16 pn;
	109	bool has_tc;
	110	bool has_wdog;
	111	};
	112
	113	static struct abx80x_cap abx80x_caps[] = {
	114	[AB0801] = {.pn = 0x0801},
	115	[AB0803] = {.pn = 0x0803},
	116	[AB0804] = {.pn = 0x0804, .has_tc = true, .has_wdog = true},
	117	[AB0805] = {.pn = 0x0805, .has_tc = true, .has_wdog = true},
	118	[AB1801] = {.pn = 0x1801},
	119	[AB1803] = {.pn = 0x1803},
	120	[AB1804] = {.pn = 0x1804, .has_tc = true, .has_wdog = true},
	121	[AB1805] = {.pn = 0x1805, .has_tc = true, .has_wdog = true},
	122	[RV1805] = {.pn = 0x1805, .has_tc = true, .has_wdog = true},
	123	[ABX80X] = {.pn = 0}
	124	};
	125
546795b5 SA	126	static int abx80x_rtc_xfer(struct udevice *dev, unsigned int offset,
546795b5 SA	127	u8 *val, unsigned int bytes, bool write)
8d612ccd	128	{
546795b5	129	int ret;
8d612ccd	130
546795b5	131	if (offset + bytes > ABX8XX_RAM_SIZE)
8d612ccd YCLP	132	return -EINVAL;
8d612ccd YCLP	133
546795b5 SA	134	while (bytes) {
	135	u8 extram, reg, len, lower, upper;
	136
	137	lower = FIELD_GET(RAM_ADDR_LOWER, offset);
	138	upper = FIELD_GET(RAM_ADDR_UPPER, offset);
	139	extram = FIELD_PREP(ABX8XX_EXTRAM_XADS, upper);
	140	reg = ABX8XX_SRAM_BASE + lower;
	141	len = min(lower + bytes, ABX8XX_SRAM_WIN_SIZE) - lower;
	142
	143	ret = dm_i2c_reg_write(dev, ABX8XX_REG_EXTRAM, extram);
	144	if (ret)
	145	return ret;
	146
	147	if (write)
	148	ret = dm_i2c_write(dev, reg, val, len);
	149	else
	150	ret = dm_i2c_read(dev, reg, val, len);
	151	if (ret)
	152	return ret;
	153
	154	offset += len;
	155	val += len;
	156	bytes -= len;
	157	}
8d612ccd	158
546795b5	159	return 0;
8d612ccd YCLP	160	}
8d612ccd YCLP	161
546795b5 SA	162	static int abx80x_rtc_read(struct udevice dev, unsigned int offset, u8 val,
546795b5 SA	163	unsigned int bytes)
8d612ccd	164	{
546795b5 SA	165	return abx80x_rtc_xfer(dev, offset, val, bytes, false);
546795b5 SA	166	}
8d612ccd	167
546795b5 SA	168	static int abx80x_rtc_write(struct udevice *dev, unsigned int offset,
	169	const u8 *val, unsigned int bytes)
	170	{
	171	return abx80x_rtc_xfer(dev, offset, (u8 *)val, bytes, true);
8d612ccd YCLP	172	}
	173
	174	static int abx80x_is_rc_mode(struct udevice *dev)
	175	{
	176	int flags = 0;
	177
	178	flags = dm_i2c_reg_read(dev, ABX8XX_REG_OSS);
	179	if (flags < 0) {
	180	log_err("Failed to read autocalibration attribute\n");
	181	return flags;
	182	}
	183
	184	return (flags & ABX8XX_OSS_OMODE) ? 1 : 0;
	185	}
	186
	187	static int abx80x_enable_trickle_charger(struct udevice *dev, u8 trickle_cfg)
	188	{
	189	int err;
	190
	191	/*
	192	* Write the configuration key register to enable access to the Trickle
	193	* register
	194	*/
	195	err = dm_i2c_reg_write(dev, ABX8XX_REG_CFG_KEY, ABX8XX_CFG_KEY_MISC);
	196	if (err < 0) {
	197	log_err("Unable to write configuration key\n");
	198	return -EIO;
	199	}
	200
	201	err = dm_i2c_reg_write(dev, ABX8XX_REG_TRICKLE,
	202	ABX8XX_TRICKLE_CHARGE_ENABLE \| trickle_cfg);
	203	if (err < 0) {
	204	log_err("Unable to write trickle register\n");
	205	return -EIO;
	206	}
	207
	208	return 0;
	209	}
	210
	211	static int abx80x_rtc_read_time(struct udevice dev, struct rtc_time tm)
	212	{
	213	unsigned char buf[8];
	214	int err, flags, rc_mode = 0;
	215
	216	/* Read the Oscillator Failure only in XT mode */
	217	rc_mode = abx80x_is_rc_mode(dev);
	218	if (rc_mode < 0)
	219	return rc_mode;
	220
	221	if (!rc_mode) {
	222	flags = dm_i2c_reg_read(dev, ABX8XX_REG_OSS);
	223	if (flags < 0) {
	224	log_err("Unable to read oscillator status.\n");
	225	return flags;
	226	}
	227
	228	if (flags & ABX8XX_OSS_OF)
	229	log_debug("Oscillator fail, data is not accurate.\n");
	230	}
	231
	232	err = dm_i2c_read(dev, ABX8XX_REG_HTH,
	233	buf, sizeof(buf));
	234	if (err < 0) {
	235	log_err("Unable to read date\n");
236	return -EIO;
237	}
238
239	tm->tm_sec = bcd2bin(buf[ABX8XX_REG_SC] & 0x7F);
240	tm->tm_min = bcd2bin(buf[ABX8XX_REG_MN] & 0x7F);
241	tm->tm_hour = bcd2bin(buf[ABX8XX_REG_HR] & 0x3F);
242	tm->tm_wday = buf[ABX8XX_REG_WD] & 0x7;
243	tm->tm_mday = bcd2bin(buf[ABX8XX_REG_DA] & 0x3F);
244	tm->tm_mon = bcd2bin(buf[ABX8XX_REG_MO] & 0x1F);
245	tm->tm_year = bcd2bin(buf[ABX8XX_REG_YR]) + 2000;
246
247	return 0;
248	}
249
250	static int abx80x_rtc_set_time(struct udevice dev, const struct rtc_time tm)
251	{
252	unsigned char buf[8];
253	int err, flags;
254
255	if (tm->tm_year < 2000)
256	return -EINVAL;
257
258	buf[ABX8XX_REG_HTH] = 0;
259	buf[ABX8XX_REG_SC] = bin2bcd(tm->tm_sec);
260	buf[ABX8XX_REG_MN] = bin2bcd(tm->tm_min);
261	buf[ABX8XX_REG_HR] = bin2bcd(tm->tm_hour);
262	buf[ABX8XX_REG_DA] = bin2bcd(tm->tm_mday);
263	buf[ABX8XX_REG_MO] = bin2bcd(tm->tm_mon);
264	buf[ABX8XX_REG_YR] = bin2bcd(tm->tm_year - 2000);
265	buf[ABX8XX_REG_WD] = tm->tm_wday;
266
267	err = dm_i2c_write(dev, ABX8XX_REG_HTH,
268	buf, sizeof(buf));
269	if (err < 0) {
270	log_err("Unable to write to date registers\n");
271	return -EIO;
272	}
273
274	/* Clear the OF bit of Oscillator Status Register */
275	flags = dm_i2c_reg_read(dev, ABX8XX_REG_OSS);
276	if (flags < 0) {
277	log_err("Unable to read oscillator status.\n");
278	return flags;
279	}
280
281	err = dm_i2c_reg_write(dev, ABX8XX_REG_OSS,
282	flags & ~ABX8XX_OSS_OF);
283	if (err < 0) {
284	log_err("Unable to write oscillator status register\n");
285	return err;
286	}
287
288	return 0;
289	}
290
291	static int abx80x_rtc_set_autocalibration(struct udevice *dev,
292	int autocalibration)
293	{
294	int retval, flags = 0;
295
296	if (autocalibration != 0 && autocalibration != 1024 &&
297	autocalibration != 512) {
298	log_err("autocalibration value outside permitted range\n");
299	return -EINVAL;
300	}
301
302	flags = dm_i2c_reg_read(dev, ABX8XX_REG_OSC);
303	if (flags < 0)
304	return flags;
305
306	if (autocalibration == 0) {
307	flags &= ~(ABX8XX_OSC_ACAL_512 \| ABX8XX_OSC_ACAL_1024);
308	} else if (autocalibration == 1024) {
309	/* 1024 autocalibration is 0x10 */
310	flags \|= ABX8XX_OSC_ACAL_1024;
311	flags &= ~(ABX8XX_OSC_ACAL_512);
312	} else {
313	/* 512 autocalibration is 0x11 */
314	flags \|= (ABX8XX_OSC_ACAL_1024 \| ABX8XX_OSC_ACAL_512);
315	}
316
317	/* Unlock write access to Oscillator Control Register */
318	retval = dm_i2c_reg_write(dev, ABX8XX_REG_CFG_KEY,
319	ABX8XX_CFG_KEY_OSC);
320	if (retval < 0) {
321	log_err("Failed to write CONFIG_KEY register\n");
322	return retval;
323	}
324
325	retval = dm_i2c_reg_write(dev, ABX8XX_REG_OSC, flags);
326
327	return retval;
328	}
329
330	static int abx80x_rtc_get_autocalibration(struct udevice *dev)
331	{
332	int flags = 0, autocalibration;
333
334	flags = dm_i2c_reg_read(dev, ABX8XX_REG_OSC);
335	if (flags < 0)
336	return flags;
337
338	if (flags & ABX8XX_OSC_ACAL_512)
339	autocalibration = 512;
340	else if (flags & ABX8XX_OSC_ACAL_1024)
341	autocalibration = 1024;
342	else
343	autocalibration = 0;
344
345	return autocalibration;
346	}
347
348	static struct rtc_time default_tm = { 0, 0, 0, 1, 1, 2000, 6, 0, 0 };
349
350	static int abx80x_rtc_reset(struct udevice *dev)
351	{
352	int ret = 0;
353
354	int autocalib = abx80x_rtc_get_autocalibration(dev);
355
356	if (autocalib != 0)
357	abx80x_rtc_set_autocalibration(dev, 0);
358
359	ret = abx80x_rtc_set_time(dev, &default_tm);
360	if (ret != 0) {
361	log_err("cannot set time to default_tm. error %d\n", ret);
362	return ret;
363	}
364
365	return ret;
366	}
367
368	static const struct rtc_ops abx80x_rtc_ops = {
369	.get = abx80x_rtc_read_time,
370	.set = abx80x_rtc_set_time,
546795b5 SA	371	.reset = abx80x_rtc_reset,
	372	.read = abx80x_rtc_read,
	373	.write = abx80x_rtc_write,
8d612ccd YCLP	374	};
	375
	376	static int abx80x_dt_trickle_cfg(struct udevice *dev)
	377	{
	378	const char *diode;
	379	int trickle_cfg = 0;
	380	int i, ret = 0;
	381	u32 tmp;
	382
	383	diode = ofnode_read_string(dev_ofnode(dev), "abracon,tc-diode");
	384	if (!diode)
	385	return ret;
	386
	387	if (!strcmp(diode, "standard")) {
	388	trickle_cfg \|= ABX8XX_TRICKLE_STANDARD_DIODE;
	389	} else if (!strcmp(diode, "schottky")) {
	390	trickle_cfg \|= ABX8XX_TRICKLE_SCHOTTKY_DIODE;
	391	} else {
	392	log_err("Invalid tc-diode value: %s\n", diode);
	393	return -EINVAL;
	394	}
	395
	396	ret = ofnode_read_u32(dev_ofnode(dev), "abracon,tc-resistor", &tmp);
	397	if (ret)
	398	return ret;
	399
	400	for (i = 0; i < sizeof(trickle_resistors); i++)
	401	if (trickle_resistors[i] == tmp)
	402	break;
	403
	404	if (i == sizeof(trickle_resistors)) {
	405	log_err("Invalid tc-resistor value: %u\n", tmp);
	406	return -EINVAL;
	407	}
	408
	409	return (trickle_cfg \| i);
	410	}
	411
	412	static int abx80x_probe(struct udevice *dev)
	413	{
	414	int i, data, err, trickle_cfg = -EINVAL;
	415	unsigned char buf[7];
	416	unsigned int part = dev->driver_data;
	417	unsigned int partnumber;
	418	unsigned int majrev, minrev;
	419	unsigned int lot;
	420	unsigned int wafer;
	421	unsigned int uid;
	422
	423	err = dm_i2c_read(dev, ABX8XX_REG_ID0, buf, sizeof(buf));
	424	if (err < 0) {
	425	log_err("Unable to read partnumber\n");
	426	return -EIO;
	427	}
	428
	429	partnumber = (buf[0] << 8) \| buf[1];
	430	majrev = buf[2] >> 3;
	431	minrev = buf[2] & 0x7;
	432	lot = ((buf[4] & 0x80) << 2) \| ((buf[6] & 0x80) << 1) \| buf[3];
	433	uid = ((buf[4] & 0x7f) << 8) \| buf[5];
	434	wafer = (buf[6] & 0x7c) >> 2;
	435	log_debug("model %04x, revision %u.%u, lot %x, wafer %x, uid %x\n",
	436	partnumber, majrev, minrev, lot, wafer, uid);
	437
438	data = dm_i2c_reg_read(dev, ABX8XX_REG_CTRL1);
439	if (data < 0) {
440	log_err("Unable to read control register\n");
441	return -EIO;
442	}
443
444	err = dm_i2c_reg_write(dev, ABX8XX_REG_CTRL1,
445	((data & ~(ABX8XX_CTRL_12_24 \|
446	ABX8XX_CTRL_ARST)) \|
447	ABX8XX_CTRL_WRITE));
448	if (err < 0) {
449	log_err("Unable to write control register\n");
450	return -EIO;
451	}
452
453	/* Configure RV1805 specifics */
454	if (part == RV1805) {
455	/*
456	* Avoid accidentally entering test mode. This can happen
457	* on the RV1805 in case the reserved bit 5 in control2
458	* register is set. RV-1805-C3 datasheet indicates that
459	* the bit should be cleared in section 11h - Control2.
460	*/
461	data = dm_i2c_reg_read(dev, ABX8XX_REG_CTRL2);
462	if (data < 0) {
463	log_err("Unable to read control2 register\n");
464	return -EIO;
465	}
466
467	err = dm_i2c_reg_write(dev, ABX8XX_REG_CTRL2,
468	data & ~ABX8XX_CTRL2_RSVD);
469	if (err < 0) {
470	log_err("Unable to write control2 register\n");
471	return -EIO;
472	}
473
474	/*
475	* Avoid extra power leakage. The RV1805 uses smaller
476	* 10pin package and the EXTI input is not present.
477	* Disable it to avoid leakage.
478	*/
479	data = dm_i2c_reg_read(dev, ABX8XX_REG_OUT_CTRL);
480	if (data < 0) {
481	log_err("Unable to read output control register\n");
482	return -EIO;
483	}
484
485	/*
486	* Write the configuration key register to enable access to
487	* the config2 register
488	*/
489	err = dm_i2c_reg_write(dev, ABX8XX_REG_CFG_KEY,
490	ABX8XX_CFG_KEY_MISC);
491	if (err < 0) {
492	log_err("Unable to write configuration key\n");
493	return -EIO;
494	}
495
496	err = dm_i2c_reg_write(dev, ABX8XX_REG_OUT_CTRL,
497	data \| ABX8XX_OUT_CTRL_EXDS);
498	if (err < 0) {
499	log_err("Unable to write output control register\n");
500	return -EIO;
501	}
502	}
503
504	/* part autodetection */
505	if (part == ABX80X) {
506	for (i = 0; abx80x_caps[i].pn; i++)
507	if (partnumber == abx80x_caps[i].pn)
508	break;
509	if (abx80x_caps[i].pn == 0) {
510	log_err("Unknown part: %04x\n", partnumber);
511	return -EINVAL;
512	}
513	part = i;
514	}
515
516	if (partnumber != abx80x_caps[part].pn) {
517	log_err("partnumber mismatch %04x != %04x\n",
518	partnumber, abx80x_caps[part].pn);
519	return -EINVAL;
520	}
521
522	if (abx80x_caps[part].has_tc)
523	trickle_cfg = abx80x_dt_trickle_cfg(dev);
524
525	if (trickle_cfg > 0) {
526	log_debug("Enabling trickle charger: %02x\n", trickle_cfg);
527	abx80x_enable_trickle_charger(dev, trickle_cfg);
528	}
529
530	err = dm_i2c_reg_write(dev, ABX8XX_REG_CD_TIMER_CTL, BIT(2));
531	if (err)
532	return err;
533
534	return 0;
535	}
536
537	static const struct udevice_id abx80x_of_match[] = {
538	{
539	.compatible = "abracon,abx80x",
540	.data = ABX80X
541	},
542	{
543	.compatible = "abracon,ab0801",
544	.data = AB0801
545	},
546	{
547	.compatible = "abracon,ab0803",
548	.data = AB0803
549	},
550	{
551	.compatible = "abracon,ab0804",
552	.data = AB0804
553	},
554	{
555	.compatible = "abracon,ab0805",
556	.data = AB0805
557	},
558	{
559	.compatible = "abracon,ab1801",
560	.data = AB1801
561	},
562	{
563	.compatible = "abracon,ab1803",
564	.data = AB1803
565	},
566	{
567	.compatible = "abracon,ab1804",
568	.data = AB1804
569	},
570	{
571	.compatible = "abracon,ab1805",
572	.data = AB1805
573	},
574	{
575	.compatible = "microcrystal,rv1805",
576	.data = RV1805
577	},
578	{ }
579	};
580
581	U_BOOT_DRIVER(abx80x_rtc) = {
582	.name = "rtc-abx80x",
583	.id = UCLASS_RTC,
584	.probe = abx80x_probe,
585	.of_match = abx80x_of_match,
586	.ops = &abx80x_rtc_ops,
587	};