projects / J-u-boot.git / blame
| Commit | Line | Data |
|---|---|---|
| 594cacf0 LFT |
1 | // SPDX-License-Identifier: GPL-2.0 |
| 2 | /* | |
| 3 | * Copyright (C) 2019 Intel Corporation <www.intel.com> | |
| 4 | * | |
| 5 | */ | |
| 6 | ||
| 691d719d | 7 | #include <init.h> |
| f7ae49fc | 8 | #include <log.h> |
| 594cacf0 LFT |
9 | #include <asm/io.h> |
| 10 | #include <asm/u-boot.h> | |
| 11 | #include <asm/utils.h> | |
| 12 | #include <common.h> | |
| db41d65a | 13 | #include <hang.h> |
| 594cacf0 LFT |
14 | #include <image.h> |
| 15 | #include <spl.h> | |
| 16 | #include <asm/arch/clock_manager.h> | |
| 17 | #include <asm/arch/firewall.h> | |
| 18 | #include <asm/arch/mailbox_s10.h> | |
| 19 | #include <asm/arch/misc.h> | |
| 20 | #include <asm/arch/reset_manager.h> | |
| 21 | #include <asm/arch/system_manager.h> | |
| 22 | #include <watchdog.h> | |
| 23 | #include <dm/uclass.h> | |
| 24 | ||
| 25 | DECLARE_GLOBAL_DATA_PTR; | |
| 26 | ||
| 27 | u32 spl_boot_device(void) | |
| 28 | { | |
| 29 | return BOOT_DEVICE_MMC1; | |
| 30 | } | |
| 31 | ||
| 32 | #ifdef CONFIG_SPL_MMC_SUPPORT | |
| e9759065 | 33 | u32 spl_mmc_boot_mode(const u32 boot_device) |
| 594cacf0 LFT |
34 | { |
| 35 | #if defined(CONFIG_SPL_FS_FAT) || defined(CONFIG_SPL_FS_EXT4) | |
| 36 | return MMCSD_MODE_FS; | |
| 37 | #else | |
| 38 | return MMCSD_MODE_RAW; | |
| 39 | #endif | |
| 40 | } | |
| 41 | #endif | |
| 42 | ||
| 43 | void board_init_f(ulong dummy) | |
| 44 | { | |
| 45 | int ret; | |
| 46 | struct udevice *dev; | |
| 47 | ||
| 48 | ret = spl_early_init(); | |
| 49 | if (ret) | |
| 50 | hang(); | |
| 51 | ||
| 52 | socfpga_get_managers_addr(); | |
| 53 | ||
| 594cacf0 LFT |
54 | /* Ensure watchdog is paused when debugging is happening */ |
| 55 | writel(SYSMGR_WDDBG_PAUSE_ALL_CPU, | |
| 56 | socfpga_get_sysmgr_addr() + SYSMGR_SOC64_WDDBG); | |
| 57 | ||
| 2473e13b | 58 | #ifdef CONFIG_HW_WATCHDOG |
| 594cacf0 LFT |
59 | /* Enable watchdog before initializing the HW */ |
| 60 | socfpga_per_reset(SOCFPGA_RESET(L4WD0), 1); | |
| 61 | socfpga_per_reset(SOCFPGA_RESET(L4WD0), 0); | |
| 62 | hw_watchdog_init(); | |
| 63 | #endif | |
| 64 | ||
| 65 | /* ensure all processors are not released prior Linux boot */ | |
| 66 | writeq(0, CPU_RELEASE_ADDR); | |
| 67 | ||
| 68 | timer_init(); | |
| 69 | ||
| 70 | sysmgr_pinmux_init(); | |
| 71 | ||
| 72 | ret = uclass_get_device(UCLASS_CLK, 0, &dev); | |
| 73 | if (ret) { | |
| 74 | debug("Clock init failed: %d\n", ret); | |
| 75 | hang(); | |
| 76 | } | |
| 77 | ||
| 78 | preloader_console_init(); | |
| b3e2d9fc | 79 | print_reset_info(); |
| 594cacf0 LFT |
80 | cm_print_clock_quick_summary(); |
| 81 | ||
| 82 | firewall_setup(); | |
| 83 | ret = uclass_get_device(UCLASS_CACHE, 0, &dev); | |
| 84 | if (ret) { | |
| 85 | debug("CCU init failed: %d\n", ret); | |
| 86 | hang(); | |
| 87 | } | |
| 88 | ||
| 89 | #if CONFIG_IS_ENABLED(ALTERA_SDRAM) | |
| 90 | ret = uclass_get_device(UCLASS_RAM, 0, &dev); | |
| 91 | if (ret) { | |
| 92 | debug("DRAM init failed: %d\n", ret); | |
| 93 | hang(); | |
| 94 | } | |
| 95 | #endif | |
| 96 | ||
| 97 | mbox_init(); | |
| 98 | ||
| 99 | #ifdef CONFIG_CADENCE_QSPI | |
| 100 | mbox_qspi_open(); | |
| 101 | #endif | |
| 102 | } |