[J-u-boot.git] / arch / x86 / cpu / apollolake / cpu.c

// SPDX-License-Identifier: GPL-2.0
/*
 * Copyright 2019 Google LLC
 */

#include <common.h>
#include <cpu.h>
#include <dm.h>
#include <log.h>
#include <acpi/acpigen.h>
#include <acpi/acpi_table.h>
#include <asm/cpu_common.h>
#include <asm/cpu_x86.h>
#include <asm/intel_acpi.h>
#include <asm/msr.h>
#include <dm/acpi.h>

#define CSTATE_RES(address_space, width, offset, address)		\
	{								\
	.space_id = address_space,					\
	.bit_width = width,						\
	.bit_offset = offset,						\
	.addrl = address,						\
	}

static struct acpi_cstate cstate_map[] = {
	{
		/* C1 */
		.ctype = 1,		/* ACPI C1 */
		.latency = 1,
		.power = 1000,
		.resource = {
			.space_id = ACPI_ADDRESS_SPACE_FIXED,
		},
	}, {
		.ctype = 2,		/* ACPI C2 */
		.latency = 50,
		.power = 10,
		.resource = {
			.space_id = ACPI_ADDRESS_SPACE_IO,
			.bit_width = 8,
			.addrl = 0x415,
		},
	}, {
		.ctype = 3,		/* ACPI C3 */
		.latency = 150,
		.power = 10,
		.resource = {
			.space_id = ACPI_ADDRESS_SPACE_IO,
			.bit_width = 8,
			.addrl = 0x419,
		},
	},
};

static int apl_get_info(const struct udevice *dev, struct cpu_info *info)
{
	return cpu_intel_get_info(info, INTEL_BCLK_MHZ);
}

static int acpi_cpu_fill_ssdt(const struct udevice *dev, struct acpi_ctx *ctx)
{
	uint core_id = dev->req_seq;
	int cores_per_package;
	int ret;

	cores_per_package = cpu_get_cores_per_package();
	ret = acpi_generate_cpu_header(ctx, core_id, cstate_map,
				       ARRAY_SIZE(cstate_map));

	/* Generate P-state tables */
	generate_p_state_entries(ctx, core_id, cores_per_package);

	/* Generate T-state tables */
	generate_t_state_entries(ctx, core_id, cores_per_package, NULL, 0);

	acpigen_pop_len(ctx);

	if (device_is_last_sibling(dev)) {
		ret = acpi_generate_cpu_package_final(ctx, cores_per_package);

		if (ret)
			return ret;
	}

	return 0;
}

struct acpi_ops apl_cpu_acpi_ops = {
	.fill_ssdt	= acpi_cpu_fill_ssdt,
};

static const struct cpu_ops cpu_x86_apl_ops = {
	.get_desc	= cpu_x86_get_desc,
	.get_info	= apl_get_info,
	.get_count	= cpu_x86_get_count,
	.get_vendor	= cpu_x86_get_vendor,
};

static const struct udevice_id cpu_x86_apl_ids[] = {
	{ .compatible = "intel,apl-cpu" },
	{ }
};

U_BOOT_DRIVER(intel_apl_cpu) = {
	.name		= "intel_apl_cpu",
	.id		= UCLASS_CPU,
	.of_match	= cpu_x86_apl_ids,
	.bind		= cpu_x86_bind,
	.ops		= &cpu_x86_apl_ops,
	ACPI_OPS_PTR(&apl_cpu_acpi_ops)
	.flags		= DM_FLAG_PRE_RELOC,
};
Commit	Line	Data
6a4c237a SG	1	// SPDX-License-Identifier: GPL-2.0
	2	/*
	3	* Copyright 2019 Google LLC
	4	*/
	5
	6	#include <common.h>
	7	#include <cpu.h>
	8	#include <dm.h>
60c02310 SG	9	#include <log.h>
	10	#include <acpi/acpigen.h>
	11	#include <acpi/acpi_table.h>
6a4c237a SG	12	#include <asm/cpu_common.h>
6a4c237a SG	13	#include <asm/cpu_x86.h>
60c02310 SG	14	#include <asm/intel_acpi.h>
	15	#include <asm/msr.h>
	16	#include <dm/acpi.h>
	17
	18	#define CSTATE_RES(address_space, width, offset, address) \
	19	{ \
	20	.space_id = address_space, \
	21	.bit_width = width, \
	22	.bit_offset = offset, \
	23	.addrl = address, \
	24	}
	25
	26	static struct acpi_cstate cstate_map[] = {
	27	{
	28	/* C1 */
	29	.ctype = 1, /* ACPI C1 */
	30	.latency = 1,
	31	.power = 1000,
	32	.resource = {
	33	.space_id = ACPI_ADDRESS_SPACE_FIXED,
	34	},
	35	}, {
	36	.ctype = 2, /* ACPI C2 */
	37	.latency = 50,
	38	.power = 10,
	39	.resource = {
	40	.space_id = ACPI_ADDRESS_SPACE_IO,
	41	.bit_width = 8,
	42	.addrl = 0x415,
	43	},
	44	}, {
	45	.ctype = 3, /* ACPI C3 */
	46	.latency = 150,
	47	.power = 10,
	48	.resource = {
	49	.space_id = ACPI_ADDRESS_SPACE_IO,
	50	.bit_width = 8,
	51	.addrl = 0x419,
	52	},
	53	},
	54	};
6a4c237a	55
961420fa	56	static int apl_get_info(const struct udevice dev, struct cpu_info info)
6a4c237a SG	57	{
	58	return cpu_intel_get_info(info, INTEL_BCLK_MHZ);
	59	}
	60
60c02310 SG	61	static int acpi_cpu_fill_ssdt(const struct udevice dev, struct acpi_ctx ctx)
	62	{
	63	uint core_id = dev->req_seq;
	64	int cores_per_package;
	65	int ret;
	66
	67	cores_per_package = cpu_get_cores_per_package();
	68	ret = acpi_generate_cpu_header(ctx, core_id, cstate_map,
	69	ARRAY_SIZE(cstate_map));
	70
	71	/* Generate P-state tables */
	72	generate_p_state_entries(ctx, core_id, cores_per_package);
	73
	74	/* Generate T-state tables */
	75	generate_t_state_entries(ctx, core_id, cores_per_package, NULL, 0);
	76
	77	acpigen_pop_len(ctx);
	78
	79	if (device_is_last_sibling(dev)) {
	80	ret = acpi_generate_cpu_package_final(ctx, cores_per_package);
	81
	82	if (ret)
	83	return ret;
	84	}
	85
	86	return 0;
	87	}
	88
	89	struct acpi_ops apl_cpu_acpi_ops = {
	90	.fill_ssdt = acpi_cpu_fill_ssdt,
	91	};
	92
6a4c237a SG	93	static const struct cpu_ops cpu_x86_apl_ops = {
	94	.get_desc = cpu_x86_get_desc,
	95	.get_info = apl_get_info,
2c64d11e	96	.get_count = cpu_x86_get_count,
6a4c237a SG	97	.get_vendor = cpu_x86_get_vendor,
	98	};
	99
	100	static const struct udevice_id cpu_x86_apl_ids[] = {
	101	{ .compatible = "intel,apl-cpu" },
	102	{ }
	103	};
	104
9d20db04 SG	105	U_BOOT_DRIVER(intel_apl_cpu) = {
9d20db04 SG	106	.name = "intel_apl_cpu",
6a4c237a SG	107	.id = UCLASS_CPU,
	108	.of_match = cpu_x86_apl_ids,
	109	.bind = cpu_x86_bind,
	110	.ops = &cpu_x86_apl_ops,
60c02310	111	ACPI_OPS_PTR(&apl_cpu_acpi_ops)
6a4c237a SG	112	.flags = DM_FLAG_PRE_RELOC,
6a4c237a SG	113	};