[J-u-boot.git] / include / configs / MPC8260ADS.h

/*
 * (C) Copyright 2001
 * Stuart Hughes <[email protected]>
 * This file is based on similar values for other boards found in other
 * U-Boot config files, and some that I found in the mpc8260ads manual.
 *
 * Note: my board is a PILOT rev.
 * Note: the mpc8260ads doesn't come with a proper Ethernet MAC address.
 *
 * (C) Copyright 2003-2004 Arabella Software Ltd.
 * Yuli Barcohen <[email protected]>
 * Added support for SDRAM DIMMs SPD EEPROM, MII, JFFS2.
 * Ported to PQ2FADS-ZU and PQ2FADS-VR boards.
 * Ported to MPC8272ADS board.
 *
 * See file CREDITS for list of people who contributed to this
 * project.
 *
 * This program is free software; you can redistribute it and/or
 * modify it under the terms of the GNU General Public License as
 * published by the Free Software Foundation; either version 2 of
 * the License, or (at your option) any later version.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
 * GNU General Public License for more details.
 *
 * You should have received a copy of the GNU General Public License
 * along with this program; if not, write to the Free Software
 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
 * MA 02111-1307 USA
 */

#ifndef __CONFIG_H
#define __CONFIG_H

/*
 * High Level Configuration Options
 * (easy to change)
 */

#define CONFIG_MPC8260ADS	1	/* Motorola PQ2 ADS family board */

#define CONFIG_CPM2		1	/* Has a CPM2 */

/*
 * Figure out if we are booting low via flash HRCW or high via the BCSR.
 */
#if (TEXT_BASE != 0xFFF00000)		/* Boot low (flash HRCW) */
#   define CFG_LOWBOOT          1
#endif


/* ADS flavours */
#define CFG_8260ADS		1	/* MPC8260ADS */
#define CFG_8266ADS		2	/* MPC8266ADS */
#define CFG_PQ2FADS		3	/* PQ2FADS-ZU or PQ2FADS-VR */
#define CFG_8272ADS		4	/* MPC8272ADS */

#ifndef CONFIG_ADSTYPE
#define CONFIG_ADSTYPE		CFG_8260ADS
#endif /* CONFIG_ADSTYPE */

#if CONFIG_ADSTYPE == CFG_8272ADS
#define CONFIG_MPC8272		1
#else
#define CONFIG_MPC8260		1
#endif /* CONFIG_ADSTYPE == CFG_8272ADS */

#define CONFIG_BOARD_EARLY_INIT_F 1	/* Call board_early_init_f	*/

/* allow serial and ethaddr to be overwritten */
#define CONFIG_ENV_OVERWRITE

/*
 * select serial console configuration
 *
 * if either CONFIG_CONS_ON_SMC or CONFIG_CONS_ON_SCC is selected, then
 * CONFIG_CONS_INDEX must be set to the channel number (1-2 for SMC, 1-4
 * for SCC).
 *
 * if CONFIG_CONS_NONE is defined, then the serial console routines must
 * defined elsewhere (for example, on the cogent platform, there are serial
 * ports on the motherboard which are used for the serial console - see
 * cogent/cma101/serial.[ch]).
 */
#undef	CONFIG_CONS_ON_SMC		/* define if console on SMC */
#define CONFIG_CONS_ON_SCC		/* define if console on SCC */
#undef	CONFIG_CONS_NONE		/* define if console on something else */
#define CONFIG_CONS_INDEX	1	/* which serial channel for console */

/*
 * select ethernet configuration
 *
 * if either CONFIG_ETHER_ON_SCC or CONFIG_ETHER_ON_FCC is selected, then
 * CONFIG_ETHER_INDEX must be set to the channel number (1-4 for SCC, 1-3
 * for FCC)
 *
 * if CONFIG_ETHER_NONE is defined, then either the ethernet routines must be
 * defined elsewhere (as for the console), or CFG_CMD_NET must be removed
 * from CONFIG_COMMANDS to remove support for networking.
 */
#undef	CONFIG_ETHER_ON_SCC		/* define if ether on SCC   */
#define CONFIG_ETHER_ON_FCC		/* define if ether on FCC   */
#undef	CONFIG_ETHER_NONE		/* define if ether on something else */

#ifdef CONFIG_ETHER_ON_FCC

#define CONFIG_ETHER_INDEX	2	/* which SCC/FCC channel for ethernet */

#if   CONFIG_ETHER_INDEX == 1

# define CFG_PHY_ADDR		0
# define CFG_CMXFCR_VALUE	(CMXFCR_RF1CS_CLK11 | CMXFCR_TF1CS_CLK10)
# define CFG_CMXFCR_MASK	(CMXFCR_FC1 | CMXFCR_RF1CS_MSK | CMXFCR_TF1CS_MSK)

#elif CONFIG_ETHER_INDEX == 2

#if CONFIG_ADSTYPE == CFG_8272ADS	/* RxCLK is CLK15, TxCLK is CLK16 */
# define CFG_PHY_ADDR		3
# define CFG_CMXFCR_VALUE	(CMXFCR_RF2CS_CLK15 | CMXFCR_TF2CS_CLK16)
#else					/* RxCLK is CLK13, TxCLK is CLK14 */
# define CFG_PHY_ADDR		0
# define CFG_CMXFCR_VALUE	(CMXFCR_RF2CS_CLK13 | CMXFCR_TF2CS_CLK14)
#endif /* CONFIG_ADSTYPE == CFG_8272ADS */

# define CFG_CMXFCR_MASK	(CMXFCR_FC2 | CMXFCR_RF2CS_MSK | CMXFCR_TF2CS_MSK)

#endif	/* CONFIG_ETHER_INDEX */

#define CFG_CPMFCR_RAMTYPE	0		/* BDs and buffers on 60x bus */
#define CFG_FCC_PSMR		(FCC_PSMR_FDE | FCC_PSMR_LPB)  /* Full duplex */

#define CONFIG_MII			/* MII PHY management		*/
#define CONFIG_BITBANGMII		/* bit-bang MII PHY management	*/
/*
 * GPIO pins used for bit-banged MII communications
 */
#define MDIO_PORT	2		/* Port C */

#if CONFIG_ADSTYPE == CFG_8272ADS
#define CFG_MDIO_PIN	0x00002000	/* PC18 */
#define CFG_MDC_PIN	0x00001000	/* PC19 */
#else
#define CFG_MDIO_PIN	0x00400000	/* PC9  */
#define CFG_MDC_PIN	0x00200000	/* PC10 */
#endif /* CONFIG_ADSTYPE == CFG_8272ADS */

#define MDIO_ACTIVE	(iop->pdir |=  CFG_MDIO_PIN)
#define MDIO_TRISTATE	(iop->pdir &= ~CFG_MDIO_PIN)
#define MDIO_READ	((iop->pdat &  CFG_MDIO_PIN) != 0)

#define MDIO(bit)	if(bit) iop->pdat |=  CFG_MDIO_PIN; \
			else	iop->pdat &= ~CFG_MDIO_PIN

#define MDC(bit)	if(bit) iop->pdat |=  CFG_MDC_PIN; \
			else	iop->pdat &= ~CFG_MDC_PIN

#define MIIDELAY	udelay(1)

#endif /* CONFIG_ETHER_ON_FCC */

#if CONFIG_ADSTYPE >= CFG_PQ2FADS
#undef CONFIG_SPD_EEPROM	/* On new boards, SDRAM is soldered */
#else
#define CONFIG_HARD_I2C		1	/* To enable I2C support	*/
#define CFG_I2C_SPEED		100000	/* I2C speed and slave address	*/
#define CFG_I2C_SLAVE		0x7F

#if defined(CONFIG_SPD_EEPROM) && !defined(CONFIG_SPD_ADDR)
#define CONFIG_SPD_ADDR         0x50
#endif
#endif /* CONFIG_ADSTYPE >= CFG_PQ2FADS */

#ifndef CONFIG_SDRAM_PBI
#define CONFIG_SDRAM_PBI        0 /* By default, use bank-based interleaving */
#endif

#ifndef CONFIG_8260_CLKIN
#if CONFIG_ADSTYPE >= CFG_PQ2FADS
#define CONFIG_8260_CLKIN	100000000	/* in Hz */
#else
#define CONFIG_8260_CLKIN	66000000	/* in Hz */
#endif
#endif

#define CONFIG_BAUDRATE		115200

#define CFG_EXCLUDE		CFG_CMD_BEDBUG | \
				CFG_CMD_BMP	| \
				CFG_CMD_BSP	| \
				CFG_CMD_DATE	| \
				CFG_CMD_DOC	| \
				CFG_CMD_DTT	| \
				CFG_CMD_EEPROM | \
				CFG_CMD_ELF    | \
				CFG_CMD_EXT2	| \
				CFG_CMD_FAT    | \
				CFG_CMD_FDC	| \
				CFG_CMD_FDOS	| \
				CFG_CMD_HWFLOW	| \
				CFG_CMD_IDE	| \
				CFG_CMD_KGDB	| \
				CFG_CMD_MMC	| \
				CFG_CMD_NAND	| \
				CFG_CMD_PCI	| \
				CFG_CMD_PCMCIA | \
				CFG_CMD_REISER	| \
				CFG_CMD_SCSI	| \
				CFG_CMD_SPI	| \
				CFG_CMD_SNTP	| \
				CFG_CMD_UNIVERSE | \
				CFG_CMD_USB	| \
				CFG_CMD_VFD	| \
				CFG_CMD_XIMG

#if CONFIG_ADSTYPE >= CFG_PQ2FADS
#define CONFIG_COMMANDS		(CFG_CMD_ALL & ~( \
				 CFG_CMD_SDRAM	| \
				 CFG_CMD_I2C	| \
				 CFG_EXCLUDE	) )
#else
#define CONFIG_COMMANDS		(CFG_CMD_ALL & ~( \
				 CFG_EXCLUDE	) )
#endif /* CONFIG_ADSTYPE >= CFG_PQ2FADS */

/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
#include <cmd_confdefs.h>

#define CONFIG_BOOTDELAY	5		/* autoboot after 5 seconds */
#define CONFIG_BOOTCOMMAND	"bootm fff80000"	/* autoboot command */
#define CONFIG_BOOTARGS		"root=/dev/mtdblock2"

#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
#undef	CONFIG_KGDB_ON_SMC		/* define if kgdb on SMC */
#define CONFIG_KGDB_ON_SCC		/* define if kgdb on SCC */
#undef	CONFIG_KGDB_NONE		/* define if kgdb on something else */
#define CONFIG_KGDB_INDEX	2	/* which serial channel for kgdb */
#define CONFIG_KGDB_BAUDRATE	115200	/* speed to run kgdb serial port at */
#endif

#define CONFIG_BZIP2	/* include support for bzip2 compressed images */
#undef	CONFIG_WATCHDOG	/* disable platform specific watchdog */

/*
 * Miscellaneous configurable options
 */
#define CFG_HUSH_PARSER
#define CFG_PROMPT_HUSH_PS2 "> "
#define CFG_LONGHELP			/* undef to save memory	    */
#define CFG_PROMPT	"=> "		/* Monitor Command Prompt   */
#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
#define CFG_CBSIZE	1024		/* Console I/O Buffer Size  */
#else
#define CFG_CBSIZE	256			/* Console I/O Buffer Size  */
#endif
#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16)	/* Print Buffer Size */
#define CFG_MAXARGS	16			/* max number of command args	*/
#define CFG_BARGSIZE	CFG_CBSIZE	/* Boot Argument Buffer Size	*/

#define CFG_MEMTEST_START	0x00100000	/* memtest works on */
#define CFG_MEMTEST_END		0x00f00000	/* 1 ... 15 MB in DRAM	*/

#define CFG_LOAD_ADDR		0x400000	/* default load address */

#define CFG_HZ			1000	/* decrementer freq: 1 ms ticks */

#define CFG_BAUDRATE_TABLE	{ 9600, 19200, 38400, 57600, 115200, 230400 }

#define CFG_FLASH_BASE		0xff800000
#define CFG_MAX_FLASH_BANKS	1	/* max num of memory banks	*/
#define CFG_MAX_FLASH_SECT	32	/* max num of sects on one chip */
#define CFG_FLASH_SIZE		8
#define CFG_FLASH_ERASE_TOUT	8000	/* Timeout for Flash Erase (in ms)    */
#define CFG_FLASH_WRITE_TOUT	5	/* Timeout for Flash Write (in ms)    */
#define CFG_FLASH_LOCK_TOUT	5	/* Timeout for Flash Set Lock Bit (in ms) */
#define CFG_FLASH_UNLOCK_TOUT	10000	/* Timeout for Flash Clear Lock Bits (in ms) */
#define CFG_FLASH_PROTECTION		/* "Real" (hardware) sectors protection */

#define CFG_JFFS2_FIRST_SECTOR  1
#define CFG_JFFS2_LAST_SECTOR   27
#define CFG_JFFS2_SORT_FRAGMENTS
#define CFG_JFFS_CUSTOM_PART

/* this is stuff came out of the Motorola docs */
#ifndef CFG_LOWBOOT
#define CFG_DEFAULT_IMMR	0x0F010000
#endif

#define CFG_IMMR		0xF0000000
#define CFG_BCSR		0xF4500000
#define CFG_SDRAM_BASE		0x00000000
#define CFG_LSDRAM_BASE		0xFD000000

#define RS232EN_1		0x02000002
#define RS232EN_2		0x01000001
#define FETHIEN1		0x08000008
#define FETH1_RST		0x04000004
#define FETHIEN2		0x10000000
#define FETH2_RST		0x08000000
#define BCSR_PCI_MODE		0x01000000

#define CFG_INIT_RAM_ADDR	CFG_IMMR
#define CFG_INIT_RAM_END	0x2000	/* End of used area in DPRAM	*/
#define CFG_GBL_DATA_SIZE	128	/* size in bytes reserved for initial data */
#define CFG_GBL_DATA_OFFSET	(CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
#define CFG_INIT_SP_OFFSET	CFG_GBL_DATA_OFFSET


#ifdef CFG_LOWBOOT
/* PQ2FADS flash HRCW = 0x0EB4B645 */
#define CFG_HRCW_MASTER (   ( HRCW_BPS11 | HRCW_CIP )			    |\
			    ( HRCW_L2CPC10 | HRCW_DPPC11 | HRCW_ISB100 )    |\
			    ( HRCW_BMS | HRCW_MMR11 | HRCW_LBPC01 | HRCW_APPC10 ) |\
			    ( HRCW_CS10PC01 | HRCW_MODCK_H0101 )	     \
			)
#else
/* PQ2FADS BCSR HRCW = 0x0CB23645 */
#define CFG_HRCW_MASTER (   ( HRCW_BPS11 | HRCW_CIP )			    |\
			    ( HRCW_L2CPC10 | HRCW_DPPC10 | HRCW_ISB010 )    |\
			    ( HRCW_BMS | HRCW_APPC10 )			    |\
			    ( HRCW_MODCK_H0101 )			     \
			)
#endif
/* no slaves */
#define CFG_HRCW_SLAVE1 0
#define CFG_HRCW_SLAVE2 0
#define CFG_HRCW_SLAVE3 0
#define CFG_HRCW_SLAVE4 0
#define CFG_HRCW_SLAVE5 0
#define CFG_HRCW_SLAVE6 0
#define CFG_HRCW_SLAVE7 0

#define BOOTFLAG_COLD	0x01	/* Normal Power-On: Boot from FLASH  */
#define BOOTFLAG_WARM	0x02	/* Software reboot	     */

#define CFG_MONITOR_BASE    TEXT_BASE
#if (CFG_MONITOR_BASE < CFG_FLASH_BASE)
#   define CFG_RAMBOOT
#endif

#define CFG_MONITOR_LEN		(256 << 10)	/* Reserve 256 kB for Monitor	*/
#define CFG_BOOTMAPSZ		(8 << 20)	/* Initial Memory map for Linux */

#ifdef CONFIG_BZIP2
#define CFG_MALLOC_LEN		(4096 << 10)	/* Reserve 4 MB for malloc()	*/
#else
#define CFG_MALLOC_LEN		(128 << 10)	/* Reserve 128 KB for malloc()	*/
#endif /* CONFIG_BZIP2 */

#ifndef CFG_RAMBOOT
#  define CFG_ENV_IS_IN_FLASH	1
#  define CFG_ENV_SECT_SIZE	0x40000
#  define CFG_ENV_ADDR		(CFG_MONITOR_BASE + CFG_ENV_SECT_SIZE)
#else
#  define CFG_ENV_IS_IN_NVRAM	1
#  define CFG_ENV_ADDR		(CFG_MONITOR_BASE - 0x1000)
#  define CFG_ENV_SIZE		0x200
#endif /* CFG_RAMBOOT */


#define CFG_CACHELINE_SIZE	32	/* For MPC8260 CPU */
#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
#  define CFG_CACHELINE_SHIFT	5	/* log base 2 of the above value */
#endif


#define CFG_HID0_INIT		0
#define CFG_HID0_FINAL		(HID0_ICE | HID0_IFEM | HID0_ABE )

#define CFG_HID2		0

#define CFG_SYPCR		0xFFFFFFC3
#define CFG_BCR			0x100C0000
#define CFG_SIUMCR		0x0A200000
#define CFG_SCCR		SCCR_DFBRG01
#define CFG_BR0_PRELIM		CFG_FLASH_BASE | 0x00001801
#define CFG_OR0_PRELIM		0xFF800876
#define CFG_BR1_PRELIM		CFG_BCSR | 0x00001801
#define CFG_OR1_PRELIM		0xFFFF8010

#define CFG_RMR			RMR_CSRE
#define CFG_TMCNTSC		(TMCNTSC_SEC|TMCNTSC_ALR|TMCNTSC_TCF|TMCNTSC_TCE)
#define CFG_PISCR		(PISCR_PS|PISCR_PTF|PISCR_PTE)
#define CFG_RCCR		0

#if (CONFIG_ADSTYPE == CFG_8266ADS) || (CONFIG_ADSTYPE == CFG_8272ADS)
#undef CFG_LSDRAM_BASE		/* No local bus SDRAM on these boards */
#endif /* CONFIG_ADSTYPE == CFG_8266ADS */

#if CONFIG_ADSTYPE == CFG_PQ2FADS
#define CFG_OR2			0xFE002EC0
#define CFG_PSDMR		0x824B36A3
#define CFG_PSRT		0x13
#define CFG_LSDMR		0x828737A3
#define CFG_LSRT		0x13
#define CFG_MPTPR		0x2800
#elif CONFIG_ADSTYPE == CFG_8272ADS
#define CFG_OR2			0xFC002CC0
#define CFG_PSDMR		0x834E24A3
#define CFG_PSRT		0x13
#define CFG_MPTPR		0x2800
#else
#define CFG_OR2			0xFF000CA0
#define CFG_PSDMR		0x016EB452
#define CFG_PSRT		0x21
#define CFG_LSDMR		0x0086A522
#define CFG_LSRT		0x21
#define CFG_MPTPR		0x1900
#endif /* CONFIG_ADSTYPE == CFG_PQ2FADS */

#define CFG_RESET_ADDRESS	0x04400000

#endif /* __CONFIG_H */
Commit	Line	Data
e2211743 WD	1	/*
	2	* (C) Copyright 2001
	3	* Stuart Hughes <[email protected]>
	4	* This file is based on similar values for other boards found in other
	5	* U-Boot config files, and some that I found in the mpc8260ads manual.
	6	*
	7	* Note: my board is a PILOT rev.
	8	* Note: the mpc8260ads doesn't come with a proper Ethernet MAC address.
	9	*
04a85b3b	10	* (C) Copyright 2003-2004 Arabella Software Ltd.
cceb871f	11	* Yuli Barcohen <[email protected]>
2535d602	12	* Added support for SDRAM DIMMs SPD EEPROM, MII, JFFS2.
ef5a9672	13	* Ported to PQ2FADS-ZU and PQ2FADS-VR boards.
04a85b3b	14	* Ported to MPC8272ADS board.
cceb871f	15	*
e2211743 WD	16	* See file CREDITS for list of people who contributed to this
	17	* project.
	18	*
	19	* This program is free software; you can redistribute it and/or
	20	* modify it under the terms of the GNU General Public License as
	21	* published by the Free Software Foundation; either version 2 of
	22	* the License, or (at your option) any later version.
	23	*
	24	* This program is distributed in the hope that it will be useful,
	25	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	26	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	27	* GNU General Public License for more details.
	28	*
	29	* You should have received a copy of the GNU General Public License
	30	* along with this program; if not, write to the Free Software
	31	* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
	32	* MA 02111-1307 USA
	33	*/
	34
e2211743 WD	35	#ifndef __CONFIG_H
	36	#define __CONFIG_H
	37
	38	/*
	39	* High Level Configuration Options
	40	* (easy to change)
	41	*/
	42
04a85b3b	43	#define CONFIG_MPC8260ADS 1 /* Motorola PQ2 ADS family board */
e2211743	44
9c4c5ae3 JL	45	#define CONFIG_CPM2 1 /* Has a CPM2 */
9c4c5ae3 JL	46
901787d6 WD	47	/*
	48	* Figure out if we are booting low via flash HRCW or high via the BCSR.
	49	*/
	50	#if (TEXT_BASE != 0xFFF00000) /* Boot low (flash HRCW) */
	51	# define CFG_LOWBOOT 1
	52	#endif
	53
	54
2535d602 WD	55	/* ADS flavours */
	56	#define CFG_8260ADS 1 /* MPC8260ADS */
	57	#define CFG_8266ADS 2 /* MPC8266ADS */
ef5a9672	58	#define CFG_PQ2FADS 3 /* PQ2FADS-ZU or PQ2FADS-VR */
04a85b3b	59	#define CFG_8272ADS 4 /* MPC8272ADS */
2535d602 WD	60
	61	#ifndef CONFIG_ADSTYPE
	62	#define CONFIG_ADSTYPE CFG_8260ADS
	63	#endif /* CONFIG_ADSTYPE */
	64
04a85b3b WD	65	#if CONFIG_ADSTYPE == CFG_8272ADS
	66	#define CONFIG_MPC8272 1
	67	#else
	68	#define CONFIG_MPC8260 1
	69	#endif /* CONFIG_ADSTYPE == CFG_8272ADS */
	70
c837dcb1	71	#define CONFIG_BOARD_EARLY_INIT_F 1 /* Call board_early_init_f */
e2211743 WD	72
	73	/* allow serial and ethaddr to be overwritten */
	74	#define CONFIG_ENV_OVERWRITE
	75
	76	/*
	77	* select serial console configuration
	78	*
	79	* if either CONFIG_CONS_ON_SMC or CONFIG_CONS_ON_SCC is selected, then
	80	* CONFIG_CONS_INDEX must be set to the channel number (1-2 for SMC, 1-4
	81	* for SCC).
	82	*
	83	* if CONFIG_CONS_NONE is defined, then the serial console routines must
	84	* defined elsewhere (for example, on the cogent platform, there are serial
	85	* ports on the motherboard which are used for the serial console - see
	86	* cogent/cma101/serial.[ch]).
	87	*/
	88	#undef CONFIG_CONS_ON_SMC /* define if console on SMC */
	89	#define CONFIG_CONS_ON_SCC /* define if console on SCC */
	90	#undef CONFIG_CONS_NONE /* define if console on something else */
	91	#define CONFIG_CONS_INDEX 1 /* which serial channel for console */
	92
	93	/*
	94	* select ethernet configuration
	95	*
	96	* if either CONFIG_ETHER_ON_SCC or CONFIG_ETHER_ON_FCC is selected, then
	97	* CONFIG_ETHER_INDEX must be set to the channel number (1-4 for SCC, 1-3
	98	* for FCC)
	99	*
	100	* if CONFIG_ETHER_NONE is defined, then either the ethernet routines must be
	101	* defined elsewhere (as for the console), or CFG_CMD_NET must be removed
	102	* from CONFIG_COMMANDS to remove support for networking.
	103	*/
	104	#undef CONFIG_ETHER_ON_SCC /* define if ether on SCC */
	105	#define CONFIG_ETHER_ON_FCC /* define if ether on FCC */
	106	#undef CONFIG_ETHER_NONE /* define if ether on something else */
e2211743	107
48b42616	108	#ifdef CONFIG_ETHER_ON_FCC
e2211743	109
48b42616 WD	110	#define CONFIG_ETHER_INDEX 2 /* which SCC/FCC channel for ethernet */
48b42616 WD	111
04a85b3b WD	112	#if CONFIG_ETHER_INDEX == 1
	113
	114	# define CFG_PHY_ADDR 0
	115	# define CFG_CMXFCR_VALUE (CMXFCR_RF1CS_CLK11 \| CMXFCR_TF1CS_CLK10)
	116	# define CFG_CMXFCR_MASK (CMXFCR_FC1 \| CMXFCR_RF1CS_MSK \| CMXFCR_TF1CS_MSK)
	117
	118	#elif CONFIG_ETHER_INDEX == 2
	119
	120	#if CONFIG_ADSTYPE == CFG_8272ADS /* RxCLK is CLK15, TxCLK is CLK16 */
	121	# define CFG_PHY_ADDR 3
	122	# define CFG_CMXFCR_VALUE (CMXFCR_RF2CS_CLK15 \| CMXFCR_TF2CS_CLK16)
	123	#else /* RxCLK is CLK13, TxCLK is CLK14 */
	124	# define CFG_PHY_ADDR 0
e2211743	125	# define CFG_CMXFCR_VALUE (CMXFCR_RF2CS_CLK13 \| CMXFCR_TF2CS_CLK14)
04a85b3b WD	126	#endif /* CONFIG_ADSTYPE == CFG_8272ADS */
	127
	128	# define CFG_CMXFCR_MASK (CMXFCR_FC2 \| CMXFCR_RF2CS_MSK \| CMXFCR_TF2CS_MSK)
e2211743 WD	129
	130	#endif /* CONFIG_ETHER_INDEX */
	131
04a85b3b WD	132	#define CFG_CPMFCR_RAMTYPE 0 /* BDs and buffers on 60x bus */
	133	#define CFG_FCC_PSMR (FCC_PSMR_FDE \| FCC_PSMR_LPB) /* Full duplex */
	134
48b42616 WD	135	#define CONFIG_MII /* MII PHY management */
	136	#define CONFIG_BITBANGMII /* bit-bang MII PHY management */
	137	/*
	138	* GPIO pins used for bit-banged MII communications
	139	*/
	140	#define MDIO_PORT 2 /* Port C */
48b42616	141
04a85b3b WD	142	#if CONFIG_ADSTYPE == CFG_8272ADS
	143	#define CFG_MDIO_PIN 0x00002000 /* PC18 */
	144	#define CFG_MDC_PIN 0x00001000 /* PC19 */
	145	#else
	146	#define CFG_MDIO_PIN 0x00400000 /* PC9 */
	147	#define CFG_MDC_PIN 0x00200000 /* PC10 */
	148	#endif /* CONFIG_ADSTYPE == CFG_8272ADS */
	149
	150	#define MDIO_ACTIVE (iop->pdir \|= CFG_MDIO_PIN)
	151	#define MDIO_TRISTATE (iop->pdir &= ~CFG_MDIO_PIN)
	152	#define MDIO_READ ((iop->pdat & CFG_MDIO_PIN) != 0)
	153
	154	#define MDIO(bit) if(bit) iop->pdat \|= CFG_MDIO_PIN; \
	155	else iop->pdat &= ~CFG_MDIO_PIN
48b42616	156
04a85b3b WD	157	#define MDC(bit) if(bit) iop->pdat \|= CFG_MDC_PIN; \
04a85b3b WD	158	else iop->pdat &= ~CFG_MDC_PIN
48b42616 WD	159
	160	#define MIIDELAY udelay(1)
	161
	162	#endif /* CONFIG_ETHER_ON_FCC */
	163
04a85b3b WD	164	#if CONFIG_ADSTYPE >= CFG_PQ2FADS
04a85b3b WD	165	#undef CONFIG_SPD_EEPROM /* On new boards, SDRAM is soldered */
2535d602	166	#else
e2211743	167	#define CONFIG_HARD_I2C 1 /* To enable I2C support */
ef5a9672	168	#define CFG_I2C_SPEED 100000 /* I2C speed and slave address */
e2211743 WD	169	#define CFG_I2C_SLAVE 0x7F
e2211743 WD	170
db2f721f WD	171	#if defined(CONFIG_SPD_EEPROM) && !defined(CONFIG_SPD_ADDR)
	172	#define CONFIG_SPD_ADDR 0x50
	173	#endif
04a85b3b	174	#endif /* CONFIG_ADSTYPE >= CFG_PQ2FADS */
e2211743	175
db2f721f	176	#ifndef CONFIG_SDRAM_PBI
ef5a9672	177	#define CONFIG_SDRAM_PBI 0 /* By default, use bank-based interleaving */
db2f721f WD	178	#endif
	179
	180	#ifndef CONFIG_8260_CLKIN
04a85b3b	181	#if CONFIG_ADSTYPE >= CFG_PQ2FADS
2535d602 WD	182	#define CONFIG_8260_CLKIN 100000000 /* in Hz */
2535d602 WD	183	#else
ef5a9672	184	#define CONFIG_8260_CLKIN 66000000 /* in Hz */
db2f721f	185	#endif
2535d602 WD	186	#endif
2535d602 WD	187
e1599e83	188	#define CONFIG_BAUDRATE 115200
e2211743	189
414eec35 WD	190	#define CFG_EXCLUDE CFG_CMD_BEDBUG \| \
	191	CFG_CMD_BMP \| \
	192	CFG_CMD_BSP \| \
	193	CFG_CMD_DATE \| \
	194	CFG_CMD_DOC \| \
	195	CFG_CMD_DTT \| \
	196	CFG_CMD_EEPROM \| \
	197	CFG_CMD_ELF \| \
	198	CFG_CMD_EXT2 \| \
	199	CFG_CMD_FAT \| \
	200	CFG_CMD_FDC \| \
	201	CFG_CMD_FDOS \| \
	202	CFG_CMD_HWFLOW \| \
	203	CFG_CMD_IDE \| \
	204	CFG_CMD_KGDB \| \
	205	CFG_CMD_MMC \| \
	206	CFG_CMD_NAND \| \
	207	CFG_CMD_PCI \| \
	208	CFG_CMD_PCMCIA \| \
	209	CFG_CMD_REISER \| \
	210	CFG_CMD_SCSI \| \
	211	CFG_CMD_SPI \| \
	212	CFG_CMD_SNTP \| \
	213	CFG_CMD_UNIVERSE \| \
	214	CFG_CMD_USB \| \
	215	CFG_CMD_VFD \| \
	216	CFG_CMD_XIMG
2535d602	217
04a85b3b	218	#if CONFIG_ADSTYPE >= CFG_PQ2FADS
2535d602 WD	219	#define CONFIG_COMMANDS (CFG_CMD_ALL & ~( \
	220	CFG_CMD_SDRAM \| \
	221	CFG_CMD_I2C \| \
	222	CFG_EXCLUDE ) )
	223	#else
	224	#define CONFIG_COMMANDS (CFG_CMD_ALL & ~( \
	225	CFG_EXCLUDE ) )
04a85b3b	226	#endif /* CONFIG_ADSTYPE >= CFG_PQ2FADS */
e2211743 WD	227
	228	/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
	229	#include <cmd_confdefs.h>
	230
04a85b3b WD	231	#define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */
	232	#define CONFIG_BOOTCOMMAND "bootm fff80000" /* autoboot command */
	233	#define CONFIG_BOOTARGS "root=/dev/mtdblock2"
e2211743 WD	234
	235	#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
	236	#undef CONFIG_KGDB_ON_SMC /* define if kgdb on SMC */
	237	#define CONFIG_KGDB_ON_SCC /* define if kgdb on SCC */
	238	#undef CONFIG_KGDB_NONE /* define if kgdb on something else */
	239	#define CONFIG_KGDB_INDEX 2 /* which serial channel for kgdb */
	240	#define CONFIG_KGDB_BAUDRATE 115200 /* speed to run kgdb serial port at */
	241	#endif
	242
ef5a9672 WD	243	#define CONFIG_BZIP2 /* include support for bzip2 compressed images */
ef5a9672 WD	244	#undef CONFIG_WATCHDOG /* disable platform specific watchdog */
e2211743 WD	245
	246	/*
	247	* Miscellaneous configurable options
	248	*/
326428cc WD	249	#define CFG_HUSH_PARSER
326428cc WD	250	#define CFG_PROMPT_HUSH_PS2 "> "
e2211743 WD	251	#define CFG_LONGHELP /* undef to save memory */
	252	#define CFG_PROMPT "=> " /* Monitor Command Prompt */
	253	#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
	254	#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */
	255	#else
	256	#define CFG_CBSIZE 256 /* Console I/O Buffer Size */
	257	#endif
	258	#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
	259	#define CFG_MAXARGS 16 /* max number of command args */
	260	#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */
	261
	262	#define CFG_MEMTEST_START 0x00100000 /* memtest works on */
	263	#define CFG_MEMTEST_END 0x00f00000 /* 1 ... 15 MB in DRAM */
	264
901787d6	265	#define CFG_LOAD_ADDR 0x400000 /* default load address */
e2211743 WD	266
	267	#define CFG_HZ 1000 /* decrementer freq: 1 ms ticks */
	268
	269	#define CFG_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200, 230400 }
	270
	271	#define CFG_FLASH_BASE 0xff800000
e2211743 WD	272	#define CFG_MAX_FLASH_BANKS 1 /* max num of memory banks */
	273	#define CFG_MAX_FLASH_SECT 32 /* max num of sects on one chip */
	274	#define CFG_FLASH_SIZE 8
	275	#define CFG_FLASH_ERASE_TOUT 8000 /* Timeout for Flash Erase (in ms) */
	276	#define CFG_FLASH_WRITE_TOUT 5 /* Timeout for Flash Write (in ms) */
8564acf9 WD	277	#define CFG_FLASH_LOCK_TOUT 5 /* Timeout for Flash Set Lock Bit (in ms) */
	278	#define CFG_FLASH_UNLOCK_TOUT 10000 /* Timeout for Flash Clear Lock Bits (in ms) */
	279	#define CFG_FLASH_PROTECTION /* "Real" (hardware) sectors protection */
	280
	281	#define CFG_JFFS2_FIRST_SECTOR 1
	282	#define CFG_JFFS2_LAST_SECTOR 27
	283	#define CFG_JFFS2_SORT_FRAGMENTS
	284	#define CFG_JFFS_CUSTOM_PART
e2211743 WD	285
e2211743 WD	286	/* this is stuff came out of the Motorola docs */
901787d6	287	#ifndef CFG_LOWBOOT
e2211743	288	#define CFG_DEFAULT_IMMR 0x0F010000
901787d6	289	#endif
e2211743	290
5d232d0e	291	#define CFG_IMMR 0xF0000000
2535d602	292	#define CFG_BCSR 0xF4500000
e2211743	293	#define CFG_SDRAM_BASE 0x00000000
326428cc	294	#define CFG_LSDRAM_BASE 0xFD000000
e2211743 WD	295
	296	#define RS232EN_1 0x02000002
	297	#define RS232EN_2 0x01000001
2535d602 WD	298	#define FETHIEN1 0x08000008
2535d602 WD	299	#define FETH1_RST 0x04000004
04a85b3b	300	#define FETHIEN2 0x10000000
2535d602	301	#define FETH2_RST 0x08000000
326428cc	302	#define BCSR_PCI_MODE 0x01000000
e2211743 WD	303
e2211743 WD	304	#define CFG_INIT_RAM_ADDR CFG_IMMR
04a85b3b	305	#define CFG_INIT_RAM_END 0x2000 /* End of used area in DPRAM */
e2211743 WD	306	#define CFG_GBL_DATA_SIZE 128 /* size in bytes reserved for initial data */
	307	#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
	308	#define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET
	309
	310
901787d6 WD	311	#ifdef CFG_LOWBOOT
	312	/* PQ2FADS flash HRCW = 0x0EB4B645 */
	313	#define CFG_HRCW_MASTER ( ( HRCW_BPS11 \| HRCW_CIP ) \|\
	314	( HRCW_L2CPC10 \| HRCW_DPPC11 \| HRCW_ISB100 ) \|\
	315	( HRCW_BMS \| HRCW_MMR11 \| HRCW_LBPC01 \| HRCW_APPC10 ) \|\
	316	( HRCW_CS10PC01 \| HRCW_MODCK_H0101 ) \
	317	)
	318	#else
	319	/* PQ2FADS BCSR HRCW = 0x0CB23645 */
e2211743 WD	320	#define CFG_HRCW_MASTER ( ( HRCW_BPS11 \| HRCW_CIP ) \|\
	321	( HRCW_L2CPC10 \| HRCW_DPPC10 \| HRCW_ISB010 ) \|\
	322	( HRCW_BMS \| HRCW_APPC10 ) \|\
	323	( HRCW_MODCK_H0101 ) \
	324	)
901787d6	325	#endif
e2211743 WD	326	/* no slaves */
	327	#define CFG_HRCW_SLAVE1 0
	328	#define CFG_HRCW_SLAVE2 0
	329	#define CFG_HRCW_SLAVE3 0
	330	#define CFG_HRCW_SLAVE4 0
	331	#define CFG_HRCW_SLAVE5 0
	332	#define CFG_HRCW_SLAVE6 0
	333	#define CFG_HRCW_SLAVE7 0
	334
	335	#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */
	336	#define BOOTFLAG_WARM 0x02 /* Software reboot */
	337
	338	#define CFG_MONITOR_BASE TEXT_BASE
	339	#if (CFG_MONITOR_BASE < CFG_FLASH_BASE)
	340	# define CFG_RAMBOOT
	341	#endif
	342
	343	#define CFG_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */
e2211743 WD	344	#define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
e2211743 WD	345
ef5a9672 WD	346	#ifdef CONFIG_BZIP2
	347	#define CFG_MALLOC_LEN (4096 << 10) /* Reserve 4 MB for malloc() */
	348	#else
	349	#define CFG_MALLOC_LEN (128 << 10) /* Reserve 128 KB for malloc() */
	350	#endif /* CONFIG_BZIP2 */
	351
e2211743 WD	352	#ifndef CFG_RAMBOOT
e2211743 WD	353	# define CFG_ENV_IS_IN_FLASH 1
48b42616 WD	354	# define CFG_ENV_SECT_SIZE 0x40000
48b42616 WD	355	# define CFG_ENV_ADDR (CFG_MONITOR_BASE + CFG_ENV_SECT_SIZE)
e2211743 WD	356	#else
	357	# define CFG_ENV_IS_IN_NVRAM 1
	358	# define CFG_ENV_ADDR (CFG_MONITOR_BASE - 0x1000)
	359	# define CFG_ENV_SIZE 0x200
	360	#endif /* CFG_RAMBOOT */
	361
	362
	363	#define CFG_CACHELINE_SIZE 32 /* For MPC8260 CPU */
	364	#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
	365	# define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */
	366	#endif
	367
	368
	369	#define CFG_HID0_INIT 0
	370	#define CFG_HID0_FINAL (HID0_ICE \| HID0_IFEM \| HID0_ABE )
	371
	372	#define CFG_HID2 0
	373
	374	#define CFG_SYPCR 0xFFFFFFC3
	375	#define CFG_BCR 0x100C0000
	376	#define CFG_SIUMCR 0x0A200000
2535d602 WD	377	#define CFG_SCCR SCCR_DFBRG01
	378	#define CFG_BR0_PRELIM CFG_FLASH_BASE \| 0x00001801
	379	#define CFG_OR0_PRELIM 0xFF800876
	380	#define CFG_BR1_PRELIM CFG_BCSR \| 0x00001801
e2211743 WD	381	#define CFG_OR1_PRELIM 0xFFFF8010
e2211743 WD	382
2535d602	383	#define CFG_RMR RMR_CSRE
e2211743 WD	384	#define CFG_TMCNTSC (TMCNTSC_SEC\|TMCNTSC_ALR\|TMCNTSC_TCF\|TMCNTSC_TCE)
	385	#define CFG_PISCR (PISCR_PS\|PISCR_PTF\|PISCR_PTE)
	386	#define CFG_RCCR 0
2535d602	387
04a85b3b WD	388	#if (CONFIG_ADSTYPE == CFG_8266ADS) \|\| (CONFIG_ADSTYPE == CFG_8272ADS)
04a85b3b WD	389	#undef CFG_LSDRAM_BASE /* No local bus SDRAM on these boards */
326428cc WD	390	#endif /* CONFIG_ADSTYPE == CFG_8266ADS */
326428cc WD	391
2535d602	392	#if CONFIG_ADSTYPE == CFG_PQ2FADS
ef5a9672	393	#define CFG_OR2 0xFE002EC0
2535d602 WD	394	#define CFG_PSDMR 0x824B36A3
	395	#define CFG_PSRT 0x13
	396	#define CFG_LSDMR 0x828737A3
	397	#define CFG_LSRT 0x13
	398	#define CFG_MPTPR 0x2800
04a85b3b WD	399	#elif CONFIG_ADSTYPE == CFG_8272ADS
	400	#define CFG_OR2 0xFC002CC0
	401	#define CFG_PSDMR 0x834E24A3
	402	#define CFG_PSRT 0x13
	403	#define CFG_MPTPR 0x2800
2535d602	404	#else
ef5a9672	405	#define CFG_OR2 0xFF000CA0
e2211743	406	#define CFG_PSDMR 0x016EB452
2535d602 WD	407	#define CFG_PSRT 0x21
	408	#define CFG_LSDMR 0x0086A522
	409	#define CFG_LSRT 0x21
	410	#define CFG_MPTPR 0x1900
	411	#endif /* CONFIG_ADSTYPE == CFG_PQ2FADS */
e2211743 WD	412
	413	#define CFG_RESET_ADDRESS 0x04400000
	414
	415	#endif /* __CONFIG_H */