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1 | /* |
2 | * (C) Copyright 2003 Motorola Inc. | |
3 | * Xianghua Xiao ([email protected]) | |
4 | * Modified based on 8260 for 8560. | |
5 | * | |
6 | * (C) Copyright 2000 | |
7 | * Wolfgang Denk, DENX Software Engineering, [email protected]. | |
8 | * | |
9 | * See file CREDITS for list of people who contributed to this | |
10 | * project. | |
11 | * | |
12 | * This program is free software; you can redistribute it and/or | |
13 | * modify it under the terms of the GNU General Public License as | |
14 | * published by the Free Software Foundation; either version 2 of | |
15 | * the License, or (at your option) any later version. | |
16 | * | |
17 | * This program is distributed in the hope that it will be useful, | |
18 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
19 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
20 | * GNU General Public License for more details. | |
21 | * | |
22 | * You should have received a copy of the GNU General Public License | |
23 | * along with this program; if not, write to the Free Software | |
24 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, | |
25 | * MA 02111-1307 USA | |
26 | * | |
27 | * Hacked for MPC8260 by [email protected], 19-Oct-00. | |
28 | */ | |
29 | ||
30 | /* | |
31 | * Minimal serial functions needed to use one of the SCC ports | |
32 | * as serial console interface. | |
33 | */ | |
34 | ||
35 | #include <common.h> | |
36 | #include <asm/cpm_85xx.h> | |
37 | ||
9c4c5ae3 | 38 | #if defined(CONFIG_CPM2) |
42d1f039 WD |
39 | #if defined(CONFIG_CONS_ON_SCC) |
40 | ||
41 | #if CONFIG_CONS_INDEX == 1 /* Console on SCC1 */ | |
42 | ||
43 | #define SCC_INDEX 0 | |
44 | #define PROFF_SCC PROFF_SCC1 | |
45 | #define CMXSCR_MASK (CMXSCR_GR1|CMXSCR_SC1|\ | |
46 | CMXSCR_RS1CS_MSK|CMXSCR_TS1CS_MSK) | |
47 | #define CMXSCR_VALUE (CMXSCR_RS1CS_BRG1|CMXSCR_TS1CS_BRG1) | |
48 | #define CPM_CR_SCC_PAGE CPM_CR_SCC1_PAGE | |
49 | #define CPM_CR_SCC_SBLOCK CPM_CR_SCC1_SBLOCK | |
50 | ||
51 | #elif CONFIG_CONS_INDEX == 2 /* Console on SCC2 */ | |
52 | ||
53 | #define SCC_INDEX 1 | |
54 | #define PROFF_SCC PROFF_SCC2 | |
55 | #define CMXSCR_MASK (CMXSCR_GR2|CMXSCR_SC2|\ | |
56 | CMXSCR_RS2CS_MSK|CMXSCR_TS2CS_MSK) | |
57 | #define CMXSCR_VALUE (CMXSCR_RS2CS_BRG2|CMXSCR_TS2CS_BRG2) | |
58 | #define CPM_CR_SCC_PAGE CPM_CR_SCC2_PAGE | |
59 | #define CPM_CR_SCC_SBLOCK CPM_CR_SCC2_SBLOCK | |
60 | ||
61 | #elif CONFIG_CONS_INDEX == 3 /* Console on SCC3 */ | |
62 | ||
63 | #define SCC_INDEX 2 | |
64 | #define PROFF_SCC PROFF_SCC3 | |
65 | #define CMXSCR_MASK (CMXSCR_GR3|CMXSCR_SC3|\ | |
66 | CMXSCR_RS3CS_MSK|CMXSCR_TS3CS_MSK) | |
67 | #define CMXSCR_VALUE (CMXSCR_RS3CS_BRG3|CMXSCR_TS3CS_BRG3) | |
68 | #define CPM_CR_SCC_PAGE CPM_CR_SCC3_PAGE | |
69 | #define CPM_CR_SCC_SBLOCK CPM_CR_SCC3_SBLOCK | |
70 | ||
71 | #elif CONFIG_CONS_INDEX == 4 /* Console on SCC4 */ | |
72 | ||
73 | #define SCC_INDEX 3 | |
74 | #define PROFF_SCC PROFF_SCC4 | |
75 | #define CMXSCR_MASK (CMXSCR_GR4|CMXSCR_SC4|\ | |
76 | CMXSCR_RS4CS_MSK|CMXSCR_TS4CS_MSK) | |
77 | #define CMXSCR_VALUE (CMXSCR_RS4CS_BRG4|CMXSCR_TS4CS_BRG4) | |
78 | #define CPM_CR_SCC_PAGE CPM_CR_SCC4_PAGE | |
79 | #define CPM_CR_SCC_SBLOCK CPM_CR_SCC4_SBLOCK | |
80 | ||
81 | #else | |
82 | ||
83 | #error "console not correctly defined" | |
84 | ||
85 | #endif | |
86 | ||
87 | int serial_init (void) | |
88 | { | |
89 | volatile immap_t *im = (immap_t *)CFG_IMMR; | |
90 | volatile ccsr_cpm_scc_t *sp; | |
91 | volatile scc_uart_t *up; | |
92 | volatile cbd_t *tbdf, *rbdf; | |
93 | volatile ccsr_cpm_cp_t *cp = &(im->im_cpm.im_cpm_cp); | |
94 | uint dpaddr; | |
95 | ||
96 | /* initialize pointers to SCC */ | |
97 | ||
98 | sp = (ccsr_cpm_scc_t *) &(im->im_cpm.im_cpm_scc[SCC_INDEX]); | |
99 | up = (scc_uart_t *)&(im->im_cpm.im_dprambase[PROFF_SCC]); | |
100 | ||
101 | /* Disable transmitter/receiver. | |
102 | */ | |
103 | sp->gsmrl &= ~(SCC_GSMRL_ENR | SCC_GSMRL_ENT); | |
104 | ||
105 | /* put the SCC channel into NMSI (non multiplexd serial interface) | |
106 | * mode and wire the selected SCC Tx and Rx clocks to BRGx (15-15). | |
107 | */ | |
108 | im->im_cpm.im_cpm_mux.cmxscr = \ | |
109 | (im->im_cpm.im_cpm_mux.cmxscr&~CMXSCR_MASK)|CMXSCR_VALUE; | |
110 | ||
111 | /* Set up the baud rate generator. | |
112 | */ | |
113 | serial_setbrg (); | |
114 | ||
115 | /* Allocate space for two buffer descriptors in the DP ram. | |
116 | * damm: allocating space after the two buffers for rx/tx data | |
117 | */ | |
118 | ||
119 | dpaddr = m8560_cpm_dpalloc((2 * sizeof (cbd_t)) + 2, 16); | |
120 | ||
121 | /* Set the physical address of the host memory buffers in | |
122 | * the buffer descriptors. | |
123 | */ | |
124 | rbdf = (cbd_t *)&(im->im_cpm.im_dprambase[dpaddr]); | |
125 | rbdf->cbd_bufaddr = (uint) (rbdf+2); | |
126 | rbdf->cbd_sc = BD_SC_EMPTY | BD_SC_WRAP; | |
127 | tbdf = rbdf + 1; | |
128 | tbdf->cbd_bufaddr = ((uint) (rbdf+2)) + 1; | |
129 | tbdf->cbd_sc = BD_SC_WRAP; | |
130 | ||
131 | /* Set up the uart parameters in the parameter ram. | |
132 | */ | |
133 | up->scc_genscc.scc_rbase = dpaddr; | |
134 | up->scc_genscc.scc_tbase = dpaddr+sizeof(cbd_t); | |
135 | up->scc_genscc.scc_rfcr = CPMFCR_EB; | |
136 | up->scc_genscc.scc_tfcr = CPMFCR_EB; | |
137 | up->scc_genscc.scc_mrblr = 1; | |
138 | up->scc_maxidl = 0; | |
139 | up->scc_brkcr = 1; | |
140 | up->scc_parec = 0; | |
141 | up->scc_frmec = 0; | |
142 | up->scc_nosec = 0; | |
143 | up->scc_brkec = 0; | |
144 | up->scc_uaddr1 = 0; | |
145 | up->scc_uaddr2 = 0; | |
146 | up->scc_toseq = 0; | |
147 | up->scc_char1 = up->scc_char2 = up->scc_char3 = up->scc_char4 = 0x8000; | |
148 | up->scc_char5 = up->scc_char6 = up->scc_char7 = up->scc_char8 = 0x8000; | |
149 | up->scc_rccm = 0xc0ff; | |
150 | ||
151 | /* Mask all interrupts and remove anything pending. | |
152 | */ | |
153 | sp->sccm = 0; | |
154 | sp->scce = 0xffff; | |
155 | ||
156 | /* Set 8 bit FIFO, 16 bit oversampling and UART mode. | |
157 | */ | |
158 | sp->gsmrh = SCC_GSMRH_RFW; /* 8 bit FIFO */ | |
159 | sp->gsmrl = \ | |
160 | SCC_GSMRL_TDCR_16 | SCC_GSMRL_RDCR_16 | SCC_GSMRL_MODE_UART; | |
161 | ||
162 | /* Set CTS no flow control, 1 stop bit, 8 bit character length, | |
163 | * normal async UART mode, no parity | |
164 | */ | |
165 | sp->psmr = SCU_PSMR_CL; | |
166 | ||
167 | /* execute the "Init Rx and Tx params" CP command. | |
168 | */ | |
169 | ||
170 | while (cp->cpcr & CPM_CR_FLG) /* wait if cp is busy */ | |
171 | ; | |
172 | ||
173 | cp->cpcr = mk_cr_cmd(CPM_CR_SCC_PAGE, CPM_CR_SCC_SBLOCK, | |
174 | 0, CPM_CR_INIT_TRX) | CPM_CR_FLG; | |
175 | ||
176 | while (cp->cpcr & CPM_CR_FLG) /* wait if cp is busy */ | |
177 | ; | |
178 | ||
179 | /* Enable transmitter/receiver. | |
180 | */ | |
181 | sp->gsmrl |= SCC_GSMRL_ENR | SCC_GSMRL_ENT; | |
182 | ||
183 | return (0); | |
184 | } | |
185 | ||
186 | void | |
187 | serial_setbrg (void) | |
188 | { | |
189 | DECLARE_GLOBAL_DATA_PTR; | |
190 | ||
191 | #if defined(CONFIG_CONS_USE_EXTC) | |
192 | m8560_cpm_extcbrg(SCC_INDEX, gd->baudrate, | |
193 | CONFIG_CONS_EXTC_RATE, CONFIG_CONS_EXTC_PINSEL); | |
194 | #else | |
195 | m8560_cpm_setbrg(SCC_INDEX, gd->baudrate); | |
196 | #endif | |
197 | } | |
198 | ||
199 | void | |
200 | serial_putc(const char c) | |
201 | { | |
202 | volatile scc_uart_t *up; | |
203 | volatile cbd_t *tbdf; | |
204 | volatile immap_t *im; | |
205 | ||
206 | if (c == '\n') | |
207 | serial_putc ('\r'); | |
208 | ||
209 | im = (immap_t *)CFG_IMMR; | |
210 | up = (scc_uart_t *)&(im->im_cpm.im_dprambase[PROFF_SCC]); | |
211 | tbdf = (cbd_t *)&(im->im_cpm.im_dprambase[up->scc_genscc.scc_tbase]); | |
212 | ||
213 | /* Wait for last character to go. | |
214 | */ | |
215 | while (tbdf->cbd_sc & BD_SC_READY) | |
216 | ; | |
217 | ||
218 | /* Load the character into the transmit buffer. | |
219 | */ | |
220 | *(volatile char *)tbdf->cbd_bufaddr = c; | |
221 | tbdf->cbd_datlen = 1; | |
222 | tbdf->cbd_sc |= BD_SC_READY; | |
223 | } | |
224 | ||
225 | void | |
226 | serial_puts (const char *s) | |
227 | { | |
228 | while (*s) { | |
229 | serial_putc (*s++); | |
230 | } | |
231 | } | |
232 | ||
233 | int | |
234 | serial_getc(void) | |
235 | { | |
236 | volatile cbd_t *rbdf; | |
237 | volatile scc_uart_t *up; | |
238 | volatile immap_t *im; | |
239 | unsigned char c; | |
240 | ||
241 | im = (immap_t *)CFG_IMMR; | |
242 | up = (scc_uart_t *)&(im->im_cpm.im_dprambase[PROFF_SCC]); | |
243 | rbdf = (cbd_t *)&(im->im_cpm.im_dprambase[up->scc_genscc.scc_rbase]); | |
244 | ||
245 | /* Wait for character to show up. | |
246 | */ | |
247 | while (rbdf->cbd_sc & BD_SC_EMPTY) | |
248 | ; | |
249 | ||
250 | /* Grab the char and clear the buffer again. | |
251 | */ | |
252 | c = *(volatile unsigned char *)rbdf->cbd_bufaddr; | |
253 | rbdf->cbd_sc |= BD_SC_EMPTY; | |
254 | ||
255 | return (c); | |
256 | } | |
257 | ||
258 | int | |
259 | serial_tstc() | |
260 | { | |
261 | volatile cbd_t *rbdf; | |
262 | volatile scc_uart_t *up; | |
263 | volatile immap_t *im; | |
264 | ||
265 | im = (immap_t *)CFG_IMMR; | |
266 | up = (scc_uart_t *)&(im->im_cpm.im_dprambase[PROFF_SCC]); | |
267 | rbdf = (cbd_t *)&(im->im_cpm.im_dprambase[up->scc_genscc.scc_rbase]); | |
268 | ||
269 | return ((rbdf->cbd_sc & BD_SC_EMPTY) == 0); | |
270 | } | |
271 | ||
272 | #endif /* CONFIG_CONS_ON_SCC */ | |
273 | ||
9c4c5ae3 | 274 | #endif /* CONFIG_CPM2 */ |