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test: dm: update test for open-drain/open-source emulation in gpio-uclass
[J-u-boot.git] / drivers / video / ivybridge_igd.c
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83d290c5 1// SPDX-License-Identifier: GPL-2.0
2c943804
SG		 2/*
3 * Copyright (C) 2016 Google, Inc
2c943804
SG		 4 */
5
6#include <common.h>
7#include <bios_emul.h>
8#include <dm.h>
9#include <errno.h>
10#include <fdtdec.h>
11#include <pci_rom.h>
12#include <vbe.h>
13#include <asm/intel_regs.h>
14#include <asm/io.h>
15#include <asm/mtrr.h>
16#include <asm/pci.h>
17#include <asm/arch/pch.h>
18#include <asm/arch/sandybridge.h>
19
05af050e
SG		 20DECLARE_GLOBAL_DATA_PTR;
21
2c943804
SG		 22struct gt_powermeter {
23 u16 reg;
24 u32 value;
25};
26
27/* These are magic values - unfortunately the meaning is unknown */
28static const struct gt_powermeter snb_pm_gt1[] = {
29 { 0xa200, 0xcc000000 },
30 { 0xa204, 0x07000040 },
31 { 0xa208, 0x0000fe00 },
32 { 0xa20c, 0x00000000 },
33 { 0xa210, 0x17000000 },
34 { 0xa214, 0x00000021 },
35 { 0xa218, 0x0817fe19 },
36 { 0xa21c, 0x00000000 },
37 { 0xa220, 0x00000000 },
38 { 0xa224, 0xcc000000 },
39 { 0xa228, 0x07000040 },
40 { 0xa22c, 0x0000fe00 },
41 { 0xa230, 0x00000000 },
42 { 0xa234, 0x17000000 },
43 { 0xa238, 0x00000021 },
44 { 0xa23c, 0x0817fe19 },
45 { 0xa240, 0x00000000 },
46 { 0xa244, 0x00000000 },
47 { 0xa248, 0x8000421e },
48 { 0 }
49};
50
51static const struct gt_powermeter snb_pm_gt2[] = {
52 { 0xa200, 0x330000a6 },
53 { 0xa204, 0x402d0031 },
54 { 0xa208, 0x00165f83 },
55 { 0xa20c, 0xf1000000 },
56 { 0xa210, 0x00000000 },
57 { 0xa214, 0x00160016 },
58 { 0xa218, 0x002a002b },
59 { 0xa21c, 0x00000000 },
60 { 0xa220, 0x00000000 },
61 { 0xa224, 0x330000a6 },
62 { 0xa228, 0x402d0031 },
63 { 0xa22c, 0x00165f83 },
64 { 0xa230, 0xf1000000 },
65 { 0xa234, 0x00000000 },
66 { 0xa238, 0x00160016 },
67 { 0xa23c, 0x002a002b },
68 { 0xa240, 0x00000000 },
69 { 0xa244, 0x00000000 },
70 { 0xa248, 0x8000421e },
71 { 0 }
72};
73
74static const struct gt_powermeter ivb_pm_gt1[] = {
75 { 0xa800, 0x00000000 },
76 { 0xa804, 0x00021c00 },
77 { 0xa808, 0x00000403 },
78 { 0xa80c, 0x02001700 },
79 { 0xa810, 0x05000200 },
80 { 0xa814, 0x00000000 },
81 { 0xa818, 0x00690500 },
82 { 0xa81c, 0x0000007f },
83 { 0xa820, 0x01002501 },
84 { 0xa824, 0x00000300 },
85 { 0xa828, 0x01000331 },
86 { 0xa82c, 0x0000000c },
87 { 0xa830, 0x00010016 },
88 { 0xa834, 0x01100101 },
89 { 0xa838, 0x00010103 },
90 { 0xa83c, 0x00041300 },
91 { 0xa840, 0x00000b30 },
92 { 0xa844, 0x00000000 },
93 { 0xa848, 0x7f000000 },
94 { 0xa84c, 0x05000008 },
95 { 0xa850, 0x00000001 },
96 { 0xa854, 0x00000004 },
97 { 0xa858, 0x00000007 },
98 { 0xa85c, 0x00000000 },
99 { 0xa860, 0x00010000 },
100 { 0xa248, 0x0000221e },
101 { 0xa900, 0x00000000 },
102 { 0xa904, 0x00001c00 },
103 { 0xa908, 0x00000000 },
104 { 0xa90c, 0x06000000 },
105 { 0xa910, 0x09000200 },
106 { 0xa914, 0x00000000 },
107 { 0xa918, 0x00590000 },
108 { 0xa91c, 0x00000000 },
109 { 0xa920, 0x04002501 },
110 { 0xa924, 0x00000100 },
111 { 0xa928, 0x03000410 },
112 { 0xa92c, 0x00000000 },
113 { 0xa930, 0x00020000 },
114 { 0xa934, 0x02070106 },
115 { 0xa938, 0x00010100 },
116 { 0xa93c, 0x00401c00 },
117 { 0xa940, 0x00000000 },
118 { 0xa944, 0x00000000 },
119 { 0xa948, 0x10000e00 },
120 { 0xa94c, 0x02000004 },
121 { 0xa950, 0x00000001 },
122 { 0xa954, 0x00000004 },
123 { 0xa960, 0x00060000 },
124 { 0xaa3c, 0x00001c00 },
125 { 0xaa54, 0x00000004 },
126 { 0xaa60, 0x00060000 },
127 { 0 }
128};
129
2c943804
SG		 130static const struct gt_powermeter ivb_pm_gt2_17w[] = {
131 { 0xa800, 0x20000000 },
132 { 0xa804, 0x000e3800 },
133 { 0xa808, 0x00000806 },
134 { 0xa80c, 0x0c002f00 },
135 { 0xa810, 0x0c000800 },
136 { 0xa814, 0x00000000 },
137 { 0xa818, 0x00d20d00 },
138 { 0xa81c, 0x000000ff },
139 { 0xa820, 0x03004b02 },
140 { 0xa824, 0x00000600 },
141 { 0xa828, 0x07000773 },
142 { 0xa82c, 0x00000000 },
143 { 0xa830, 0x00020032 },
144 { 0xa834, 0x1520040d },
145 { 0xa838, 0x00020105 },
146 { 0xa83c, 0x00083700 },
147 { 0xa840, 0x000016ff },
148 { 0xa844, 0x00000000 },
149 { 0xa848, 0xff000000 },
150 { 0xa84c, 0x0a000010 },
151 { 0xa850, 0x00000002 },
152 { 0xa854, 0x00000008 },
153 { 0xa858, 0x0000000f },
154 { 0xa85c, 0x00000000 },
155 { 0xa860, 0x00020000 },
156 { 0xa248, 0x0000221e },
157 { 0xa900, 0x00000000 },
158 { 0xa904, 0x00003800 },
159 { 0xa908, 0x00000000 },
160 { 0xa90c, 0x0c000000 },
161 { 0xa910, 0x12000800 },
162 { 0xa914, 0x00000000 },
163 { 0xa918, 0x00b20000 },
164 { 0xa91c, 0x00000000 },
165 { 0xa920, 0x08004b02 },
166 { 0xa924, 0x00000300 },
167 { 0xa928, 0x01000820 },
168 { 0xa92c, 0x00000000 },
169 { 0xa930, 0x00030000 },
170 { 0xa934, 0x15150406 },
171 { 0xa938, 0x00020300 },
172 { 0xa93c, 0x00903900 },
173 { 0xa940, 0x00000000 },
174 { 0xa944, 0x00000000 },
175 { 0xa948, 0x20001b00 },
176 { 0xa94c, 0x0a000010 },
177 { 0xa950, 0x00000000 },
178 { 0xa954, 0x00000008 },
179 { 0xa960, 0x00110000 },
180 { 0xaa3c, 0x00003900 },
181 { 0xaa54, 0x00000008 },
182 { 0xaa60, 0x00110000 },
183 { 0 }
184};
185
186static const struct gt_powermeter ivb_pm_gt2_35w[] = {
187 { 0xa800, 0x00000000 },
188 { 0xa804, 0x00030400 },
189 { 0xa808, 0x00000806 },
190 { 0xa80c, 0x0c002f00 },
191 { 0xa810, 0x0c000300 },
192 { 0xa814, 0x00000000 },
193 { 0xa818, 0x00d20d00 },
194 { 0xa81c, 0x000000ff },
195 { 0xa820, 0x03004b02 },
196 { 0xa824, 0x00000600 },
197 { 0xa828, 0x07000773 },
198 { 0xa82c, 0x00000000 },
199 { 0xa830, 0x00020032 },
200 { 0xa834, 0x1520040d },
201 { 0xa838, 0x00020105 },
202 { 0xa83c, 0x00083700 },
203 { 0xa840, 0x000016ff },
204 { 0xa844, 0x00000000 },
205 { 0xa848, 0xff000000 },
206 { 0xa84c, 0x0a000010 },
207 { 0xa850, 0x00000001 },
208 { 0xa854, 0x00000008 },
209 { 0xa858, 0x00000008 },
210 { 0xa85c, 0x00000000 },
211 { 0xa860, 0x00020000 },
212 { 0xa248, 0x0000221e },
213 { 0xa900, 0x00000000 },
214 { 0xa904, 0x00003800 },
215 { 0xa908, 0x00000000 },
216 { 0xa90c, 0x0c000000 },
217 { 0xa910, 0x12000800 },
218 { 0xa914, 0x00000000 },
219 { 0xa918, 0x00b20000 },
220 { 0xa91c, 0x00000000 },
221 { 0xa920, 0x08004b02 },
222 { 0xa924, 0x00000300 },
223 { 0xa928, 0x01000820 },
224 { 0xa92c, 0x00000000 },
225 { 0xa930, 0x00030000 },
226 { 0xa934, 0x15150406 },
227 { 0xa938, 0x00020300 },
228 { 0xa93c, 0x00903900 },
229 { 0xa940, 0x00000000 },
230 { 0xa944, 0x00000000 },
231 { 0xa948, 0x20001b00 },
232 { 0xa94c, 0x0a000010 },
233 { 0xa950, 0x00000000 },
234 { 0xa954, 0x00000008 },
235 { 0xa960, 0x00110000 },
236 { 0xaa3c, 0x00003900 },
237 { 0xaa54, 0x00000008 },
238 { 0xaa60, 0x00110000 },
239 { 0 }
240};
241
242static inline u32 gtt_read(void *bar, u32 reg)
243{
244 return readl(bar + reg);
245}
246
247static inline void gtt_write(void *bar, u32 reg, u32 data)
248{
249 writel(data, bar + reg);
250}
251
252static void gtt_write_powermeter(void *bar, const struct gt_powermeter *pm)
253{
254 for (; pm && pm->reg; pm++)
255 gtt_write(bar, pm->reg, pm->value);
256}
257
258#define GTT_RETRY 1000
259static int gtt_poll(void *bar, u32 reg, u32 mask, u32 value)
260{
261 unsigned try = GTT_RETRY;
262 u32 data;
263
264 while (try--) {
265 data = gtt_read(bar, reg);
266 if ((data & mask) == value)
267 return 1;
268 udelay(10);
269 }
270
271 printf("GT init timeout\n");
272 return 0;
273}
274
275static int gma_pm_init_pre_vbios(void *gtt_bar, int rev)
276{
277 u32 reg32;
278
279 debug("GT Power Management Init, silicon = %#x\n", rev);
280
281 if (rev < IVB_STEP_C0) {
282 /* 1: Enable force wake */
283 gtt_write(gtt_bar, 0xa18c, 0x00000001);
284 gtt_poll(gtt_bar, 0x130090, (1 << 0), (1 << 0));
285 } else {
286 gtt_write(gtt_bar, 0xa180, 1 << 5);
287 gtt_write(gtt_bar, 0xa188, 0xffff0001);
288 gtt_poll(gtt_bar, 0x130040, (1 << 0), (1 << 0));
289 }
290
291 if ((rev & BASE_REV_MASK) == BASE_REV_SNB) {
292 /* 1d: Set GTT+0x42004 [15:14]=11 (SnB C1+) */
293 reg32 = gtt_read(gtt_bar, 0x42004);
294 reg32 |= (1 << 14) | (1 << 15);
295 gtt_write(gtt_bar, 0x42004, reg32);
296 }
297
298 if (rev >= IVB_STEP_A0) {
299 /* Display Reset Acknowledge Settings */
300 reg32 = gtt_read(gtt_bar, 0x45010);
301 reg32 |= (1 << 1) | (1 << 0);
302 gtt_write(gtt_bar, 0x45010, reg32);
303 }
304
305 /* 2: Get GT SKU from GTT+0x911c[13] */
306 reg32 = gtt_read(gtt_bar, 0x911c);
307 if ((rev & BASE_REV_MASK) == BASE_REV_SNB) {
308 if (reg32 & (1 << 13)) {
309 debug("SNB GT1 Power Meter Weights\n");
310 gtt_write_powermeter(gtt_bar, snb_pm_gt1);
311 } else {
312 debug("SNB GT2 Power Meter Weights\n");
313 gtt_write_powermeter(gtt_bar, snb_pm_gt2);
314 }
315 } else {
316 u32 unit = readl(MCHBAR_REG(0x5938)) & 0xf;
317
318 if (reg32 & (1 << 13)) {
319 /* GT1 SKU */
320 debug("IVB GT1 Power Meter Weights\n");
321 gtt_write_powermeter(gtt_bar, ivb_pm_gt1);
322 } else {
323 /* GT2 SKU */
324 u32 tdp = readl(MCHBAR_REG(0x5930)) & 0x7fff;
325 tdp /= (1 << unit);
326
327 if (tdp <= 17) {
328 /* <=17W ULV */
329 debug("IVB GT2 17W Power Meter Weights\n");
330 gtt_write_powermeter(gtt_bar, ivb_pm_gt2_17w);
331 } else if ((tdp >= 25) && (tdp <= 35)) {
332 /* 25W-35W */
333 debug("IVB GT2 25W-35W Power Meter Weights\n");
334 gtt_write_powermeter(gtt_bar, ivb_pm_gt2_35w);
335 } else {
336 /* All others */
337 debug("IVB GT2 35W Power Meter Weights\n");
338 gtt_write_powermeter(gtt_bar, ivb_pm_gt2_35w);
339 }
340 }
341 }
342
343 /* 3: Gear ratio map */
344 gtt_write(gtt_bar, 0xa004, 0x00000010);
345
346 /* 4: GFXPAUSE */
347 gtt_write(gtt_bar, 0xa000, 0x00070020);
348
349 /* 5: Dynamic EU trip control */
350 gtt_write(gtt_bar, 0xa080, 0x00000004);
351
352 /* 6: ECO bits */
353 reg32 = gtt_read(gtt_bar, 0xa180);
354 reg32 |= (1 << 26) | (1 << 31);
355 /* (bit 20=1 for SNB step D1+ / IVB A0+) */
356 if (rev >= SNB_STEP_D1)
357 reg32 |= (1 << 20);
358 gtt_write(gtt_bar, 0xa180, reg32);
359
360 /* 6a: for SnB step D2+ only */
361 if (((rev & BASE_REV_MASK) == BASE_REV_SNB) &&
362 (rev >= SNB_STEP_D2)) {
363 reg32 = gtt_read(gtt_bar, 0x9400);
364 reg32 |= (1 << 7);
365 gtt_write(gtt_bar, 0x9400, reg32);
366
367 reg32 = gtt_read(gtt_bar, 0x941c);
368 reg32 &= 0xf;
369 reg32 |= (1 << 1);
370 gtt_write(gtt_bar, 0x941c, reg32);
371 gtt_poll(gtt_bar, 0x941c, (1 << 1), (0 << 1));
372 }
373
374 if ((rev & BASE_REV_MASK) == BASE_REV_IVB) {
375 reg32 = gtt_read(gtt_bar, 0x907c);
376 reg32 |= (1 << 16);
377 gtt_write(gtt_bar, 0x907c, reg32);
378
379 /* 6b: Clocking reset controls */
380 gtt_write(gtt_bar, 0x9424, 0x00000001);
381 } else {
382 /* 6b: Clocking reset controls */
383 gtt_write(gtt_bar, 0x9424, 0x00000000);
384 }
385
386 /* 7 */
387 if (gtt_poll(gtt_bar, 0x138124, (1 << 31), (0 << 31))) {
388 gtt_write(gtt_bar, 0x138128, 0x00000029); /* Mailbox Data */
389 /* Mailbox Cmd for RC6 VID */
390 gtt_write(gtt_bar, 0x138124, 0x80000004);
391 if (gtt_poll(gtt_bar, 0x138124, (1 << 31), (0 << 31)))
392 gtt_write(gtt_bar, 0x138124, 0x8000000a);
393 gtt_poll(gtt_bar, 0x138124, (1 << 31), (0 << 31));
394 }
395
396 /* 8 */
397 gtt_write(gtt_bar, 0xa090, 0x00000000); /* RC Control */
398 gtt_write(gtt_bar, 0xa098, 0x03e80000); /* RC1e Wake Rate Limit */
399 gtt_write(gtt_bar, 0xa09c, 0x0028001e); /* RC6/6p Wake Rate Limit */
400 gtt_write(gtt_bar, 0xa0a0, 0x0000001e); /* RC6pp Wake Rate Limit */
401 gtt_write(gtt_bar, 0xa0a8, 0x0001e848); /* RC Evaluation Interval */
402 gtt_write(gtt_bar, 0xa0ac, 0x00000019); /* RC Idle Hysteresis */
403
404 /* 9 */
405 gtt_write(gtt_bar, 0x2054, 0x0000000a); /* Render Idle Max Count */
406 gtt_write(gtt_bar, 0x12054, 0x0000000a); /* Video Idle Max Count */
407 gtt_write(gtt_bar, 0x22054, 0x0000000a); /* Blitter Idle Max Count */
408
409 /* 10 */
410 gtt_write(gtt_bar, 0xa0b0, 0x00000000); /* Unblock Ack to Busy */
411 gtt_write(gtt_bar, 0xa0b4, 0x000003e8); /* RC1e Threshold */
412 gtt_write(gtt_bar, 0xa0b8, 0x0000c350); /* RC6 Threshold */
413 gtt_write(gtt_bar, 0xa0bc, 0x000186a0); /* RC6p Threshold */
414 gtt_write(gtt_bar, 0xa0c0, 0x0000fa00); /* RC6pp Threshold */
415
416 /* 11 */
417 gtt_write(gtt_bar, 0xa010, 0x000f4240); /* RP Down Timeout */
418 gtt_write(gtt_bar, 0xa014, 0x12060000); /* RP Interrupt Limits */
419 gtt_write(gtt_bar, 0xa02c, 0x00015f90); /* RP Up Threshold */
420 gtt_write(gtt_bar, 0xa030, 0x000186a0); /* RP Down Threshold */
421 gtt_write(gtt_bar, 0xa068, 0x000186a0); /* RP Up EI */
422 gtt_write(gtt_bar, 0xa06c, 0x000493e0); /* RP Down EI */
423 gtt_write(gtt_bar, 0xa070, 0x0000000a); /* RP Idle Hysteresis */
424
425 /* 11a: Enable Render Standby (RC6) */
426 if ((rev & BASE_REV_MASK) == BASE_REV_IVB) {
427 /*
428 * IvyBridge should also support DeepRenderStandby.
429 *
430 * Unfortunately it does not work reliably on all SKUs so
431 * disable it here and it can be enabled by the kernel.
432 */
433 gtt_write(gtt_bar, 0xa090, 0x88040000); /* HW RC Control */
434 } else {
435 gtt_write(gtt_bar, 0xa090, 0x88040000); /* HW RC Control */
436 }
437
438 /* 12: Normal Frequency Request */
439 /* RPNFREQ_VAL comes from MCHBAR 0x5998 23:16 (8 bits!? use 7) */
440 reg32 = readl(MCHBAR_REG(0x5998));
441 reg32 >>= 16;
442 reg32 &= 0xef;
443 reg32 <<= 25;
444 gtt_write(gtt_bar, 0xa008, reg32);
445
446 /* 13: RP Control */
447 gtt_write(gtt_bar, 0xa024, 0x00000592);
448
449 /* 14: Enable PM Interrupts */
450 gtt_write(gtt_bar, 0x4402c, 0x03000076);
451
452 /* Clear 0x6c024 [8:6] */
453 reg32 = gtt_read(gtt_bar, 0x6c024);
454 reg32 &= ~0x000001c0;
455 gtt_write(gtt_bar, 0x6c024, reg32);
456
457 return 0;
458}
459
460static int gma_pm_init_post_vbios(struct udevice *dev, int rev, void *gtt_bar)
461{
462 const void *blob = gd->fdt_blob;
e160f7d4 463 int node = dev_of_offset(dev);
2c943804
SG		 464 u32 reg32, cycle_delay;
465
466 debug("GT Power Management Init (post VBIOS)\n");
467
468 /* 15: Deassert Force Wake */
469 if (rev < IVB_STEP_C0) {
470 gtt_write(gtt_bar, 0xa18c, gtt_read(gtt_bar, 0xa18c) & ~1);
471 gtt_poll(gtt_bar, 0x130090, (1 << 0), (0 << 0));
472 } else {
473 gtt_write(gtt_bar, 0xa188, 0x1fffe);
474 if (gtt_poll(gtt_bar, 0x130040, (1 << 0), (0 << 0))) {
475 gtt_write(gtt_bar, 0xa188,
476 gtt_read(gtt_bar, 0xa188) | 1);
477 }
478 }
479
480 /* 16: SW RC Control */
481 gtt_write(gtt_bar, 0xa094, 0x00060000);
482
483 /* Setup Digital Port Hotplug */
484 reg32 = gtt_read(gtt_bar, 0xc4030);
485 if (!reg32) {
486 u32 dp_hotplug[3];
487
488 if (fdtdec_get_int_array(blob, node, "intel,dp_hotplug",
489 dp_hotplug, ARRAY_SIZE(dp_hotplug)))
490 return -EINVAL;
491
492 reg32 = (dp_hotplug[0] & 0x7) << 2;
493 reg32 |= (dp_hotplug[0] & 0x7) << 10;
494 reg32 |= (dp_hotplug[0] & 0x7) << 18;
495 gtt_write(gtt_bar, 0xc4030, reg32);
496 }
497
498 /* Setup Panel Power On Delays */
499 reg32 = gtt_read(gtt_bar, 0xc7208);
500 if (!reg32) {
501 reg32 = (unsigned)fdtdec_get_int(blob, node,
502 "panel-port-select", 0) << 30;
503 reg32 |= fdtdec_get_int(blob, node, "panel-power-up-delay", 0)
504 << 16;
505 reg32 |= fdtdec_get_int(blob, node,
506 "panel-power-backlight-on-delay", 0);
507 gtt_write(gtt_bar, 0xc7208, reg32);
508 }
509
510 /* Setup Panel Power Off Delays */
511 reg32 = gtt_read(gtt_bar, 0xc720c);
512 if (!reg32) {
513 reg32 = fdtdec_get_int(blob, node, "panel-power-down-delay", 0)
514 << 16;
515 reg32 |= fdtdec_get_int(blob, node,
516 "panel-power-backlight-off-delay", 0);
517 gtt_write(gtt_bar, 0xc720c, reg32);
518 }
519
520 /* Setup Panel Power Cycle Delay */
521 cycle_delay = fdtdec_get_int(blob, node,
522 "intel,panel-power-cycle-delay", 0);
523 if (cycle_delay) {
524 reg32 = gtt_read(gtt_bar, 0xc7210);
525 reg32 &= ~0xff;
526 reg32 |= cycle_delay;
527 gtt_write(gtt_bar, 0xc7210, reg32);
528 }
529
530 /* Enable Backlight if needed */
531 reg32 = fdtdec_get_int(blob, node, "intel,cpu-backlight", 0);
532 if (reg32) {
533 gtt_write(gtt_bar, 0x48250, (1 << 31));
534 gtt_write(gtt_bar, 0x48254, reg32);
535 }
536 reg32 = fdtdec_get_int(blob, node, "intel,pch-backlight", 0);
537 if (reg32) {
538 gtt_write(gtt_bar, 0xc8250, (1 << 31));
539 gtt_write(gtt_bar, 0xc8254, reg32);
540 }
541
542 return 0;
543}
544
545/*
546 * Some vga option roms are used for several chipsets but they only have one
547 * PCI ID in their header. If we encounter such an option rom, we need to do
548 * the mapping ourselves.
549 */
550
551uint32_t board_map_oprom_vendev(uint32_t vendev)
552{
553 switch (vendev) {
554 case 0x80860102: /* GT1 Desktop */
555 case 0x8086010a: /* GT1 Server */
556 case 0x80860112: /* GT2 Desktop */
557 case 0x80860116: /* GT2 Mobile */
558 case 0x80860122: /* GT2 Desktop >=1.3GHz */
559 case 0x80860126: /* GT2 Mobile >=1.3GHz */
560 case 0x80860156: /* IVB */
561 case 0x80860166: /* IVB */
562 return 0x80860106; /* GT1 Mobile */
563 }
564
565 return vendev;
566}
567
568static int int15_handler(void)
569{
570 int res = 0;
571
572 debug("%s: INT15 function %04x!\n", __func__, M.x86.R_AX);
573
574 switch (M.x86.R_AX) {
575 case 0x5f34:
576 /*
577 * Set Panel Fitting Hook:
578 * bit 2 = Graphics Stretching
579 * bit 1 = Text Stretching
580 * bit 0 = Centering (do not set with bit1 or bit2)
581 * 0 = video bios default
582 */
583 M.x86.R_AX = 0x005f;
584 M.x86.R_CL = 0x00; /* Use video bios default */
585 res = 1;
586 break;
587 case 0x5f35:
588 /*
589 * Boot Display Device Hook:
590 * bit 0 = CRT
591 * bit 1 = TV (eDP)
592 * bit 2 = EFP
593 * bit 3 = LFP
594 * bit 4 = CRT2
595 * bit 5 = TV2 (eDP)
596 * bit 6 = EFP2
597 * bit 7 = LFP2
598 */
599 M.x86.R_AX = 0x005f;
600 M.x86.R_CX = 0x0000; /* Use video bios default */
601 res = 1;
602 break;
603 case 0x5f51:
604 /*
605 * Hook to select active LFP configuration:
606 * 00h = No LVDS, VBIOS does not enable LVDS
607 * 01h = Int-LVDS, LFP driven by integrated LVDS decoder
608 * 02h = SVDO-LVDS, LFP driven by SVDO decoder
609 * 03h = eDP, LFP Driven by Int-DisplayPort encoder
610 */
611 M.x86.R_AX = 0x005f;
612 M.x86.R_CX = 0x0003; /* eDP */
613 res = 1;
614 break;
615 case 0x5f70:
616 switch (M.x86.R_CH) {
617 case 0:
618 /* Get Mux */
619 M.x86.R_AX = 0x005f;
620 M.x86.R_CX = 0x0000;
621 res = 1;
622 break;
623 case 1:
624 /* Set Mux */
625 M.x86.R_AX = 0x005f;
626 M.x86.R_CX = 0x0000;
627 res = 1;
628 break;
629 case 2:
630 /* Get SG/Non-SG mode */
631 M.x86.R_AX = 0x005f;
632 M.x86.R_CX = 0x0000;
633 res = 1;
634 break;
635 default:
636 /* Interrupt was not handled */
637 debug("Unknown INT15 5f70 function: 0x%02x\n",
638 M.x86.R_CH);
639 break;
640 }
641 break;
642 case 0x5fac:
643 res = 1;
644 break;
645 default:
646 debug("Unknown INT15 function %04x!\n", M.x86.R_AX);
647 break;
648 }
649 return res;
650}
651
652static void sandybridge_setup_graphics(struct udevice *dev,
653 struct udevice *video_dev)
654{
655 u32 reg32;
656 u16 reg16;
657 u8 reg8;
658
659 dm_pci_read_config16(video_dev, PCI_DEVICE_ID, &reg16);
660 switch (reg16) {
661 case 0x0102: /* GT1 Desktop */
662 case 0x0106: /* GT1 Mobile */
663 case 0x010a: /* GT1 Server */
664 case 0x0112: /* GT2 Desktop */
665 case 0x0116: /* GT2 Mobile */
666 case 0x0122: /* GT2 Desktop >=1.3GHz */
667 case 0x0126: /* GT2 Mobile >=1.3GHz */
668 case 0x0156: /* IvyBridge */
669 case 0x0166: /* IvyBridge */
670 break;
671 default:
672 debug("Graphics not supported by this CPU/chipset\n");
673 return;
674 }
675
676 debug("Initialising Graphics\n");
677
678 /* Setup IGD memory by setting GGC[7:3] = 1 for 32MB */
679 dm_pci_read_config16(dev, GGC, &reg16);
680 reg16 &= ~0x00f8;
681 reg16 |= 1 << 3;
682 /* Program GTT memory by setting GGC[9:8] = 2MB */
683 reg16 &= ~0x0300;
684 reg16 |= 2 << 8;
685 /* Enable VGA decode */
686 reg16 &= ~0x0002;
687 dm_pci_write_config16(dev, GGC, reg16);
688
689 /* Enable 256MB aperture */
690 dm_pci_read_config8(video_dev, MSAC, &reg8);
691 reg8 &= ~0x06;
692 reg8 |= 0x02;
693 dm_pci_write_config8(video_dev, MSAC, reg8);
694
695 /* Erratum workarounds */
696 reg32 = readl(MCHBAR_REG(0x5f00));
697 reg32 |= (1 << 9) | (1 << 10);
698 writel(reg32, MCHBAR_REG(0x5f00));
699
700 /* Enable SA Clock Gating */
701 reg32 = readl(MCHBAR_REG(0x5f00));
702 writel(reg32 | 1, MCHBAR_REG(0x5f00));
703
704 /* GPU RC6 workaround for sighting 366252 */
705 reg32 = readl(MCHBAR_REG(0x5d14));
706 reg32 |= (1 << 31);
707 writel(reg32, MCHBAR_REG(0x5d14));
708
709 /* VLW */
710 reg32 = readl(MCHBAR_REG(0x6120));
711 reg32 &= ~(1 << 0);
712 writel(reg32, MCHBAR_REG(0x6120));
713
714 reg32 = readl(MCHBAR_REG(0x5418));
715 reg32 |= (1 << 4) | (1 << 5);
716 writel(reg32, MCHBAR_REG(0x5418));
717}
718
719static int gma_func0_init(struct udevice *dev)
720{
721 struct udevice *nbridge;
722 void *gtt_bar;
723 ulong base;
724 u32 reg32;
725 int ret;
726 int rev;
727
728 /* Enable PCH Display Port */
729 writew(0x0010, RCB_REG(DISPBDF));
730 setbits_le32(RCB_REG(FD2), PCH_ENABLE_DBDF);
731
732 ret = uclass_first_device_err(UCLASS_NORTHBRIDGE, &nbridge);
733 if (ret)
734 return ret;
735 rev = bridge_silicon_revision(nbridge);
736 sandybridge_setup_graphics(nbridge, dev);
737
738 /* IGD needs to be Bus Master */
739 dm_pci_read_config32(dev, PCI_COMMAND, &reg32);
740 reg32 |= PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY | PCI_COMMAND_IO;
741 dm_pci_write_config32(dev, PCI_COMMAND, reg32);
742
743 /* Use write-combining for the graphics memory, 256MB */
744 base = dm_pci_read_bar32(dev, 2);
745 mtrr_add_request(MTRR_TYPE_WRCOMB, base, 256 << 20);
746 mtrr_commit(true);
747
c7ccb2c0 748 gtt_bar = (void *)(ulong)dm_pci_read_bar32(dev, 0);
2c943804
SG		 749 debug("GT bar %p\n", gtt_bar);
750 ret = gma_pm_init_pre_vbios(gtt_bar, rev);
751 if (ret)
752 return ret;
753
754 return rev;
755}
756
757static int bd82x6x_video_probe(struct udevice *dev)
758{
759 void *gtt_bar;
760 int ret, rev;
761
762 rev = gma_func0_init(dev);
763 if (rev < 0)
764 return rev;
765 ret = vbe_setup_video(dev, int15_handler);
766 if (ret)
767 return ret;
768
769 /* Post VBIOS init */
c7ccb2c0 770 gtt_bar = (void *)(ulong)dm_pci_read_bar32(dev, 0);
2c943804
SG		 771 ret = gma_pm_init_post_vbios(dev, rev, gtt_bar);
772 if (ret)
773 return ret;
774
775 return 0;
776}
777
778static const struct udevice_id bd82x6x_video_ids[] = {
779 { .compatible = "intel,gma" },
780 { }
781};
782
783U_BOOT_DRIVER(bd82x6x_video) = {
784 .name = "bd82x6x_video",
785 .id = UCLASS_VIDEO,
786 .of_match = bd82x6x_video_ids,
787 .probe = bd82x6x_video_probe,
788};
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