[J-u-boot.git] / include / virtex2.h

/* SPDX-License-Identifier: GPL-2.0+ */
/*
 * (C) Copyright 2002
 * Rich Ireland, Enterasys Networks, [email protected].
 * Keith Outwater, [email protected]
 */

#ifndef _VIRTEX2_H_
#define _VIRTEX2_H_

#include <xilinx.h>

/*
 * Slave SelectMap or Serial Implementation function table.
 */
typedef struct {
	xilinx_pre_fn	pre;
	xilinx_pgm_fn	pgm;
	xilinx_init_fn	init;
	xilinx_err_fn	err;
	xilinx_done_fn	done;
	xilinx_clk_fn	clk;
	xilinx_cs_fn	cs;
	xilinx_wr_fn	wr;
	xilinx_rdata_fn	rdata;
	xilinx_wdata_fn	wdata;
	xilinx_bwr_fn   wbulkdata;
	xilinx_busy_fn	busy;
	xilinx_abort_fn	abort;
	xilinx_post_fn	post;
} xilinx_virtex2_slave_fns;

#if defined(CONFIG_FPGA_VIRTEX2)
extern struct xilinx_fpga_op virtex2_op;
# define FPGA_VIRTEX2_OPS	&virtex2_op
#else
# define FPGA_VIRTEX2_OPS	NULL
#endif

/* Device Image Sizes (in bytes)
 *********************************************************************/
#define XILINX_XC2V40_SIZE	(338208 / 8)
#define XILINX_XC2V80_SIZE	(597408 / 8)
#define XILINX_XC2V250_SIZE	(1591584 / 8)
#define XILINX_XC2V500_SIZE	(2557857 / 8)
#define XILINX_XC2V1000_SIZE	(3749408 / 8)
#define XILINX_XC2V1500_SIZE	(5166240 / 8)
#define XILINX_XC2V2000_SIZE	(6808352 / 8)
#define XILINX_XC2V3000_SIZE	(9589408 / 8)
#define XILINX_XC2V4000_SIZE	(14220192 / 8)
#define XILINX_XC2V6000_SIZE	(19752096 / 8)
#define XILINX_XC2V8000_SIZE	(26185120 / 8)
#define XILINX_XC2V10000_SIZE	(33519264 / 8)

/* Descriptor Macros
 *********************************************************************/
#define XILINX_XC2V40_DESC(iface, fn_table, cookie)	\
{ xilinx_virtex2, iface, XILINX_XC2V40_SIZE, fn_table, cookie, \
	FPGA_VIRTEX2_OPS }

#define XILINX_XC2V80_DESC(iface, fn_table, cookie) \
{ xilinx_virtex2, iface, XILINX_XC2V80_SIZE, fn_table, cookie, \
	FPGA_VIRTEX2_OPS }

#define XILINX_XC2V250_DESC(iface, fn_table, cookie) \
{ xilinx_virtex2, iface, XILINX_XC2V250_SIZE, fn_table, cookie, \
	FPGA_VIRTEX2_OPS }

#define XILINX_XC2V500_DESC(iface, fn_table, cookie) \
{ xilinx_virtex2, iface, XILINX_XC2V500_SIZE, fn_table, cookie, \
	FPGA_VIRTEX2_OPS }

#define XILINX_XC2V1000_DESC(iface, fn_table, cookie) \
{ xilinx_virtex2, iface, XILINX_XC2V1000_SIZE, fn_table, cookie, \
	FPGA_VIRTEX2_OPS }

#define XILINX_XC2V1500_DESC(iface, fn_table, cookie) \
{ xilinx_virtex2, iface, XILINX_XC2V1500_SIZE, fn_table, cookie, \
	FPGA_VIRTEX2_OPS }

#define XILINX_XC2V2000_DESC(iface, fn_table, cookie) \
{ xilinx_virtex2, iface, XILINX_XC2V2000_SIZE, fn_table, cookie, \
	FPGA_VIRTEX2_OPS }

#define XILINX_XC2V3000_DESC(iface, fn_table, cookie) \
{ xilinx_virtex2, iface, XILINX_XC2V3000_SIZE, fn_table, cookie, \
	FPGA_VIRTEX2_OPS }

#define XILINX_XC2V4000_DESC(iface, fn_table, cookie) \
{ xilinx_virtex2, iface, XILINX_XC2V4000_SIZE, fn_table, cookie, \
	FPGA_VIRTEX2_OPS }

#define XILINX_XC2V6000_DESC(iface, fn_table, cookie) \
{ xilinx_virtex2, iface, XILINX_XC2V6000_SIZE, fn_table, cookie, \
	FPGA_VIRTEX2_OPS }

#define XILINX_XC2V8000_DESC(iface, fn_table, cookie) \
{ xilinx_virtex2, iface, XILINX_XC2V8000_SIZE, fn_table, cookie, \
	FPGA_VIRTEX2_OPS }

#define XILINX_XC2V10000_DESC(iface, fn_table, cookie) \
{ xilinx_virtex2, iface, XILINX_XC2V10000_SIZE, fn_table, cookie, \
	FPGA_VIRTEX2_OPS }

#endif /* _VIRTEX2_H_ */
Commit	Line	Data
83d290c5	1	/* SPDX-License-Identifier: GPL-2.0+ */
c609719b WD	2	/*
	3	* (C) Copyright 2002
	4	* Rich Ireland, Enterasys Networks, [email protected].
	5	* Keith Outwater, [email protected]
c609719b WD	6	*/
	7
	8	#ifndef _VIRTEX2_H_
	9	#define _VIRTEX2_H_
	10
	11	#include <xilinx.h>
	12
c609719b	13	/*
175dccd7	14	* Slave SelectMap or Serial Implementation function table.
c609719b WD	15	*/
c609719b WD	16	typedef struct {
2df9d5c4 MS	17	xilinx_pre_fn pre;
	18	xilinx_pgm_fn pgm;
	19	xilinx_init_fn init;
	20	xilinx_err_fn err;
	21	xilinx_done_fn done;
	22	xilinx_clk_fn clk;
	23	xilinx_cs_fn cs;
	24	xilinx_wr_fn wr;
	25	xilinx_rdata_fn rdata;
	26	xilinx_wdata_fn wdata;
175dccd7	27	xilinx_bwr_fn wbulkdata;
2df9d5c4 MS	28	xilinx_busy_fn busy;
	29	xilinx_abort_fn abort;
	30	xilinx_post_fn post;
175dccd7	31	} xilinx_virtex2_slave_fns;
c609719b	32
6a6acd12 MS	33	#if defined(CONFIG_FPGA_VIRTEX2)
	34	extern struct xilinx_fpga_op virtex2_op;
	35	# define FPGA_VIRTEX2_OPS &virtex2_op
	36	#else
	37	# define FPGA_VIRTEX2_OPS NULL
	38	#endif
	39
c609719b WD	40	/* Device Image Sizes (in bytes)
c609719b WD	41	*********************************************************************/
a3607365 MS	42	#define XILINX_XC2V40_SIZE (338208 / 8)
	43	#define XILINX_XC2V80_SIZE (597408 / 8)
	44	#define XILINX_XC2V250_SIZE (1591584 / 8)
	45	#define XILINX_XC2V500_SIZE (2557857 / 8)
c609719b WD	46	#define XILINX_XC2V1000_SIZE (3749408 / 8)
	47	#define XILINX_XC2V1500_SIZE (5166240 / 8)
	48	#define XILINX_XC2V2000_SIZE (6808352 / 8)
	49	#define XILINX_XC2V3000_SIZE (9589408 / 8)
	50	#define XILINX_XC2V4000_SIZE (14220192 / 8)
	51	#define XILINX_XC2V6000_SIZE (19752096 / 8)
	52	#define XILINX_XC2V8000_SIZE (26185120 / 8)
	53	#define XILINX_XC2V10000_SIZE (33519264 / 8)
	54
	55	/* Descriptor Macros
	56	*********************************************************************/
	57	#define XILINX_XC2V40_DESC(iface, fn_table, cookie) \
6a6acd12 MS	58	{ xilinx_virtex2, iface, XILINX_XC2V40_SIZE, fn_table, cookie, \
6a6acd12 MS	59	FPGA_VIRTEX2_OPS }
c609719b WD	60
c609719b WD	61	#define XILINX_XC2V80_DESC(iface, fn_table, cookie) \
6a6acd12 MS	62	{ xilinx_virtex2, iface, XILINX_XC2V80_SIZE, fn_table, cookie, \
6a6acd12 MS	63	FPGA_VIRTEX2_OPS }
c609719b WD	64
c609719b WD	65	#define XILINX_XC2V250_DESC(iface, fn_table, cookie) \
6a6acd12 MS	66	{ xilinx_virtex2, iface, XILINX_XC2V250_SIZE, fn_table, cookie, \
6a6acd12 MS	67	FPGA_VIRTEX2_OPS }
c609719b WD	68
c609719b WD	69	#define XILINX_XC2V500_DESC(iface, fn_table, cookie) \
6a6acd12 MS	70	{ xilinx_virtex2, iface, XILINX_XC2V500_SIZE, fn_table, cookie, \
6a6acd12 MS	71	FPGA_VIRTEX2_OPS }
c609719b WD	72
c609719b WD	73	#define XILINX_XC2V1000_DESC(iface, fn_table, cookie) \
6a6acd12 MS	74	{ xilinx_virtex2, iface, XILINX_XC2V1000_SIZE, fn_table, cookie, \
6a6acd12 MS	75	FPGA_VIRTEX2_OPS }
c609719b WD	76
c609719b WD	77	#define XILINX_XC2V1500_DESC(iface, fn_table, cookie) \
6a6acd12 MS	78	{ xilinx_virtex2, iface, XILINX_XC2V1500_SIZE, fn_table, cookie, \
6a6acd12 MS	79	FPGA_VIRTEX2_OPS }
c609719b WD	80
c609719b WD	81	#define XILINX_XC2V2000_DESC(iface, fn_table, cookie) \
6a6acd12 MS	82	{ xilinx_virtex2, iface, XILINX_XC2V2000_SIZE, fn_table, cookie, \
6a6acd12 MS	83	FPGA_VIRTEX2_OPS }
c609719b WD	84
c609719b WD	85	#define XILINX_XC2V3000_DESC(iface, fn_table, cookie) \
6a6acd12 MS	86	{ xilinx_virtex2, iface, XILINX_XC2V3000_SIZE, fn_table, cookie, \
6a6acd12 MS	87	FPGA_VIRTEX2_OPS }
c609719b WD	88
c609719b WD	89	#define XILINX_XC2V4000_DESC(iface, fn_table, cookie) \
6a6acd12 MS	90	{ xilinx_virtex2, iface, XILINX_XC2V4000_SIZE, fn_table, cookie, \
6a6acd12 MS	91	FPGA_VIRTEX2_OPS }
c609719b WD	92
c609719b WD	93	#define XILINX_XC2V6000_DESC(iface, fn_table, cookie) \
6a6acd12 MS	94	{ xilinx_virtex2, iface, XILINX_XC2V6000_SIZE, fn_table, cookie, \
6a6acd12 MS	95	FPGA_VIRTEX2_OPS }
c609719b WD	96
c609719b WD	97	#define XILINX_XC2V8000_DESC(iface, fn_table, cookie) \
6a6acd12 MS	98	{ xilinx_virtex2, iface, XILINX_XC2V8000_SIZE, fn_table, cookie, \
6a6acd12 MS	99	FPGA_VIRTEX2_OPS }
c609719b WD	100
c609719b WD	101	#define XILINX_XC2V10000_DESC(iface, fn_table, cookie) \
6a6acd12 MS	102	{ xilinx_virtex2, iface, XILINX_XC2V10000_SIZE, fn_table, cookie, \
6a6acd12 MS	103	FPGA_VIRTEX2_OPS }
c609719b WD	104
c609719b WD	105	#endif /* _VIRTEX2_H_ */