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25c7de22 PB |
1 | /* SPDX-License-Identifier: GPL-2.0+ */ |
2 | /* | |
3 | * CI20 configuration | |
4 | * | |
5 | * Copyright (c) 2013 Imagination Technologies | |
6 | * Author: Paul Burton <[email protected]> | |
7 | */ | |
8 | ||
9 | #ifndef __CONFIG_CI20_H__ | |
10 | #define __CONFIG_CI20_H__ | |
11 | ||
25c7de22 | 12 | /* Ingenic JZ4780 clock configuration. */ |
25c7de22 PB |
13 | #define CONFIG_SYS_MHZ 1200 |
14 | #define CONFIG_SYS_MIPS_TIMER_FREQ (CONFIG_SYS_MHZ * 1000000) | |
15 | ||
16 | /* Memory configuration */ | |
17 | #define CONFIG_SYS_MONITOR_LEN (512 * 1024) | |
25c7de22 PB |
18 | |
19 | #define CONFIG_SYS_SDRAM_BASE 0x80000000 /* cached (KSEG0) address */ | |
20 | #define CONFIG_SYS_INIT_SP_OFFSET 0x400000 | |
25c7de22 | 21 | |
25c7de22 PB |
22 | /* NS16550-ish UARTs */ |
23 | #define CONFIG_SYS_NS16550_CLK 48000000 | |
25c7de22 PB |
24 | |
25 | /* Ethernet: davicom DM9000 */ | |
25c7de22 PB |
26 | #define CONFIG_DM9000_BASE 0xb6000000 |
27 | #define DM9000_IO CONFIG_DM9000_BASE | |
28 | #define DM9000_DATA (CONFIG_DM9000_BASE + 2) | |
29 | ||
25c7de22 PB |
30 | /* Miscellaneous configuration options */ |
31 | #define CONFIG_SYS_BOOTM_LEN (64 << 20) | |
32 | ||
33 | /* SPL */ | |
34 | #define CONFIG_SPL_STACK 0xf4008000 /* only max. 2KB spare! */ | |
35 | ||
25c7de22 | 36 | #define CONFIG_SPL_BSS_START_ADDR 0xf4004000 |
25c7de22 PB |
37 | |
38 | #define CONFIG_SPL_START_S_PATH "arch/mips/mach-jz47xx" | |
39 | ||
25c7de22 | 40 | #endif /* __CONFIG_CI20_H__ */ |