[J-u-boot.git] / board / freescale / mpc8536ds / mpc8536ds.c

/*
 * Copyright 2008 Freescale Semiconductor.
 *
 * See file CREDITS for list of people who contributed to this
 * project.
 *
 * This program is free software; you can redistribute it and/or
 * modify it under the terms of the GNU General Public License as
 * published by the Free Software Foundation; either version 2 of
 * the License, or (at your option) any later version.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
 * GNU General Public License for more details.
 *
 * You should have received a copy of the GNU General Public License
 * along with this program; if not, write to the Free Software
 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
 * MA 02111-1307 USA
 */

#include <common.h>
#include <command.h>
#include <pci.h>
#include <asm/processor.h>
#include <asm/mmu.h>
#include <asm/cache.h>
#include <asm/immap_85xx.h>
#include <asm/immap_fsl_pci.h>
#include <asm/fsl_ddr_sdram.h>
#include <asm/io.h>
#include <spd.h>
#include <miiphy.h>
#include <libfdt.h>
#include <spd_sdram.h>
#include <fdt_support.h>
#include <tsec.h>
#include <netdev.h>

#include "../common/pixis.h"
#include "../common/sgmii_riser.h"

phys_size_t fixed_sdram(void);

int checkboard (void)
{
	printf ("Board: MPC8536DS, System ID: 0x%02x, "
		"System Version: 0x%02x, FPGA Version: 0x%02x\n",
		in8(PIXIS_BASE + PIXIS_ID), in8(PIXIS_BASE + PIXIS_VER),
		in8(PIXIS_BASE + PIXIS_PVER));
	return 0;
}

phys_size_t
initdram(int board_type)
{
	phys_size_t dram_size = 0;

	puts("Initializing....");

#ifdef CONFIG_SPD_EEPROM
	dram_size = fsl_ddr_sdram();

	dram_size = setup_ddr_tlbs(dram_size / 0x100000);

	dram_size *= 0x100000;
#else
	dram_size = fixed_sdram();
#endif

	puts("    DDR: ");
	return dram_size;
}

#if !defined(CONFIG_SPD_EEPROM)
/*
 * Fixed sdram init -- doesn't use serial presence detect.
 */

phys_size_t fixed_sdram (void)
{
	volatile immap_t *immap = (immap_t *)CONFIG_SYS_IMMR;
	volatile ccsr_ddr_t *ddr= &immap->im_ddr;
	uint d_init;

	ddr->cs0_bnds = CONFIG_SYS_DDR_CS0_BNDS;
	ddr->cs0_config = CONFIG_SYS_DDR_CS0_CONFIG;

	ddr->timing_cfg_3 = CONFIG_SYS_DDR_TIMING_3;
	ddr->timing_cfg_0 = CONFIG_SYS_DDR_TIMING_0;
	ddr->timing_cfg_1 = CONFIG_SYS_DDR_TIMING_1;
	ddr->timing_cfg_2 = CONFIG_SYS_DDR_TIMING_2;
	ddr->sdram_mode = CONFIG_SYS_DDR_MODE_1;
	ddr->sdram_mode_2 = CONFIG_SYS_DDR_MODE_2;
	ddr->sdram_interval = CONFIG_SYS_DDR_INTERVAL;
	ddr->sdram_data_init = CONFIG_SYS_DDR_DATA_INIT;
	ddr->sdram_clk_cntl = CONFIG_SYS_DDR_CLK_CTRL;
	ddr->sdram_cfg_2 = CONFIG_SYS_DDR_CONTROL2;

#if defined (CONFIG_DDR_ECC)
	ddr->err_int_en = CONFIG_SYS_DDR_ERR_INT_EN;
	ddr->err_disable = CONFIG_SYS_DDR_ERR_DIS;
	ddr->err_sbe = CONFIG_SYS_DDR_SBE;
#endif
	asm("sync;isync");

	udelay(500);

	ddr->sdram_cfg = CONFIG_SYS_DDR_CONTROL;

#if defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER)
	d_init = 1;
	debug("DDR - 1st controller: memory initializing\n");
	/*
	 * Poll until memory is initialized.
	 * 512 Meg at 400 might hit this 200 times or so.
	 */
	while ((ddr->sdram_cfg_2 & (d_init << 4)) != 0) {
		udelay(1000);
	}
	debug("DDR: memory initialized\n\n");
	asm("sync; isync");
	udelay(500);
#endif

	return 512 * 1024 * 1024;
}

#endif

#ifdef CONFIG_PCI1
static struct pci_controller pci1_hose;
#endif

#ifdef CONFIG_PCIE1
static struct pci_controller pcie1_hose;
#endif

#ifdef CONFIG_PCIE2
static struct pci_controller pcie2_hose;
#endif

#ifdef CONFIG_PCIE3
static struct pci_controller pcie3_hose;
#endif

extern int fsl_pci_setup_inbound_windows(struct pci_region *r);
extern void fsl_pci_init(struct pci_controller *hose);

int first_free_busno=0;

void
pci_init_board(void)
{
	volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
	uint devdisr = gur->devdisr;
	uint sdrs2_io_sel =
		(gur->pordevsr & MPC85xx_PORDEVSR_SRDS2_IO_SEL) >> 27;
	uint io_sel = (gur->pordevsr & MPC85xx_PORDEVSR_IO_SEL) >> 19;
	uint host_agent = (gur->porbmsr & MPC85xx_PORBMSR_HA) >> 16;

	debug("   pci_init_board: devdisr=%x, sdrs2_io_sel=%x, io_sel=%x,\
		host_agent=%x\n", devdisr, sdrs2_io_sel, io_sel, host_agent);

	if (sdrs2_io_sel == 7)
		printf("    Serdes2 disalbed\n");
	else if (sdrs2_io_sel == 4) {
		printf("    eTSEC1 is in sgmii mode.\n");
		printf("    eTSEC3 is in sgmii mode.\n");
	} else if (sdrs2_io_sel == 6)
		printf("    eTSEC1 is in sgmii mode.\n");

#ifdef CONFIG_PCIE3
{
	volatile ccsr_fsl_pci_t *pci = (ccsr_fsl_pci_t *) CONFIG_SYS_PCIE3_ADDR;
	struct pci_controller *hose = &pcie3_hose;
	int pcie_ep = (host_agent == 1);
	int pcie_configured  = (io_sel == 7);
	struct pci_region *r = hose->regions;

	if (pcie_configured && !(devdisr & MPC85xx_DEVDISR_PCIE)){
		printf ("\n    PCIE3 connected to Slot3 as %s (base address %x)",
			pcie_ep ? "End Point" : "Root Complex",
			(uint)pci);
		if (pci->pme_msg_det) {
			pci->pme_msg_det = 0xffffffff;
			debug (" with errors.  Clearing.  Now 0x%08x",pci->pme_msg_det);
		}
		printf ("\n");

		/* inbound */
		r += fsl_pci_setup_inbound_windows(r);

		/* outbound memory */
		pci_set_region(r++,
			       CONFIG_SYS_PCIE3_MEM_BASE,
			       CONFIG_SYS_PCIE3_MEM_PHYS,
			       CONFIG_SYS_PCIE3_MEM_SIZE,
			       PCI_REGION_MEM);

		/* outbound io */
		pci_set_region(r++,
			       CONFIG_SYS_PCIE3_IO_BASE,
			       CONFIG_SYS_PCIE3_IO_PHYS,
			       CONFIG_SYS_PCIE3_IO_SIZE,
			       PCI_REGION_IO);

		hose->region_count = r - hose->regions;

		hose->first_busno=first_free_busno;
		pci_setup_indirect(hose, (int) &pci->cfg_addr, (int) &pci->cfg_data);

		fsl_pci_init(hose);

		first_free_busno=hose->last_busno+1;
		printf ("    PCIE3 on bus %02x - %02x\n",
			hose->first_busno,hose->last_busno);
	} else {
		printf ("    PCIE3: disabled\n");
	}

 }
#else
	gur->devdisr |= MPC85xx_DEVDISR_PCIE3; /* disable */
#endif

#ifdef CONFIG_PCIE1
 {
	volatile ccsr_fsl_pci_t *pci = (ccsr_fsl_pci_t *) CONFIG_SYS_PCIE1_ADDR;
	struct pci_controller *hose = &pcie1_hose;
	int pcie_ep = (host_agent == 5);
	int pcie_configured  = (io_sel == 2 || io_sel == 3
				|| io_sel == 5 || io_sel == 7);
	struct pci_region *r = hose->regions;

	if (pcie_configured && !(devdisr & MPC85xx_DEVDISR_PCIE)){
		printf ("\n    PCIE1 connected to Slot1 as %s (base address %x)",
			pcie_ep ? "End Point" : "Root Complex",
			(uint)pci);
		if (pci->pme_msg_det) {
			pci->pme_msg_det = 0xffffffff;
			debug (" with errors.  Clearing.  Now 0x%08x",pci->pme_msg_det);
		}
		printf ("\n");

		/* inbound */
		r += fsl_pci_setup_inbound_windows(r);

		/* outbound memory */
		pci_set_region(r++,
			       CONFIG_SYS_PCIE1_MEM_BASE,
			       CONFIG_SYS_PCIE1_MEM_PHYS,
			       CONFIG_SYS_PCIE1_MEM_SIZE,
			       PCI_REGION_MEM);

		/* outbound io */
		pci_set_region(r++,
			       CONFIG_SYS_PCIE1_IO_BASE,
			       CONFIG_SYS_PCIE1_IO_PHYS,
			       CONFIG_SYS_PCIE1_IO_SIZE,
			       PCI_REGION_IO);

#ifdef CONFIG_SYS_PCIE1_MEM_BASE2
		/* outbound memory */
		pci_set_region(r++,
			       CONFIG_SYS_PCIE1_MEM_BASE2,
			       CONFIG_SYS_PCIE1_MEM_PHYS2,
			       CONFIG_SYS_PCIE1_MEM_SIZE2,
			       PCI_REGION_MEM);
#endif
		hose->region_count = r - hose->regions;
		hose->first_busno=first_free_busno;

		pci_setup_indirect(hose, (int) &pci->cfg_addr, (int) &pci->cfg_data);

		fsl_pci_init(hose);

		first_free_busno=hose->last_busno+1;
		printf("    PCIE1 on bus %02x - %02x\n",
		       hose->first_busno,hose->last_busno);

	} else {
		printf ("    PCIE1: disabled\n");
	}

 }
#else
	gur->devdisr |= MPC85xx_DEVDISR_PCIE; /* disable */
#endif

#ifdef CONFIG_PCIE2
 {
	volatile ccsr_fsl_pci_t *pci = (ccsr_fsl_pci_t *) CONFIG_SYS_PCIE2_ADDR;
	struct pci_controller *hose = &pcie2_hose;
	int pcie_ep = (host_agent == 3);
	int pcie_configured  = (io_sel == 5 || io_sel == 7);
	struct pci_region *r = hose->regions;

	if (pcie_configured && !(devdisr & MPC85xx_DEVDISR_PCIE)){
		printf ("\n    PCIE2 connected to Slot 2 as %s (base address %x)",
			pcie_ep ? "End Point" : "Root Complex",
			(uint)pci);
		if (pci->pme_msg_det) {
			pci->pme_msg_det = 0xffffffff;
			debug (" with errors.  Clearing.  Now 0x%08x",pci->pme_msg_det);
		}
		printf ("\n");

		/* inbound */
		r += fsl_pci_setup_inbound_windows(r);

		/* outbound memory */
		pci_set_region(r++,
			       CONFIG_SYS_PCIE2_MEM_BASE,
			       CONFIG_SYS_PCIE2_MEM_PHYS,
			       CONFIG_SYS_PCIE2_MEM_SIZE,
			       PCI_REGION_MEM);

		/* outbound io */
		pci_set_region(r++,
			       CONFIG_SYS_PCIE2_IO_BASE,
			       CONFIG_SYS_PCIE2_IO_PHYS,
			       CONFIG_SYS_PCIE2_IO_SIZE,
			       PCI_REGION_IO);

#ifdef CONFIG_SYS_PCIE2_MEM_BASE2
		/* outbound memory */
		pci_set_region(r++,
			       CONFIG_SYS_PCIE2_MEM_BASE2,
			       CONFIG_SYS_PCIE2_MEM_PHYS2,
			       CONFIG_SYS_PCIE2_MEM_SIZE2,
			       PCI_REGION_MEM);
#endif
		hose->region_count = r - hose->regions;
		hose->first_busno=first_free_busno;
		pci_setup_indirect(hose, (int) &pci->cfg_addr, (int) &pci->cfg_data);

		fsl_pci_init(hose);
		first_free_busno=hose->last_busno+1;
		printf ("    PCIE2 on bus %02x - %02x\n",
			hose->first_busno,hose->last_busno);

	} else {
		printf ("    PCIE2: disabled\n");
	}

 }
#else
	gur->devdisr |= MPC85xx_DEVDISR_PCIE2; /* disable */
#endif


#ifdef CONFIG_PCI1
{
	volatile ccsr_fsl_pci_t *pci = (ccsr_fsl_pci_t *) CONFIG_SYS_PCI1_ADDR;
	struct pci_controller *hose = &pci1_hose;
	struct pci_region *r = hose->regions;

	uint pci_agent = (host_agent == 6);
	uint pci_speed = 66666000; /*get_clock_freq (); PCI PSPEED in [4:5] */
	uint pci_32 = 1;
	uint pci_arb = gur->pordevsr & MPC85xx_PORDEVSR_PCI1_ARB;	/* PORDEVSR[14] */
	uint pci_clk_sel = gur->porpllsr & MPC85xx_PORDEVSR_PCI1_SPD;	/* PORPLLSR[16] */


	if (!(devdisr & MPC85xx_DEVDISR_PCI1)) {
		printf ("\n    PCI: %d bit, %s MHz, %s, %s, %s (base address %x)\n",
			(pci_32) ? 32 : 64,
			(pci_speed == 33333000) ? "33" :
			(pci_speed == 66666000) ? "66" : "unknown",
			pci_clk_sel ? "sync" : "async",
			pci_agent ? "agent" : "host",
			pci_arb ? "arbiter" : "external-arbiter",
			(uint)pci
			);

		/* inbound */
		r += fsl_pci_setup_inbound_windows(r);

		/* outbound memory */
		pci_set_region(r++,
			       CONFIG_SYS_PCI1_MEM_BASE,
			       CONFIG_SYS_PCI1_MEM_PHYS,
			       CONFIG_SYS_PCI1_MEM_SIZE,
			       PCI_REGION_MEM);

		/* outbound io */
		pci_set_region(r++,
			       CONFIG_SYS_PCI1_IO_BASE,
			       CONFIG_SYS_PCI1_IO_PHYS,
			       CONFIG_SYS_PCI1_IO_SIZE,
			       PCI_REGION_IO);

#ifdef CONFIG_SYS_PCI1_MEM_BASE2
		/* outbound memory */
		pci_set_region(r++,
			       CONFIG_SYS_PCI1_MEM_BASE2,
			       CONFIG_SYS_PCI1_MEM_PHYS2,
			       CONFIG_SYS_PCI1_MEM_SIZE2,
			       PCI_REGION_MEM);
#endif
		hose->region_count = r - hose->regions;
		hose->first_busno=first_free_busno;
		pci_setup_indirect(hose, (int) &pci->cfg_addr, (int) &pci->cfg_data);

		fsl_pci_init(hose);
		first_free_busno=hose->last_busno+1;
		printf ("PCI on bus %02x - %02x\n",
			hose->first_busno,hose->last_busno);
	} else {
		printf ("    PCI: disabled\n");
	}
}
#else
	gur->devdisr |= MPC85xx_DEVDISR_PCI1; /* disable */
#endif
}


int board_early_init_r(void)
{
	const unsigned int flashbase = CONFIG_SYS_FLASH_BASE;
	const u8 flash_esel = 1;

	/*
	 * Remap Boot flash + PROMJET region to caching-inhibited
	 * so that flash can be erased properly.
	 */

	/* Flush d-cache and invalidate i-cache of any FLASH data */
	flush_dcache();
	invalidate_icache();

	/* invalidate existing TLB entry for flash + promjet */
	disable_tlb(flash_esel);

	set_tlb(1, flashbase, flashbase,		/* tlb, epn, rpn */
		MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,	/* perms, wimge */
		0, flash_esel, BOOKE_PAGESZ_256M, 1);	/* ts, esel, tsize, iprot */

	return 0;
}

#ifdef CONFIG_GET_CLK_FROM_ICS307
/* decode S[0-2] to Output Divider (OD) */
static unsigned char
ics307_S_to_OD[] = {
	10, 2, 8, 4, 5, 7, 3, 6
};

/* Calculate frequency being generated by ICS307-02 clock chip based upon
 * the control bytes being programmed into it. */
/* XXX: This function should probably go into a common library */
static unsigned long
ics307_clk_freq (unsigned char cw0, unsigned char cw1, unsigned char cw2)
{
	const unsigned long long InputFrequency = CONFIG_ICS307_REFCLK_HZ;
	unsigned long VDW = ((cw1 << 1) & 0x1FE) + ((cw2 >> 7) & 1);
	unsigned long RDW = cw2 & 0x7F;
	unsigned long OD = ics307_S_to_OD[cw0 & 0x7];
	unsigned long freq;

	/* CLK1Frequency = InputFrequency * 2 * (VDW + 8) / ((RDW + 2) * OD) */

	/* cw0:  C1 C0 TTL F1 F0 S2 S1 S0
	 * cw1:  V8 V7 V6 V5 V4 V3 V2 V1
	 * cw2:  V0 R6 R5 R4 R3 R2 R1 R0
	 *
	 * R6:R0 = Reference Divider Word (RDW)
	 * V8:V0 = VCO Divider Word (VDW)
	 * S2:S0 = Output Divider Select (OD)
	 * F1:F0 = Function of CLK2 Output
	 * TTL = duty cycle
	 * C1:C0 = internal load capacitance for cyrstal
	 */

	/* Adding 1 to get a "nicely" rounded number, but this needs
	 * more tweaking to get a "properly" rounded number. */

	freq = 1 + (InputFrequency * 2 * (VDW + 8) / ((RDW + 2) * OD));

	debug("ICS307: CW[0-2]: %02X %02X %02X => %u Hz\n", cw0, cw1, cw2,
		freq);
	return freq;
}

unsigned long
get_board_sys_clk(ulong dummy)
{
	return ics307_clk_freq (
	    in8(PIXIS_BASE + PIXIS_VSYSCLK0),
	    in8(PIXIS_BASE + PIXIS_VSYSCLK1),
	    in8(PIXIS_BASE + PIXIS_VSYSCLK2)
	);
}

unsigned long
get_board_ddr_clk(ulong dummy)
{
	return ics307_clk_freq (
	    in8(PIXIS_BASE + PIXIS_VDDRCLK0),
	    in8(PIXIS_BASE + PIXIS_VDDRCLK1),
	    in8(PIXIS_BASE + PIXIS_VDDRCLK2)
	);
}
#else
unsigned long
get_board_sys_clk(ulong dummy)
{
	u8 i;
	ulong val = 0;

	i = in8(PIXIS_BASE + PIXIS_SPD);
	i &= 0x07;

	switch (i) {
	case 0:
		val = 33333333;
		break;
	case 1:
		val = 40000000;
		break;
	case 2:
		val = 50000000;
		break;
	case 3:
		val = 66666666;
		break;
	case 4:
		val = 83333333;
		break;
	case 5:
		val = 100000000;
		break;
	case 6:
		val = 133333333;
		break;
	case 7:
		val = 166666666;
		break;
	}

	return val;
}

unsigned long
get_board_ddr_clk(ulong dummy)
{
	u8 i;
	ulong val = 0;

	i = in8(PIXIS_BASE + PIXIS_SPD);
	i &= 0x38;
	i >>= 3;

	switch (i) {
	case 0:
		val = 33333333;
		break;
	case 1:
		val = 40000000;
		break;
	case 2:
		val = 50000000;
		break;
	case 3:
		val = 66666666;
		break;
	case 4:
		val = 83333333;
		break;
	case 5:
		val = 100000000;
		break;
	case 6:
		val = 133333333;
		break;
	case 7:
		val = 166666666;
		break;
	}
	return val;
}
#endif

int is_sata_supported(void)
{
	volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
	uint sdrs2_io_sel =
		(gur->pordevsr & MPC85xx_PORDEVSR_SRDS2_IO_SEL) >> 27;
	if (sdrs2_io_sel & 0x04)
		return 0;

	return 1;
}

int board_eth_init(bd_t *bis)
{
#ifdef CONFIG_TSEC_ENET
	struct tsec_info_struct tsec_info[2];
	volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
	int num = 0;
	uint sdrs2_io_sel =
		(gur->pordevsr & MPC85xx_PORDEVSR_SRDS2_IO_SEL) >> 27;

#ifdef CONFIG_TSEC1
	SET_STD_TSEC_INFO(tsec_info[num], 1);
	if ((sdrs2_io_sel == 4) || (sdrs2_io_sel == 6)) {
		tsec_info[num].phyaddr = 0;
		tsec_info[num].flags |= TSEC_SGMII;
	}
	num++;
#endif
#ifdef CONFIG_TSEC3
	SET_STD_TSEC_INFO(tsec_info[num], 3);
	if (sdrs2_io_sel == 4) {
		tsec_info[num].phyaddr = 1;
		tsec_info[num].flags |= TSEC_SGMII;
	}
	num++;
#endif

	if (!num) {
		printf("No TSECs initialized\n");
		return 0;
	}

	if ((sdrs2_io_sel == 4) || (sdrs2_io_sel == 6))
		fsl_sgmii_riser_init(tsec_info, num);

	tsec_eth_init(bis, tsec_info, num);
#endif
	return pci_eth_init(bis);
}

#if defined(CONFIG_OF_BOARD_SETUP)
extern void ft_fsl_pci_setup(void *blob, const char *pci_alias,
			struct pci_controller *hose);

void ft_board_setup(void *blob, bd_t *bd)
{
	ft_cpu_setup(blob, bd);

#ifdef CONFIG_PCI1
	ft_fsl_pci_setup(blob, "pci0", &pci1_hose);
#endif
#ifdef CONFIG_PCIE2
	ft_fsl_pci_setup(blob, "pci1", &pcie2_hose);
#endif
#ifdef CONFIG_PCIE2
	ft_fsl_pci_setup(blob, "pci2", &pcie1_hose);
#endif
#ifdef CONFIG_PCIE1
	ft_fsl_pci_setup(blob, "pci3", &pcie3_hose);
#endif
}
#endif
Commit	Line	Data
9490a7f1 KG	1	/*
	2	* Copyright 2008 Freescale Semiconductor.
	3	*
	4	* See file CREDITS for list of people who contributed to this
	5	* project.
	6	*
	7	* This program is free software; you can redistribute it and/or
	8	* modify it under the terms of the GNU General Public License as
	9	* published by the Free Software Foundation; either version 2 of
	10	* the License, or (at your option) any later version.
	11	*
	12	* This program is distributed in the hope that it will be useful,
	13	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	14	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	15	* GNU General Public License for more details.
	16	*
	17	* You should have received a copy of the GNU General Public License
	18	* along with this program; if not, write to the Free Software
	19	* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
	20	* MA 02111-1307 USA
	21	*/
	22
	23	#include <common.h>
	24	#include <command.h>
	25	#include <pci.h>
	26	#include <asm/processor.h>
	27	#include <asm/mmu.h>
7c0d4a75	28	#include <asm/cache.h>
9490a7f1 KG	29	#include <asm/immap_85xx.h>
	30	#include <asm/immap_fsl_pci.h>
	31	#include <asm/fsl_ddr_sdram.h>
	32	#include <asm/io.h>
	33	#include <spd.h>
	34	#include <miiphy.h>
	35	#include <libfdt.h>
	36	#include <spd_sdram.h>
	37	#include <fdt_support.h>
2e26d837 JJ	38	#include <tsec.h>
2e26d837 JJ	39	#include <netdev.h>
9490a7f1 KG	40
9490a7f1 KG	41	#include "../common/pixis.h"
2e26d837	42	#include "../common/sgmii_riser.h"
9490a7f1	43
9490a7f1 KG	44	phys_size_t fixed_sdram(void);
	45
	46	int checkboard (void)
	47	{
	48	printf ("Board: MPC8536DS, System ID: 0x%02x, "
	49	"System Version: 0x%02x, FPGA Version: 0x%02x\n",
	50	in8(PIXIS_BASE + PIXIS_ID), in8(PIXIS_BASE + PIXIS_VER),
	51	in8(PIXIS_BASE + PIXIS_PVER));
	52	return 0;
	53	}
	54
	55	phys_size_t
	56	initdram(int board_type)
	57	{
	58	phys_size_t dram_size = 0;
	59
	60	puts("Initializing....");
	61
	62	#ifdef CONFIG_SPD_EEPROM
	63	dram_size = fsl_ddr_sdram();
	64
	65	dram_size = setup_ddr_tlbs(dram_size / 0x100000);
	66
	67	dram_size *= 0x100000;
	68	#else
	69	dram_size = fixed_sdram();
	70	#endif
	71
9490a7f1 KG	72	puts(" DDR: ");
	73	return dram_size;
	74	}
	75
	76	#if !defined(CONFIG_SPD_EEPROM)
	77	/*
	78	* Fixed sdram init -- doesn't use serial presence detect.
	79	*/
	80
	81	phys_size_t fixed_sdram (void)
	82	{
6d0f6bcf	83	volatile immap_t immap = (immap_t )CONFIG_SYS_IMMR;
9490a7f1 KG	84	volatile ccsr_ddr_t *ddr= &immap->im_ddr;
	85	uint d_init;
	86
6d0f6bcf JCPV	87	ddr->cs0_bnds = CONFIG_SYS_DDR_CS0_BNDS;
6d0f6bcf JCPV	88	ddr->cs0_config = CONFIG_SYS_DDR_CS0_CONFIG;
9490a7f1	89
6d0f6bcf JCPV	90	ddr->timing_cfg_3 = CONFIG_SYS_DDR_TIMING_3;
	91	ddr->timing_cfg_0 = CONFIG_SYS_DDR_TIMING_0;
	92	ddr->timing_cfg_1 = CONFIG_SYS_DDR_TIMING_1;
	93	ddr->timing_cfg_2 = CONFIG_SYS_DDR_TIMING_2;
	94	ddr->sdram_mode = CONFIG_SYS_DDR_MODE_1;
	95	ddr->sdram_mode_2 = CONFIG_SYS_DDR_MODE_2;
	96	ddr->sdram_interval = CONFIG_SYS_DDR_INTERVAL;
	97	ddr->sdram_data_init = CONFIG_SYS_DDR_DATA_INIT;
	98	ddr->sdram_clk_cntl = CONFIG_SYS_DDR_CLK_CTRL;
	99	ddr->sdram_cfg_2 = CONFIG_SYS_DDR_CONTROL2;
9490a7f1 KG	100
9490a7f1 KG	101	#if defined (CONFIG_DDR_ECC)
6d0f6bcf JCPV	102	ddr->err_int_en = CONFIG_SYS_DDR_ERR_INT_EN;
	103	ddr->err_disable = CONFIG_SYS_DDR_ERR_DIS;
	104	ddr->err_sbe = CONFIG_SYS_DDR_SBE;
9490a7f1 KG	105	#endif
	106	asm("sync;isync");
	107
	108	udelay(500);
	109
6d0f6bcf	110	ddr->sdram_cfg = CONFIG_SYS_DDR_CONTROL;
9490a7f1 KG	111
	112	#if defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER)
	113	d_init = 1;
	114	debug("DDR - 1st controller: memory initializing\n");
	115	/*
	116	* Poll until memory is initialized.
	117	* 512 Meg at 400 might hit this 200 times or so.
	118	*/
	119	while ((ddr->sdram_cfg_2 & (d_init << 4)) != 0) {
	120	udelay(1000);
	121	}
	122	debug("DDR: memory initialized\n\n");
	123	asm("sync; isync");
	124	udelay(500);
	125	#endif
	126
	127	return 512 * 1024 * 1024;
	128	}
	129
	130	#endif
	131
	132	#ifdef CONFIG_PCI1
	133	static struct pci_controller pci1_hose;
	134	#endif
	135
	136	#ifdef CONFIG_PCIE1
	137	static struct pci_controller pcie1_hose;
	138	#endif
	139
	140	#ifdef CONFIG_PCIE2
	141	static struct pci_controller pcie2_hose;
	142	#endif
	143
	144	#ifdef CONFIG_PCIE3
	145	static struct pci_controller pcie3_hose;
	146	#endif
	147
2dba0dea KG	148	extern int fsl_pci_setup_inbound_windows(struct pci_region *r);
	149	extern void fsl_pci_init(struct pci_controller *hose);
	150
9490a7f1 KG	151	int first_free_busno=0;
	152
	153	void
	154	pci_init_board(void)
	155	{
6d0f6bcf	156	volatile ccsr_gur_t gur = (void )(CONFIG_SYS_MPC85xx_GUTS_ADDR);
9490a7f1 KG	157	uint devdisr = gur->devdisr;
	158	uint sdrs2_io_sel =
	159	(gur->pordevsr & MPC85xx_PORDEVSR_SRDS2_IO_SEL) >> 27;
	160	uint io_sel = (gur->pordevsr & MPC85xx_PORDEVSR_IO_SEL) >> 19;
	161	uint host_agent = (gur->porbmsr & MPC85xx_PORBMSR_HA) >> 16;
	162
	163	debug(" pci_init_board: devdisr=%x, sdrs2_io_sel=%x, io_sel=%x,\
	164	host_agent=%x\n", devdisr, sdrs2_io_sel, io_sel, host_agent);
	165
	166	if (sdrs2_io_sel == 7)
	167	printf(" Serdes2 disalbed\n");
	168	else if (sdrs2_io_sel == 4) {
	169	printf(" eTSEC1 is in sgmii mode.\n");
	170	printf(" eTSEC3 is in sgmii mode.\n");
	171	} else if (sdrs2_io_sel == 6)
	172	printf(" eTSEC1 is in sgmii mode.\n");
	173
	174	#ifdef CONFIG_PCIE3
	175	{
6d0f6bcf	176	volatile ccsr_fsl_pci_t pci = (ccsr_fsl_pci_t ) CONFIG_SYS_PCIE3_ADDR;
9490a7f1 KG	177	struct pci_controller *hose = &pcie3_hose;
	178	int pcie_ep = (host_agent == 1);
	179	int pcie_configured = (io_sel == 7);
2dba0dea	180	struct pci_region *r = hose->regions;
9490a7f1 KG	181
	182	if (pcie_configured && !(devdisr & MPC85xx_DEVDISR_PCIE)){
	183	printf ("\n PCIE3 connected to Slot3 as %s (base address %x)",
	184	pcie_ep ? "End Point" : "Root Complex",
	185	(uint)pci);
	186	if (pci->pme_msg_det) {
	187	pci->pme_msg_det = 0xffffffff;
	188	debug (" with errors. Clearing. Now 0x%08x",pci->pme_msg_det);
	189	}
	190	printf ("\n");
	191
	192	/* inbound */
2dba0dea	193	r += fsl_pci_setup_inbound_windows(r);
9490a7f1 KG	194
9490a7f1 KG	195	/* outbound memory */
2dba0dea	196	pci_set_region(r++,
6d0f6bcf JCPV	197	CONFIG_SYS_PCIE3_MEM_BASE,
	198	CONFIG_SYS_PCIE3_MEM_PHYS,
	199	CONFIG_SYS_PCIE3_MEM_SIZE,
9490a7f1 KG	200	PCI_REGION_MEM);
	201
	202	/* outbound io */
2dba0dea	203	pci_set_region(r++,
6d0f6bcf JCPV	204	CONFIG_SYS_PCIE3_IO_BASE,
	205	CONFIG_SYS_PCIE3_IO_PHYS,
	206	CONFIG_SYS_PCIE3_IO_SIZE,
9490a7f1 KG	207	PCI_REGION_IO);
9490a7f1 KG	208
2dba0dea	209	hose->region_count = r - hose->regions;
9490a7f1 KG	210
	211	hose->first_busno=first_free_busno;
	212	pci_setup_indirect(hose, (int) &pci->cfg_addr, (int) &pci->cfg_data);
	213
	214	fsl_pci_init(hose);
	215
	216	first_free_busno=hose->last_busno+1;
	217	printf (" PCIE3 on bus %02x - %02x\n",
	218	hose->first_busno,hose->last_busno);
	219	} else {
	220	printf (" PCIE3: disabled\n");
	221	}
	222
	223	}
	224	#else
	225	gur->devdisr \|= MPC85xx_DEVDISR_PCIE3; /* disable */
	226	#endif
	227
	228	#ifdef CONFIG_PCIE1
	229	{
6d0f6bcf	230	volatile ccsr_fsl_pci_t pci = (ccsr_fsl_pci_t ) CONFIG_SYS_PCIE1_ADDR;
9490a7f1 KG	231	struct pci_controller *hose = &pcie1_hose;
	232	int pcie_ep = (host_agent == 5);
	233	int pcie_configured = (io_sel == 2 \|\| io_sel == 3
	234	\|\| io_sel == 5 \|\| io_sel == 7);
2dba0dea	235	struct pci_region *r = hose->regions;
9490a7f1 KG	236
	237	if (pcie_configured && !(devdisr & MPC85xx_DEVDISR_PCIE)){
	238	printf ("\n PCIE1 connected to Slot1 as %s (base address %x)",
	239	pcie_ep ? "End Point" : "Root Complex",
	240	(uint)pci);
	241	if (pci->pme_msg_det) {
	242	pci->pme_msg_det = 0xffffffff;
	243	debug (" with errors. Clearing. Now 0x%08x",pci->pme_msg_det);
	244	}
	245	printf ("\n");
	246
	247	/* inbound */
2dba0dea	248	r += fsl_pci_setup_inbound_windows(r);
9490a7f1 KG	249
9490a7f1 KG	250	/* outbound memory */
2dba0dea	251	pci_set_region(r++,
6d0f6bcf JCPV	252	CONFIG_SYS_PCIE1_MEM_BASE,
	253	CONFIG_SYS_PCIE1_MEM_PHYS,
	254	CONFIG_SYS_PCIE1_MEM_SIZE,
9490a7f1 KG	255	PCI_REGION_MEM);
	256
	257	/* outbound io */
2dba0dea	258	pci_set_region(r++,
6d0f6bcf JCPV	259	CONFIG_SYS_PCIE1_IO_BASE,
	260	CONFIG_SYS_PCIE1_IO_PHYS,
	261	CONFIG_SYS_PCIE1_IO_SIZE,
9490a7f1 KG	262	PCI_REGION_IO);
9490a7f1 KG	263
6d0f6bcf	264	#ifdef CONFIG_SYS_PCIE1_MEM_BASE2
9490a7f1	265	/* outbound memory */
2dba0dea	266	pci_set_region(r++,
6d0f6bcf JCPV	267	CONFIG_SYS_PCIE1_MEM_BASE2,
	268	CONFIG_SYS_PCIE1_MEM_PHYS2,
	269	CONFIG_SYS_PCIE1_MEM_SIZE2,
9490a7f1	270	PCI_REGION_MEM);
9490a7f1	271	#endif
2dba0dea	272	hose->region_count = r - hose->regions;
9490a7f1 KG	273	hose->first_busno=first_free_busno;
	274
	275	pci_setup_indirect(hose, (int) &pci->cfg_addr, (int) &pci->cfg_data);
	276
	277	fsl_pci_init(hose);
	278
	279	first_free_busno=hose->last_busno+1;
	280	printf(" PCIE1 on bus %02x - %02x\n",
	281	hose->first_busno,hose->last_busno);
	282
	283	} else {
	284	printf (" PCIE1: disabled\n");
	285	}
	286
	287	}
	288	#else
	289	gur->devdisr \|= MPC85xx_DEVDISR_PCIE; /* disable */
	290	#endif
	291
	292	#ifdef CONFIG_PCIE2
	293	{
6d0f6bcf	294	volatile ccsr_fsl_pci_t pci = (ccsr_fsl_pci_t ) CONFIG_SYS_PCIE2_ADDR;
9490a7f1 KG	295	struct pci_controller *hose = &pcie2_hose;
	296	int pcie_ep = (host_agent == 3);
	297	int pcie_configured = (io_sel == 5 \|\| io_sel == 7);
2dba0dea	298	struct pci_region *r = hose->regions;
9490a7f1 KG	299
	300	if (pcie_configured && !(devdisr & MPC85xx_DEVDISR_PCIE)){
	301	printf ("\n PCIE2 connected to Slot 2 as %s (base address %x)",
	302	pcie_ep ? "End Point" : "Root Complex",
	303	(uint)pci);
	304	if (pci->pme_msg_det) {
	305	pci->pme_msg_det = 0xffffffff;
	306	debug (" with errors. Clearing. Now 0x%08x",pci->pme_msg_det);
	307	}
	308	printf ("\n");
	309
	310	/* inbound */
2dba0dea	311	r += fsl_pci_setup_inbound_windows(r);
9490a7f1 KG	312
9490a7f1 KG	313	/* outbound memory */
2dba0dea	314	pci_set_region(r++,
6d0f6bcf JCPV	315	CONFIG_SYS_PCIE2_MEM_BASE,
	316	CONFIG_SYS_PCIE2_MEM_PHYS,
	317	CONFIG_SYS_PCIE2_MEM_SIZE,
9490a7f1 KG	318	PCI_REGION_MEM);
	319
	320	/* outbound io */
2dba0dea	321	pci_set_region(r++,
6d0f6bcf JCPV	322	CONFIG_SYS_PCIE2_IO_BASE,
	323	CONFIG_SYS_PCIE2_IO_PHYS,
	324	CONFIG_SYS_PCIE2_IO_SIZE,
9490a7f1 KG	325	PCI_REGION_IO);
9490a7f1 KG	326
6d0f6bcf	327	#ifdef CONFIG_SYS_PCIE2_MEM_BASE2
9490a7f1	328	/* outbound memory */
2dba0dea	329	pci_set_region(r++,
6d0f6bcf JCPV	330	CONFIG_SYS_PCIE2_MEM_BASE2,
	331	CONFIG_SYS_PCIE2_MEM_PHYS2,
	332	CONFIG_SYS_PCIE2_MEM_SIZE2,
9490a7f1	333	PCI_REGION_MEM);
9490a7f1	334	#endif
2dba0dea	335	hose->region_count = r - hose->regions;
9490a7f1 KG	336	hose->first_busno=first_free_busno;
	337	pci_setup_indirect(hose, (int) &pci->cfg_addr, (int) &pci->cfg_data);
	338
	339	fsl_pci_init(hose);
	340	first_free_busno=hose->last_busno+1;
	341	printf (" PCIE2 on bus %02x - %02x\n",
	342	hose->first_busno,hose->last_busno);
	343
	344	} else {
	345	printf (" PCIE2: disabled\n");
	346	}
	347
	348	}
	349	#else
	350	gur->devdisr \|= MPC85xx_DEVDISR_PCIE2; /* disable */
	351	#endif
	352
	353
	354	#ifdef CONFIG_PCI1
	355	{
6d0f6bcf	356	volatile ccsr_fsl_pci_t pci = (ccsr_fsl_pci_t ) CONFIG_SYS_PCI1_ADDR;
9490a7f1	357	struct pci_controller *hose = &pci1_hose;
2dba0dea	358	struct pci_region *r = hose->regions;
9490a7f1 KG	359
	360	uint pci_agent = (host_agent == 6);
	361	uint pci_speed = 66666000; /get_clock_freq (); PCI PSPEED in [4:5] /
	362	uint pci_32 = 1;
	363	uint pci_arb = gur->pordevsr & MPC85xx_PORDEVSR_PCI1_ARB; /* PORDEVSR[14] */
	364	uint pci_clk_sel = gur->porpllsr & MPC85xx_PORDEVSR_PCI1_SPD; /* PORPLLSR[16] */
	365
	366
	367	if (!(devdisr & MPC85xx_DEVDISR_PCI1)) {
	368	printf ("\n PCI: %d bit, %s MHz, %s, %s, %s (base address %x)\n",
	369	(pci_32) ? 32 : 64,
	370	(pci_speed == 33333000) ? "33" :
	371	(pci_speed == 66666000) ? "66" : "unknown",
	372	pci_clk_sel ? "sync" : "async",
	373	pci_agent ? "agent" : "host",
	374	pci_arb ? "arbiter" : "external-arbiter",
	375	(uint)pci
	376	);
	377
	378	/* inbound */
2dba0dea	379	r += fsl_pci_setup_inbound_windows(r);
9490a7f1 KG	380
9490a7f1 KG	381	/* outbound memory */
2dba0dea	382	pci_set_region(r++,
6d0f6bcf JCPV	383	CONFIG_SYS_PCI1_MEM_BASE,
	384	CONFIG_SYS_PCI1_MEM_PHYS,
	385	CONFIG_SYS_PCI1_MEM_SIZE,
9490a7f1 KG	386	PCI_REGION_MEM);
	387
	388	/* outbound io */
2dba0dea	389	pci_set_region(r++,
6d0f6bcf JCPV	390	CONFIG_SYS_PCI1_IO_BASE,
	391	CONFIG_SYS_PCI1_IO_PHYS,
	392	CONFIG_SYS_PCI1_IO_SIZE,
9490a7f1	393	PCI_REGION_IO);
2dba0dea	394
6d0f6bcf	395	#ifdef CONFIG_SYS_PCI1_MEM_BASE2
9490a7f1	396	/* outbound memory */
2dba0dea	397	pci_set_region(r++,
6d0f6bcf JCPV	398	CONFIG_SYS_PCI1_MEM_BASE2,
	399	CONFIG_SYS_PCI1_MEM_PHYS2,
	400	CONFIG_SYS_PCI1_MEM_SIZE2,
9490a7f1	401	PCI_REGION_MEM);
9490a7f1	402	#endif
2dba0dea	403	hose->region_count = r - hose->regions;
9490a7f1 KG	404	hose->first_busno=first_free_busno;
	405	pci_setup_indirect(hose, (int) &pci->cfg_addr, (int) &pci->cfg_data);
	406
	407	fsl_pci_init(hose);
	408	first_free_busno=hose->last_busno+1;
	409	printf ("PCI on bus %02x - %02x\n",
	410	hose->first_busno,hose->last_busno);
	411	} else {
	412	printf (" PCI: disabled\n");
	413	}
	414	}
	415	#else
	416	gur->devdisr \|= MPC85xx_DEVDISR_PCI1; /* disable */
	417	#endif
	418	}
	419
	420
	421	int board_early_init_r(void)
	422	{
6d0f6bcf	423	const unsigned int flashbase = CONFIG_SYS_FLASH_BASE;
9490a7f1 KG	424	const u8 flash_esel = 1;
	425
	426	/*
	427	* Remap Boot flash + PROMJET region to caching-inhibited
	428	* so that flash can be erased properly.
	429	*/
	430
7c0d4a75	431	/* Flush d-cache and invalidate i-cache of any FLASH data */
3cbd8231 WD	432	flush_dcache();
3cbd8231 WD	433	invalidate_icache();
9490a7f1 KG	434
	435	/* invalidate existing TLB entry for flash + promjet */
	436	disable_tlb(flash_esel);
	437
	438	set_tlb(1, flashbase, flashbase, /* tlb, epn, rpn */
	439	MAS3_SX\|MAS3_SW\|MAS3_SR, MAS2_I\|MAS2_G, /* perms, wimge */
	440	0, flash_esel, BOOKE_PAGESZ_256M, 1); /* ts, esel, tsize, iprot */
	441
	442	return 0;
	443	}
	444
	445	#ifdef CONFIG_GET_CLK_FROM_ICS307
	446	/* decode S[0-2] to Output Divider (OD) */
	447	static unsigned char
	448	ics307_S_to_OD[] = {
	449	10, 2, 8, 4, 5, 7, 3, 6
	450	};
	451
	452	/* Calculate frequency being generated by ICS307-02 clock chip based upon
	453	* the control bytes being programmed into it. */
	454	/* XXX: This function should probably go into a common library */
	455	static unsigned long
	456	ics307_clk_freq (unsigned char cw0, unsigned char cw1, unsigned char cw2)
	457	{
	458	const unsigned long long InputFrequency = CONFIG_ICS307_REFCLK_HZ;
	459	unsigned long VDW = ((cw1 << 1) & 0x1FE) + ((cw2 >> 7) & 1);
	460	unsigned long RDW = cw2 & 0x7F;
	461	unsigned long OD = ics307_S_to_OD[cw0 & 0x7];
	462	unsigned long freq;
	463
	464	/* CLK1Frequency = InputFrequency * 2 * (VDW + 8) / ((RDW + 2) * OD) */
	465
	466	/* cw0: C1 C0 TTL F1 F0 S2 S1 S0
	467	* cw1: V8 V7 V6 V5 V4 V3 V2 V1
	468	* cw2: V0 R6 R5 R4 R3 R2 R1 R0
	469	*
	470	* R6:R0 = Reference Divider Word (RDW)
	471	* V8:V0 = VCO Divider Word (VDW)
	472	* S2:S0 = Output Divider Select (OD)
	473	* F1:F0 = Function of CLK2 Output
	474	* TTL = duty cycle
	475	* C1:C0 = internal load capacitance for cyrstal
	476	*/
	477
	478	/* Adding 1 to get a "nicely" rounded number, but this needs
	479	* more tweaking to get a "properly" rounded number. */
	480
	481	freq = 1 + (InputFrequency * 2 * (VDW + 8) / ((RDW + 2) * OD));
	482
	483	debug("ICS307: CW[0-2]: %02X %02X %02X => %u Hz\n", cw0, cw1, cw2,
	484	freq);
	485	return freq;
	486	}
	487
	488	unsigned long
	489	get_board_sys_clk(ulong dummy)
	490	{
	491	return ics307_clk_freq (
	492	in8(PIXIS_BASE + PIXIS_VSYSCLK0),
	493	in8(PIXIS_BASE + PIXIS_VSYSCLK1),
	494	in8(PIXIS_BASE + PIXIS_VSYSCLK2)
	495	);
	496	}
	497
498	unsigned long
499	get_board_ddr_clk(ulong dummy)
500	{
501	return ics307_clk_freq (
502	in8(PIXIS_BASE + PIXIS_VDDRCLK0),
503	in8(PIXIS_BASE + PIXIS_VDDRCLK1),
504	in8(PIXIS_BASE + PIXIS_VDDRCLK2)
505	);
506	}
507	#else
508	unsigned long
509	get_board_sys_clk(ulong dummy)
510	{
511	u8 i;
512	ulong val = 0;
513
514	i = in8(PIXIS_BASE + PIXIS_SPD);
515	i &= 0x07;
516
517	switch (i) {
518	case 0:
519	val = 33333333;
520	break;
521	case 1:
522	val = 40000000;
523	break;
524	case 2:
525	val = 50000000;
526	break;
527	case 3:
528	val = 66666666;
529	break;
530	case 4:
531	val = 83333333;
532	break;
533	case 5:
534	val = 100000000;
535	break;
536	case 6:
537	val = 133333333;
538	break;
539	case 7:
540	val = 166666666;
541	break;
542	}
543
544	return val;
545	}
546
547	unsigned long
548	get_board_ddr_clk(ulong dummy)
549	{
550	u8 i;
551	ulong val = 0;
552
553	i = in8(PIXIS_BASE + PIXIS_SPD);
554	i &= 0x38;
555	i >>= 3;
556
557	switch (i) {
558	case 0:
559	val = 33333333;
560	break;
561	case 1:
562	val = 40000000;
563	break;
564	case 2:
565	val = 50000000;
566	break;
567	case 3:
568	val = 66666666;
569	break;
570	case 4:
571	val = 83333333;
572	break;
573	case 5:
574	val = 100000000;
575	break;
576	case 6:
577	val = 133333333;
578	break;
579	case 7:
580	val = 166666666;
581	break;
582	}
583	return val;
584	}
585	#endif
586
374b9038	587	int is_sata_supported(void)
0f8cbc18	588	{
6d0f6bcf	589	volatile ccsr_gur_t gur = (void )(CONFIG_SYS_MPC85xx_GUTS_ADDR);
0f8cbc18 JJ	590	uint sdrs2_io_sel =
	591	(gur->pordevsr & MPC85xx_PORDEVSR_SRDS2_IO_SEL) >> 27;
	592	if (sdrs2_io_sel & 0x04)
	593	return 0;
	594
	595	return 1;
	596	}
	597
2e26d837 JJ	598	int board_eth_init(bd_t *bis)
	599	{
	600	#ifdef CONFIG_TSEC_ENET
	601	struct tsec_info_struct tsec_info[2];
	602	volatile ccsr_gur_t gur = (void )(CONFIG_SYS_MPC85xx_GUTS_ADDR);
	603	int num = 0;
	604	uint sdrs2_io_sel =
	605	(gur->pordevsr & MPC85xx_PORDEVSR_SRDS2_IO_SEL) >> 27;
	606
	607	#ifdef CONFIG_TSEC1
	608	SET_STD_TSEC_INFO(tsec_info[num], 1);
	609	if ((sdrs2_io_sel == 4) \|\| (sdrs2_io_sel == 6)) {
	610	tsec_info[num].phyaddr = 0;
	611	tsec_info[num].flags \|= TSEC_SGMII;
	612	}
	613	num++;
	614	#endif
	615	#ifdef CONFIG_TSEC3
	616	SET_STD_TSEC_INFO(tsec_info[num], 3);
	617	if (sdrs2_io_sel == 4) {
	618	tsec_info[num].phyaddr = 1;
	619	tsec_info[num].flags \|= TSEC_SGMII;
	620	}
	621	num++;
	622	#endif
	623
	624	if (!num) {
	625	printf("No TSECs initialized\n");
	626	return 0;
	627	}
	628
	629	if ((sdrs2_io_sel == 4) \|\| (sdrs2_io_sel == 6))
	630	fsl_sgmii_riser_init(tsec_info, num);
	631
	632	tsec_eth_init(bis, tsec_info, num);
	633	#endif
	634	return pci_eth_init(bis);
	635	}
	636
9490a7f1	637	#if defined(CONFIG_OF_BOARD_SETUP)
2dba0dea	638	extern void ft_fsl_pci_setup(void blob, const char pci_alias,
3cbd8231	639	struct pci_controller *hose);
9490a7f1	640
2dba0dea KG	641	void ft_board_setup(void blob, bd_t bd)
2dba0dea KG	642	{
9490a7f1 KG	643	ft_cpu_setup(blob, bd);
9490a7f1 KG	644
9490a7f1	645	#ifdef CONFIG_PCI1
2dba0dea	646	ft_fsl_pci_setup(blob, "pci0", &pci1_hose);
9490a7f1 KG	647	#endif
9490a7f1 KG	648	#ifdef CONFIG_PCIE2
2dba0dea	649	ft_fsl_pci_setup(blob, "pci1", &pcie2_hose);
9490a7f1	650	#endif
2dba0dea KG	651	#ifdef CONFIG_PCIE2
2dba0dea KG	652	ft_fsl_pci_setup(blob, "pci2", &pcie1_hose);
9490a7f1	653	#endif
2dba0dea KG	654	#ifdef CONFIG_PCIE1
2dba0dea KG	655	ft_fsl_pci_setup(blob, "pci3", &pcie3_hose);
9490a7f1	656	#endif
9490a7f1 KG	657	}
9490a7f1 KG	658	#endif