[J-u-boot.git] / board / amcc / yosemite / yosemite.c

/*
 * (C) Copyright 2006-2007
 * Stefan Roese, DENX Software Engineering, [email protected].
 *
 * See file CREDITS for list of people who contributed to this
 * project.
 *
 * This program is free software; you can redistribute it and/or
 * modify it under the terms of the GNU General Public License as
 * published by the Free Software Foundation; either version 2 of
 * the License, or (at your option) any later version.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
 * GNU General Public License for more details.
 *
 * You should have received a copy of the GNU General Public License
 * along with this program; if not, write to the Free Software
 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
 * MA 02111-1307 USA
 */

#include <common.h>
#include <ppc4xx.h>
#include <asm/processor.h>
#include <asm/io.h>
#include <spd_sdram.h>
#include <libfdt.h>
#include <fdt_support.h>

DECLARE_GLOBAL_DATA_PTR;

extern flash_info_t flash_info[CONFIG_SYS_MAX_FLASH_BANKS]; /* info for FLASH chips	*/

static inline u32 get_async_pci_freq(void)
{
	if (in_8((void *)(CONFIG_SYS_BCSR_BASE + 5)) &
		CONFIG_SYS_BCSR5_PCI66EN)
		return 66666666;
	else
		return 33333333;
}

int board_early_init_f(void)
{
	register uint reg;

	/*--------------------------------------------------------------------
	 * Setup the external bus controller/chip selects
	 *-------------------------------------------------------------------*/
	mtdcr(EBC0_CFGADDR, EBC0_CFG);
	reg = mfdcr(EBC0_CFGDATA);
	mtdcr(EBC0_CFGDATA, reg | 0x04000000);	/* Set ATC */

	/*--------------------------------------------------------------------
	 * Setup the GPIO pins
	 *-------------------------------------------------------------------*/
	/*CPLD cs */
	/*setup Address lines for flash size 64Meg. */
	out32(GPIO0_OSRL, in32(GPIO0_OSRL) | 0x50010000);
	out32(GPIO0_TSRL, in32(GPIO0_TSRL) | 0x50010000);
	out32(GPIO0_ISR1L, in32(GPIO0_ISR1L) | 0x50000000);

	/*setup emac */
	out32(GPIO0_TCR, in32(GPIO0_TCR) | 0xC080);
	out32(GPIO0_TSRL, in32(GPIO0_TSRL) | 0x40);
	out32(GPIO0_ISR1L, in32(GPIO0_ISR1L) | 0x55);
	out32(GPIO0_OSRH, in32(GPIO0_OSRH) | 0x50004000);
	out32(GPIO0_ISR1H, in32(GPIO0_ISR1H) | 0x00440000);

	/*UART1 */
	out32(GPIO1_TCR, in32(GPIO1_TCR) | 0x02000000);
	out32(GPIO1_OSRL, in32(GPIO1_OSRL) | 0x00080000);
	out32(GPIO1_ISR2L, in32(GPIO1_ISR2L) | 0x00010000);

	/* external interrupts IRQ0...3 */
	out32(GPIO1_TCR, in32(GPIO1_TCR) & ~0x00f00000);
	out32(GPIO1_TSRL, in32(GPIO1_TSRL) & ~0x0000ff00);
	out32(GPIO1_ISR1L, in32(GPIO1_ISR1L) | 0x00005500);

#ifdef CONFIG_440EP
	/*setup USB 2.0 */
	out32(GPIO1_TCR, in32(GPIO1_TCR) | 0xc0000000);
	out32(GPIO1_OSRL, in32(GPIO1_OSRL) | 0x50000000);
	out32(GPIO0_TCR, in32(GPIO0_TCR) | 0xf);
	out32(GPIO0_OSRH, in32(GPIO0_OSRH) | 0xaa);
	out32(GPIO0_ISR2H, in32(GPIO0_ISR2H) | 0x00000500);
#endif

	/*--------------------------------------------------------------------
	 * Setup the interrupt controller polarities, triggers, etc.
	 *-------------------------------------------------------------------*/
	mtdcr(UIC0SR, 0xffffffff);	/* clear all */
	mtdcr(UIC0ER, 0x00000000);	/* disable all */
	mtdcr(UIC0CR, 0x00000009);	/* ATI & UIC1 crit are critical */
	mtdcr(UIC0PR, 0xfffffe13);	/* per ref-board manual */
	mtdcr(UIC0TR, 0x01c00008);	/* per ref-board manual */
	mtdcr(UIC0VR, 0x00000001);	/* int31 highest, base=0x000 */
	mtdcr(UIC0SR, 0xffffffff);	/* clear all */

	mtdcr(UIC1SR, 0xffffffff);	/* clear all */
	mtdcr(UIC1ER, 0x00000000);	/* disable all */
	mtdcr(UIC1CR, 0x00000000);	/* all non-critical */
	mtdcr(UIC1PR, 0xffffe0ff);	/* per ref-board manual */
	mtdcr(UIC1TR, 0x00ffc000);	/* per ref-board manual */
	mtdcr(UIC1VR, 0x00000001);	/* int31 highest, base=0x000 */
	mtdcr(UIC1SR, 0xffffffff);	/* clear all */

	/*--------------------------------------------------------------------
	 * Setup other serial configuration
	 *-------------------------------------------------------------------*/
	mfsdr(SDR0_PCI0, reg);
	mtsdr(SDR0_PCI0, 0x80000000 | reg);	/* PCI arbiter enabled */
	mtsdr(SDR0_PFC0, 0x00003e00);	/* Pin function */
	mtsdr(SDR0_PFC1, 0x00048000);	/* Pin function: UART0 has 4 pins */

	/* Check and reconfigure the PCI sync clock if necessary */
	ppc4xx_pci_sync_clock_config(get_async_pci_freq());

	/*clear tmrclk divisor */
	*(unsigned char *)(CONFIG_SYS_BCSR_BASE | 0x04) = 0x00;

	/*enable ethernet */
	*(unsigned char *)(CONFIG_SYS_BCSR_BASE | 0x08) = 0xf0;

#ifdef CONFIG_440EP
	/*enable usb 1.1 fs device and remove usb 2.0 reset */
	*(unsigned char *)(CONFIG_SYS_BCSR_BASE | 0x09) = 0x00;
#endif

	/*get rid of flash write protect */
	*(unsigned char *)(CONFIG_SYS_BCSR_BASE | 0x07) = 0x00;

	return 0;
}

int misc_init_r (void)
{
	uint pbcr;
	int size_val = 0;

	/* Re-do sizing to get full correct info */
	mtdcr(EBC0_CFGADDR, PB0CR);
	pbcr = mfdcr(EBC0_CFGDATA);
	switch (gd->bd->bi_flashsize) {
	case 1 << 20:
		size_val = 0;
		break;
	case 2 << 20:
		size_val = 1;
		break;
	case 4 << 20:
		size_val = 2;
		break;
	case 8 << 20:
		size_val = 3;
		break;
	case 16 << 20:
		size_val = 4;
		break;
	case 32 << 20:
		size_val = 5;
		break;
	case 64 << 20:
		size_val = 6;
		break;
	case 128 << 20:
		size_val = 7;
		break;
	}
	pbcr = (pbcr & 0x0001ffff) | gd->bd->bi_flashstart | (size_val << 17);
	mtdcr(EBC0_CFGADDR, PB0CR);
	mtdcr(EBC0_CFGDATA, pbcr);

	/* adjust flash start and offset */
	gd->bd->bi_flashstart = 0 - gd->bd->bi_flashsize;
	gd->bd->bi_flashoffset = 0;

	/* Monitor protection ON by default */
	(void)flash_protect(FLAG_PROTECT_SET,
			    -CONFIG_SYS_MONITOR_LEN,
			    0xffffffff,
			    &flash_info[0]);

	return 0;
}

int checkboard(void)
{
	char *s = getenv("serial#");
	u8 rev;
	u32 clock = get_async_pci_freq();

#ifdef CONFIG_440EP
	printf("Board: Yosemite - AMCC PPC440EP Evaluation Board");
#else
	printf("Board: Yellowstone - AMCC PPC440GR Evaluation Board");
#endif

	rev = in_8((void *)(CONFIG_SYS_BCSR_BASE + 0));
	printf(", Rev. %X, PCI-Async=%d MHz", rev, clock / 1000000);

	if (s != NULL) {
		puts(", serial# ");
		puts(s);
	}
	putc('\n');

	/*
	 * Reconfiguration of the PCI sync clock is already done,
	 * now check again if everything is in range:
	 */
	if (ppc4xx_pci_sync_clock_config(clock)) {
		printf("ERROR: PCI clocking incorrect (async=%d "
		       "sync=%ld)!\n", clock, get_PCI_freq());
	}

	return (0);
}

/*************************************************************************
 *  initdram -- doesn't use serial presence detect.
 *
 *  Assumes:    256 MB, ECC, non-registered
 *              PLB @ 133 MHz
 *
 ************************************************************************/
#define NUM_TRIES 64
#define NUM_READS 10

void sdram_tr1_set(int ram_address, int* tr1_value)
{
	int i;
	int j, k;
	volatile unsigned int* ram_pointer =  (unsigned int*)ram_address;
	int first_good = -1, last_bad = 0x1ff;

	unsigned long test[NUM_TRIES] = {
		0x00000000, 0x00000000, 0xFFFFFFFF, 0xFFFFFFFF,
		0x00000000, 0x00000000, 0xFFFFFFFF, 0xFFFFFFFF,
		0xFFFFFFFF, 0xFFFFFFFF, 0x00000000, 0x00000000,
		0xFFFFFFFF, 0xFFFFFFFF, 0x00000000, 0x00000000,
		0xAAAAAAAA, 0xAAAAAAAA, 0x55555555, 0x55555555,
		0xAAAAAAAA, 0xAAAAAAAA, 0x55555555, 0x55555555,
		0x55555555, 0x55555555, 0xAAAAAAAA, 0xAAAAAAAA,
		0x55555555, 0x55555555, 0xAAAAAAAA, 0xAAAAAAAA,
		0xA5A5A5A5, 0xA5A5A5A5, 0x5A5A5A5A, 0x5A5A5A5A,
		0xA5A5A5A5, 0xA5A5A5A5, 0x5A5A5A5A, 0x5A5A5A5A,
		0x5A5A5A5A, 0x5A5A5A5A, 0xA5A5A5A5, 0xA5A5A5A5,
		0x5A5A5A5A, 0x5A5A5A5A, 0xA5A5A5A5, 0xA5A5A5A5,
		0xAA55AA55, 0xAA55AA55, 0x55AA55AA, 0x55AA55AA,
		0xAA55AA55, 0xAA55AA55, 0x55AA55AA, 0x55AA55AA,
		0x55AA55AA, 0x55AA55AA, 0xAA55AA55, 0xAA55AA55,
		0x55AA55AA, 0x55AA55AA, 0xAA55AA55, 0xAA55AA55 };

	/* go through all possible SDRAM0_TR1[RDCT] values */
	for (i=0; i<=0x1ff; i++) {
		/* set the current value for TR1 */
		mtsdram(SDRAM0_TR1, (0x80800800 | i));

		/* write values */
		for (j=0; j<NUM_TRIES; j++) {
			ram_pointer[j] = test[j];

			/* clear any cache at ram location */
			__asm__("dcbf 0,%0": :"r" (&ram_pointer[j]));
		}

		/* read values back */
		for (j=0; j<NUM_TRIES; j++) {
			for (k=0; k<NUM_READS; k++) {
				/* clear any cache at ram location */
				__asm__("dcbf 0,%0": :"r" (&ram_pointer[j]));

				if (ram_pointer[j] != test[j])
					break;
			}

			/* read error */
			if (k != NUM_READS) {
				break;
			}
		}

		/* we have a SDRAM0_TR1[RDCT] that is part of the window */
		if (j == NUM_TRIES) {
			if (first_good == -1)
				first_good = i;		/* found beginning of window */
		} else { /* bad read */
			/* if we have not had a good read then don't care */
			if(first_good != -1) {
				/* first failure after a good read */
				last_bad = i-1;
				break;
			}
		}
	}

	/* return the current value for TR1 */
	*tr1_value = (first_good + last_bad) / 2;
}

phys_size_t initdram(int board)
{
	register uint reg;
	int tr1_bank1, tr1_bank2;

	/*--------------------------------------------------------------------
	 * Setup some default
	 *------------------------------------------------------------------*/
	mtsdram(SDRAM0_UABBA, 0x00000000);	/* ubba=0 (default)             */
	mtsdram(SDRAM0_SLIO, 0x00000000);	/* rdre=0 wrre=0 rarw=0         */
	mtsdram(SDRAM0_DEVOPT, 0x00000000);	/* dll=0 ds=0 (normal)          */
	mtsdram(SDRAM0_CLKTR, 0x40000000);	/* ?? */
	mtsdram(SDRAM0_WDDCTR, 0x40000000);	/* ?? */

	/*clear this first, if the DDR is enabled by a debugger
	  then you can not make changes. */
	mtsdram(SDRAM0_CFG0, 0x00000000);	/* Disable EEC */

	/*--------------------------------------------------------------------
	 * Setup for board-specific specific mem
	 *------------------------------------------------------------------*/
	/*
	 * Following for CAS Latency = 2.5 @ 133 MHz PLB
	 */
	mtsdram(SDRAM0_B0CR, 0x000a4001);	/* SDBA=0x000 128MB, Mode 3, enabled */
	mtsdram(SDRAM0_B1CR, 0x080a4001);	/* SDBA=0x080 128MB, Mode 3, enabled */

	mtsdram(SDRAM0_TR0, 0x410a4012);	/* ?? */
	mtsdram(SDRAM0_RTR, 0x04080000);	/* ?? */
	mtsdram(SDRAM0_CFG1, 0x00000000);	/* Self-refresh exit, disable PM    */
	mtsdram(SDRAM0_CFG0, 0x30000000);	/* Disable EEC */
	udelay(400);		/* Delay 200 usecs (min)            */

	/*--------------------------------------------------------------------
	 * Enable the controller, then wait for DCEN to complete
	 *------------------------------------------------------------------*/
	mtsdram(SDRAM0_CFG0, 0x80000000);	/* Enable */

	for (;;) {
		mfsdram(SDRAM0_MCSTS, reg);
		if (reg & 0x80000000)
			break;
	}

	sdram_tr1_set(0x00000000, &tr1_bank1);
	sdram_tr1_set(0x08000000, &tr1_bank2);
	mtsdram(SDRAM0_TR1, (((tr1_bank1+tr1_bank2)/2) | 0x80800800));

	return CONFIG_SYS_SDRAM_BANKS * (CONFIG_SYS_KBYTES_SDRAM * 1024);	/* return bytes */
}

/*************************************************************************
 *  pci_pre_init
 *
 *  This routine is called just prior to registering the hose and gives
 *  the board the opportunity to check things. Returning a value of zero
 *  indicates that things are bad & PCI initialization should be aborted.
 *
 *	Different boards may wish to customize the pci controller structure
 *	(add regions, override default access routines, etc) or perform
 *	certain pre-initialization actions.
 *
 ************************************************************************/
#if defined(CONFIG_PCI)
int pci_pre_init(struct pci_controller *hose)
{
	unsigned long addr;

	/*-------------------------------------------------------------------------+
	  | Set priority for all PLB3 devices to 0.
	  | Set PLB3 arbiter to fair mode.
	  +-------------------------------------------------------------------------*/
	mfsdr(SD0_AMP1, addr);
	mtsdr(SD0_AMP1, (addr & 0x000000FF) | 0x0000FF00);
	addr = mfdcr(PLB3_ACR);
	mtdcr(PLB3_ACR, addr | 0x80000000);

	/*-------------------------------------------------------------------------+
	  | Set priority for all PLB4 devices to 0.
	  +-------------------------------------------------------------------------*/
	mfsdr(SD0_AMP0, addr);
	mtsdr(SD0_AMP0, (addr & 0x000000FF) | 0x0000FF00);
	addr = mfdcr(PLB4_ACR) | 0xa0000000;	/* Was 0x8---- */
	mtdcr(PLB4_ACR, addr);

	/*-------------------------------------------------------------------------+
	  | Set Nebula PLB4 arbiter to fair mode.
	  +-------------------------------------------------------------------------*/
	/* Segment0 */
	addr = (mfdcr(PLB0_ACR) & ~PLB0_ACR_PPM_MASK) | PLB0_ACR_PPM_FAIR;
	addr = (addr & ~PLB0_ACR_HBU_MASK) | PLB0_ACR_HBU_ENABLED;
	addr = (addr & ~PLB0_ACR_RDP_MASK) | PLB0_ACR_RDP_4DEEP;
	addr = (addr & ~PLB0_ACR_WRP_MASK) | PLB0_ACR_WRP_2DEEP;
	mtdcr(PLB0_ACR, addr);

	/* Segment1 */
	addr = (mfdcr(PLB1_ACR) & ~PLB1_ACR_PPM_MASK) | PLB1_ACR_PPM_FAIR;
	addr = (addr & ~PLB1_ACR_HBU_MASK) | PLB1_ACR_HBU_ENABLED;
	addr = (addr & ~PLB1_ACR_RDP_MASK) | PLB1_ACR_RDP_4DEEP;
	addr = (addr & ~PLB1_ACR_WRP_MASK) | PLB1_ACR_WRP_2DEEP;
	mtdcr(PLB1_ACR, addr);

	return 1;
}
#endif	/* defined(CONFIG_PCI) */

/*************************************************************************
 *  pci_target_init
 *
 *	The bootstrap configuration provides default settings for the pci
 *	inbound map (PIM). But the bootstrap config choices are limited and
 *	may not be sufficient for a given board.
 *
 ************************************************************************/
#if defined(CONFIG_PCI) && defined(CONFIG_SYS_PCI_TARGET_INIT)
void pci_target_init(struct pci_controller *hose)
{
	/*--------------------------------------------------------------------------+
	 * Set up Direct MMIO registers
	 *--------------------------------------------------------------------------*/
	/*--------------------------------------------------------------------------+
	  | PowerPC440 EP PCI Master configuration.
	  | Map one 1Gig range of PLB/processor addresses to PCI memory space.
	  |   PLB address 0xA0000000-0xDFFFFFFF ==> PCI address 0xA0000000-0xDFFFFFFF
	  |   Use byte reversed out routines to handle endianess.
	  | Make this region non-prefetchable.
	  +--------------------------------------------------------------------------*/
	out32r(PCIL0_PMM0MA, 0x00000000);	/* PMM0 Mask/Attribute - disabled b4 setting */
	out32r(PCIL0_PMM0LA, CONFIG_SYS_PCI_MEMBASE);	/* PMM0 Local Address */
	out32r(PCIL0_PMM0PCILA, CONFIG_SYS_PCI_MEMBASE);	/* PMM0 PCI Low Address */
	out32r(PCIL0_PMM0PCIHA, 0x00000000);	/* PMM0 PCI High Address */
	out32r(PCIL0_PMM0MA, 0xE0000001);	/* 512M + No prefetching, and enable region */

	out32r(PCIL0_PMM1MA, 0x00000000);	/* PMM0 Mask/Attribute - disabled b4 setting */
	out32r(PCIL0_PMM1LA, CONFIG_SYS_PCI_MEMBASE2);	/* PMM0 Local Address */
	out32r(PCIL0_PMM1PCILA, CONFIG_SYS_PCI_MEMBASE2);	/* PMM0 PCI Low Address */
	out32r(PCIL0_PMM1PCIHA, 0x00000000);	/* PMM0 PCI High Address */
	out32r(PCIL0_PMM1MA, 0xE0000001);	/* 512M + No prefetching, and enable region */

	out32r(PCIL0_PTM1MS, 0x00000001);	/* Memory Size/Attribute */
	out32r(PCIL0_PTM1LA, 0);	/* Local Addr. Reg */
	out32r(PCIL0_PTM2MS, 0);	/* Memory Size/Attribute */
	out32r(PCIL0_PTM2LA, 0);	/* Local Addr. Reg */

	/*--------------------------------------------------------------------------+
	 * Set up Configuration registers
	 *--------------------------------------------------------------------------*/

	/* Program the board's subsystem id/vendor id */
	pci_write_config_word(0, PCI_SUBSYSTEM_VENDOR_ID,
			      CONFIG_SYS_PCI_SUBSYS_VENDORID);
	pci_write_config_word(0, PCI_SUBSYSTEM_ID, CONFIG_SYS_PCI_SUBSYS_ID);

	/* Configure command register as bus master */
	pci_write_config_word(0, PCI_COMMAND, PCI_COMMAND_MASTER);

	/* 240nS PCI clock */
	pci_write_config_word(0, PCI_LATENCY_TIMER, 1);

	/* No error reporting */
	pci_write_config_word(0, PCI_ERREN, 0);

	pci_write_config_dword(0, PCI_BRDGOPT2, 0x00000101);

}
#endif				/* defined(CONFIG_PCI) && defined(CONFIG_SYS_PCI_TARGET_INIT) */

/*************************************************************************
 *  pci_master_init
 *
 ************************************************************************/
#if defined(CONFIG_PCI) && defined(CONFIG_SYS_PCI_MASTER_INIT)
void pci_master_init(struct pci_controller *hose)
{
	unsigned short temp_short;

	/*--------------------------------------------------------------------------+
	  | Write the PowerPC440 EP PCI Configuration regs.
	  |   Enable PowerPC440 EP to be a master on the PCI bus (PMM).
	  |   Enable PowerPC440 EP to act as a PCI memory target (PTM).
	  +--------------------------------------------------------------------------*/
	pci_read_config_word(0, PCI_COMMAND, &temp_short);
	pci_write_config_word(0, PCI_COMMAND,
			      temp_short | PCI_COMMAND_MASTER |
			      PCI_COMMAND_MEMORY);
}
#endif				/* defined(CONFIG_PCI) && defined(CONFIG_SYS_PCI_MASTER_INIT) */

/*************************************************************************
 *  hw_watchdog_reset
 *
 *	This routine is called to reset (keep alive) the watchdog timer
 *
 ************************************************************************/
#if defined(CONFIG_HW_WATCHDOG)
void hw_watchdog_reset(void)
{

}
#endif

void board_reset(void)
{
	/* give reset to BCSR */
	*(unsigned char *)(CONFIG_SYS_BCSR_BASE | 0x06) = 0x09;
}
Commit	Line	Data
c157d8e2	1	/*
5a5958b7 SR	2	* (C) Copyright 2006-2007
5a5958b7 SR	3	* Stefan Roese, DENX Software Engineering, [email protected].
c157d8e2 SR	4	*
	5	* See file CREDITS for list of people who contributed to this
	6	* project.
	7	*
	8	* This program is free software; you can redistribute it and/or
	9	* modify it under the terms of the GNU General Public License as
	10	* published by the Free Software Foundation; either version 2 of
	11	* the License, or (at your option) any later version.
	12	*
	13	* This program is distributed in the hope that it will be useful,
	14	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	15	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	16	* GNU General Public License for more details.
	17	*
	18	* You should have received a copy of the GNU General Public License
	19	* along with this program; if not, write to the Free Software
	20	* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
	21	* MA 02111-1307 USA
	22	*/
	23
	24	#include <common.h>
84286386	25	#include <ppc4xx.h>
c157d8e2	26	#include <asm/processor.h>
5a5958b7	27	#include <asm/io.h>
c157d8e2	28	#include <spd_sdram.h>
4adb3023 IS	29	#include <libfdt.h>
4adb3023 IS	30	#include <fdt_support.h>
c157d8e2	31
d87080b7 WD	32	DECLARE_GLOBAL_DATA_PTR;
d87080b7 WD	33
6d0f6bcf	34	extern flash_info_t flash_info[CONFIG_SYS_MAX_FLASH_BANKS]; /* info for FLASH chips */
84286386	35
c85b5839 SR	36	static inline u32 get_async_pci_freq(void)
	37	{
	38	if (in_8((void *)(CONFIG_SYS_BCSR_BASE + 5)) &
	39	CONFIG_SYS_BCSR5_PCI66EN)
	40	return 66666666;
	41	else
	42	return 33333333;
	43	}
	44
c157d8e2 SR	45	int board_early_init_f(void)
	46	{
	47	register uint reg;
	48
	49	/*--------------------------------------------------------------------
	50	* Setup the external bus controller/chip selects
	51	-------------------------------------------------------------------/
d1c3b275 SR	52	mtdcr(EBC0_CFGADDR, EBC0_CFG);
	53	reg = mfdcr(EBC0_CFGDATA);
	54	mtdcr(EBC0_CFGDATA, reg \| 0x04000000); /* Set ATC */
c157d8e2	55
c157d8e2 SR	56	/*--------------------------------------------------------------------
	57	* Setup the GPIO pins
	58	-------------------------------------------------------------------/
	59	/CPLD cs /
81a3170b SR	60	/setup Address lines for flash size 64Meg. /
	61	out32(GPIO0_OSRL, in32(GPIO0_OSRL) \| 0x50010000);
	62	out32(GPIO0_TSRL, in32(GPIO0_TSRL) \| 0x50010000);
	63	out32(GPIO0_ISR1L, in32(GPIO0_ISR1L) \| 0x50000000);
c157d8e2 SR	64
	65	/setup emac /
	66	out32(GPIO0_TCR, in32(GPIO0_TCR) \| 0xC080);
	67	out32(GPIO0_TSRL, in32(GPIO0_TSRL) \| 0x40);
	68	out32(GPIO0_ISR1L, in32(GPIO0_ISR1L) \| 0x55);
	69	out32(GPIO0_OSRH, in32(GPIO0_OSRH) \| 0x50004000);
	70	out32(GPIO0_ISR1H, in32(GPIO0_ISR1H) \| 0x00440000);
	71
	72	/UART1 /
	73	out32(GPIO1_TCR, in32(GPIO1_TCR) \| 0x02000000);
	74	out32(GPIO1_OSRL, in32(GPIO1_OSRL) \| 0x00080000);
	75	out32(GPIO1_ISR2L, in32(GPIO1_ISR2L) \| 0x00010000);
	76
e190290b	77	/* external interrupts IRQ0...3 */
b9b2480f WD	78	out32(GPIO1_TCR, in32(GPIO1_TCR) & ~0x00f00000);
b9b2480f WD	79	out32(GPIO1_TSRL, in32(GPIO1_TSRL) & ~0x0000ff00);
e190290b SR	80	out32(GPIO1_ISR1L, in32(GPIO1_ISR1L) \| 0x00005500);
e190290b SR	81
700200c6	82	#ifdef CONFIG_440EP
c157d8e2 SR	83	/setup USB 2.0 /
	84	out32(GPIO1_TCR, in32(GPIO1_TCR) \| 0xc0000000);
	85	out32(GPIO1_OSRL, in32(GPIO1_OSRL) \| 0x50000000);
	86	out32(GPIO0_TCR, in32(GPIO0_TCR) \| 0xf);
	87	out32(GPIO0_OSRH, in32(GPIO0_OSRH) \| 0xaa);
	88	out32(GPIO0_ISR2H, in32(GPIO0_ISR2H) \| 0x00000500);
700200c6	89	#endif
c157d8e2	90
ef04a0aa SR	91	/*--------------------------------------------------------------------
	92	* Setup the interrupt controller polarities, triggers, etc.
	93	-------------------------------------------------------------------/
952e7760 SR	94	mtdcr(UIC0SR, 0xffffffff); /* clear all */
	95	mtdcr(UIC0ER, 0x00000000); /* disable all */
	96	mtdcr(UIC0CR, 0x00000009); /* ATI & UIC1 crit are critical */
	97	mtdcr(UIC0PR, 0xfffffe13); /* per ref-board manual */
	98	mtdcr(UIC0TR, 0x01c00008); /* per ref-board manual */
	99	mtdcr(UIC0VR, 0x00000001); /* int31 highest, base=0x000 */
	100	mtdcr(UIC0SR, 0xffffffff); /* clear all */
ef04a0aa	101
952e7760 SR	102	mtdcr(UIC1SR, 0xffffffff); /* clear all */
	103	mtdcr(UIC1ER, 0x00000000); /* disable all */
	104	mtdcr(UIC1CR, 0x00000000); /* all non-critical */
	105	mtdcr(UIC1PR, 0xffffe0ff); /* per ref-board manual */
	106	mtdcr(UIC1TR, 0x00ffc000); /* per ref-board manual */
	107	mtdcr(UIC1VR, 0x00000001); /* int31 highest, base=0x000 */
	108	mtdcr(UIC1SR, 0xffffffff); /* clear all */
ef04a0aa	109
c157d8e2 SR	110	/*--------------------------------------------------------------------
	111	* Setup other serial configuration
	112	-------------------------------------------------------------------/
d1c3b275 SR	113	mfsdr(SDR0_PCI0, reg);
	114	mtsdr(SDR0_PCI0, 0x80000000 \| reg); /* PCI arbiter enabled */
	115	mtsdr(SDR0_PFC0, 0x00003e00); /* Pin function */
	116	mtsdr(SDR0_PFC1, 0x00048000); /* Pin function: UART0 has 4 pins */
c157d8e2	117
c85b5839 SR	118	/* Check and reconfigure the PCI sync clock if necessary */
	119	ppc4xx_pci_sync_clock_config(get_async_pci_freq());
	120
c157d8e2	121	/clear tmrclk divisor /
6d0f6bcf	122	(unsigned char )(CONFIG_SYS_BCSR_BASE \| 0x04) = 0x00;
c157d8e2 SR	123
c157d8e2 SR	124	/enable ethernet /
6d0f6bcf	125	(unsigned char )(CONFIG_SYS_BCSR_BASE \| 0x08) = 0xf0;
c157d8e2	126
700200c6	127	#ifdef CONFIG_440EP
c157d8e2	128	/enable usb 1.1 fs device and remove usb 2.0 reset /
6d0f6bcf	129	(unsigned char )(CONFIG_SYS_BCSR_BASE \| 0x09) = 0x00;
700200c6	130	#endif
c157d8e2 SR	131
c157d8e2 SR	132	/get rid of flash write protect /
6d0f6bcf	133	(unsigned char )(CONFIG_SYS_BCSR_BASE \| 0x07) = 0x00;
c157d8e2 SR	134
	135	return 0;
	136	}
	137
84286386 SR	138	int misc_init_r (void)
84286386 SR	139	{
84286386 SR	140	uint pbcr;
	141	int size_val = 0;
	142
	143	/* Re-do sizing to get full correct info */
d1c3b275 SR	144	mtdcr(EBC0_CFGADDR, PB0CR);
d1c3b275 SR	145	pbcr = mfdcr(EBC0_CFGDATA);
84286386 SR	146	switch (gd->bd->bi_flashsize) {
	147	case 1 << 20:
	148	size_val = 0;
	149	break;
	150	case 2 << 20:
	151	size_val = 1;
	152	break;
	153	case 4 << 20:
	154	size_val = 2;
	155	break;
	156	case 8 << 20:
	157	size_val = 3;
	158	break;
	159	case 16 << 20:
	160	size_val = 4;
	161	break;
	162	case 32 << 20:
	163	size_val = 5;
	164	break;
	165	case 64 << 20:
	166	size_val = 6;
	167	break;
	168	case 128 << 20:
	169	size_val = 7;
	170	break;
	171	}
	172	pbcr = (pbcr & 0x0001ffff) \| gd->bd->bi_flashstart \| (size_val << 17);
d1c3b275 SR	173	mtdcr(EBC0_CFGADDR, PB0CR);
d1c3b275 SR	174	mtdcr(EBC0_CFGDATA, pbcr);
84286386	175
f190c11b SR	176	/* adjust flash start and offset */
	177	gd->bd->bi_flashstart = 0 - gd->bd->bi_flashsize;
	178	gd->bd->bi_flashoffset = 0;
	179
84286386 SR	180	/* Monitor protection ON by default */
84286386 SR	181	(void)flash_protect(FLAG_PROTECT_SET,
6d0f6bcf	182	-CONFIG_SYS_MONITOR_LEN,
84286386 SR	183	0xffffffff,
	184	&flash_info[0]);
	185
	186	return 0;
	187	}
	188
c157d8e2 SR	189	int checkboard(void)
c157d8e2 SR	190	{
3d9569b2	191	char *s = getenv("serial#");
36adff36	192	u8 rev;
c85b5839	193	u32 clock = get_async_pci_freq();
c157d8e2	194
700200c6	195	#ifdef CONFIG_440EP
93b17ec3	196	printf("Board: Yosemite - AMCC PPC440EP Evaluation Board");
700200c6 SR	197	#else
	198	printf("Board: Yellowstone - AMCC PPC440GR Evaluation Board");
	199	#endif
36adff36	200
6d0f6bcf	201	rev = in_8((void *)(CONFIG_SYS_BCSR_BASE + 0));
c85b5839	202	printf(", Rev. %X, PCI-Async=%d MHz", rev, clock / 1000000);
36adff36	203
93b17ec3 SR	204	if (s != NULL) {
	205	puts(", serial# ");
	206	puts(s);
	207	}
	208	putc('\n');
	209
c85b5839 SR	210	/*
	211	* Reconfiguration of the PCI sync clock is already done,
	212	* now check again if everything is in range:
	213	*/
	214	if (ppc4xx_pci_sync_clock_config(clock)) {
	215	printf("ERROR: PCI clocking incorrect (async=%d "
	216	"sync=%ld)!\n", clock, get_PCI_freq());
	217	}
	218
c157d8e2 SR	219	return (0);
	220	}
	221
	222	/*************************************************************************
bbeff30c	223	* initdram -- doesn't use serial presence detect.
c157d8e2 SR	224	*
	225	* Assumes: 256 MB, ECC, non-registered
	226	* PLB @ 133 MHz
	227	*
	228	************************************************************************/
81a3170b SR	229	#define NUM_TRIES 64
	230	#define NUM_READS 10
	231
	232	void sdram_tr1_set(int ram_address, int* tr1_value)
	233	{
	234	int i;
	235	int j, k;
	236	volatile unsigned int* ram_pointer = (unsigned int*)ram_address;
	237	int first_good = -1, last_bad = 0x1ff;
	238
	239	unsigned long test[NUM_TRIES] = {
	240	0x00000000, 0x00000000, 0xFFFFFFFF, 0xFFFFFFFF,
	241	0x00000000, 0x00000000, 0xFFFFFFFF, 0xFFFFFFFF,
	242	0xFFFFFFFF, 0xFFFFFFFF, 0x00000000, 0x00000000,
	243	0xFFFFFFFF, 0xFFFFFFFF, 0x00000000, 0x00000000,
	244	0xAAAAAAAA, 0xAAAAAAAA, 0x55555555, 0x55555555,
	245	0xAAAAAAAA, 0xAAAAAAAA, 0x55555555, 0x55555555,
	246	0x55555555, 0x55555555, 0xAAAAAAAA, 0xAAAAAAAA,
	247	0x55555555, 0x55555555, 0xAAAAAAAA, 0xAAAAAAAA,
	248	0xA5A5A5A5, 0xA5A5A5A5, 0x5A5A5A5A, 0x5A5A5A5A,
	249	0xA5A5A5A5, 0xA5A5A5A5, 0x5A5A5A5A, 0x5A5A5A5A,
	250	0x5A5A5A5A, 0x5A5A5A5A, 0xA5A5A5A5, 0xA5A5A5A5,
	251	0x5A5A5A5A, 0x5A5A5A5A, 0xA5A5A5A5, 0xA5A5A5A5,
	252	0xAA55AA55, 0xAA55AA55, 0x55AA55AA, 0x55AA55AA,
	253	0xAA55AA55, 0xAA55AA55, 0x55AA55AA, 0x55AA55AA,
	254	0x55AA55AA, 0x55AA55AA, 0xAA55AA55, 0xAA55AA55,
	255	0x55AA55AA, 0x55AA55AA, 0xAA55AA55, 0xAA55AA55 };
	256
	257	/* go through all possible SDRAM0_TR1[RDCT] values */
	258	for (i=0; i<=0x1ff; i++) {
	259	/* set the current value for TR1 */
95b602ba	260	mtsdram(SDRAM0_TR1, (0x80800800 \| i));
81a3170b SR	261
	262	/* write values */
	263	for (j=0; j<NUM_TRIES; j++) {
	264	ram_pointer[j] = test[j];
	265
	266	/* clear any cache at ram location */
	267	__asm__("dcbf 0,%0": :"r" (&ram_pointer[j]));
	268	}
	269
	270	/* read values back */
	271	for (j=0; j<NUM_TRIES; j++) {
	272	for (k=0; k<NUM_READS; k++) {
	273	/* clear any cache at ram location */
	274	__asm__("dcbf 0,%0": :"r" (&ram_pointer[j]));
	275
	276	if (ram_pointer[j] != test[j])
	277	break;
	278	}
	279
	280	/* read error */
	281	if (k != NUM_READS) {
	282	break;
	283	}
	284	}
	285
	286	/* we have a SDRAM0_TR1[RDCT] that is part of the window */
	287	if (j == NUM_TRIES) {
	288	if (first_good == -1)
	289	first_good = i; /* found beginning of window */
	290	} else { /* bad read */
	291	/* if we have not had a good read then don't care */
	292	if(first_good != -1) {
	293	/* first failure after a good read */
	294	last_bad = i-1;
	295	break;
	296	}
	297	}
	298	}
	299
	300	/* return the current value for TR1 */
	301	*tr1_value = (first_good + last_bad) / 2;
	302	}
	303
9973e3c6	304	phys_size_t initdram(int board)
c157d8e2 SR	305	{
c157d8e2 SR	306	register uint reg;
81a3170b	307	int tr1_bank1, tr1_bank2;
c157d8e2 SR	308
	309	/*--------------------------------------------------------------------
	310	* Setup some default
	311	------------------------------------------------------------------/
95b602ba SR	312	mtsdram(SDRAM0_UABBA, 0x00000000); /* ubba=0 (default) */
	313	mtsdram(SDRAM0_SLIO, 0x00000000); /* rdre=0 wrre=0 rarw=0 */
	314	mtsdram(SDRAM0_DEVOPT, 0x00000000); /* dll=0 ds=0 (normal) */
	315	mtsdram(SDRAM0_CLKTR, 0x40000000); /* ?? */
	316	mtsdram(SDRAM0_WDDCTR, 0x40000000); /* ?? */
c157d8e2 SR	317
c157d8e2 SR	318	/*clear this first, if the DDR is enabled by a debugger
81a3170b	319	then you can not make changes. */
95b602ba	320	mtsdram(SDRAM0_CFG0, 0x00000000); /* Disable EEC */
c157d8e2 SR	321
	322	/*--------------------------------------------------------------------
	323	* Setup for board-specific specific mem
	324	------------------------------------------------------------------/
	325	/*
	326	* Following for CAS Latency = 2.5 @ 133 MHz PLB
	327	*/
95b602ba SR	328	mtsdram(SDRAM0_B0CR, 0x000a4001); /* SDBA=0x000 128MB, Mode 3, enabled */
95b602ba SR	329	mtsdram(SDRAM0_B1CR, 0x080a4001); /* SDBA=0x080 128MB, Mode 3, enabled */
c157d8e2	330
95b602ba SR	331	mtsdram(SDRAM0_TR0, 0x410a4012); /* ?? */
	332	mtsdram(SDRAM0_RTR, 0x04080000); /* ?? */
	333	mtsdram(SDRAM0_CFG1, 0x00000000); /* Self-refresh exit, disable PM */
	334	mtsdram(SDRAM0_CFG0, 0x30000000); /* Disable EEC */
c157d8e2 SR	335	udelay(400); /* Delay 200 usecs (min) */
	336
	337	/*--------------------------------------------------------------------
	338	* Enable the controller, then wait for DCEN to complete
	339	------------------------------------------------------------------/
95b602ba	340	mtsdram(SDRAM0_CFG0, 0x80000000); /* Enable */
c157d8e2 SR	341
c157d8e2 SR	342	for (;;) {
95b602ba	343	mfsdram(SDRAM0_MCSTS, reg);
c157d8e2 SR	344	if (reg & 0x80000000)
	345	break;
	346	}
81a3170b SR	347
	348	sdram_tr1_set(0x00000000, &tr1_bank1);
	349	sdram_tr1_set(0x08000000, &tr1_bank2);
95b602ba	350	mtsdram(SDRAM0_TR1, (((tr1_bank1+tr1_bank2)/2) \| 0x80800800));
c157d8e2	351
6d0f6bcf	352	return CONFIG_SYS_SDRAM_BANKS * (CONFIG_SYS_KBYTES_SDRAM * 1024); /* return bytes */
c157d8e2 SR	353	}
c157d8e2 SR	354
c157d8e2 SR	355	/*************************************************************************
	356	* pci_pre_init
	357	*
	358	* This routine is called just prior to registering the hose and gives
	359	* the board the opportunity to check things. Returning a value of zero
	360	* indicates that things are bad & PCI initialization should be aborted.
	361	*
	362	* Different boards may wish to customize the pci controller structure
	363	* (add regions, override default access routines, etc) or perform
	364	* certain pre-initialization actions.
	365	*
	366	************************************************************************/
466fff1a	367	#if defined(CONFIG_PCI)
c157d8e2 SR	368	int pci_pre_init(struct pci_controller *hose)
c157d8e2 SR	369	{
c157d8e2 SR	370	unsigned long addr;
c157d8e2 SR	371
c157d8e2 SR	372	/*-------------------------------------------------------------------------+
	373	\| Set priority for all PLB3 devices to 0.
	374	\| Set PLB3 arbiter to fair mode.
	375	+-------------------------------------------------------------------------*/
d1c3b275 SR	376	mfsdr(SD0_AMP1, addr);
	377	mtsdr(SD0_AMP1, (addr & 0x000000FF) \| 0x0000FF00);
	378	addr = mfdcr(PLB3_ACR);
	379	mtdcr(PLB3_ACR, addr \| 0x80000000);
c157d8e2 SR	380
	381	/*-------------------------------------------------------------------------+
	382	\| Set priority for all PLB4 devices to 0.
	383	+-------------------------------------------------------------------------*/
d1c3b275 SR	384	mfsdr(SD0_AMP0, addr);
	385	mtsdr(SD0_AMP0, (addr & 0x000000FF) \| 0x0000FF00);
	386	addr = mfdcr(PLB4_ACR) \| 0xa0000000; /* Was 0x8---- */
	387	mtdcr(PLB4_ACR, addr);
c157d8e2 SR	388
	389	/*-------------------------------------------------------------------------+
	390	\| Set Nebula PLB4 arbiter to fair mode.
	391	+-------------------------------------------------------------------------*/
	392	/* Segment0 */
d1c3b275 SR	393	addr = (mfdcr(PLB0_ACR) & ~PLB0_ACR_PPM_MASK) \| PLB0_ACR_PPM_FAIR;
	394	addr = (addr & ~PLB0_ACR_HBU_MASK) \| PLB0_ACR_HBU_ENABLED;
	395	addr = (addr & ~PLB0_ACR_RDP_MASK) \| PLB0_ACR_RDP_4DEEP;
	396	addr = (addr & ~PLB0_ACR_WRP_MASK) \| PLB0_ACR_WRP_2DEEP;
	397	mtdcr(PLB0_ACR, addr);
c157d8e2 SR	398
c157d8e2 SR	399	/* Segment1 */
d1c3b275 SR	400	addr = (mfdcr(PLB1_ACR) & ~PLB1_ACR_PPM_MASK) \| PLB1_ACR_PPM_FAIR;
	401	addr = (addr & ~PLB1_ACR_HBU_MASK) \| PLB1_ACR_HBU_ENABLED;
	402	addr = (addr & ~PLB1_ACR_RDP_MASK) \| PLB1_ACR_RDP_4DEEP;
	403	addr = (addr & ~PLB1_ACR_WRP_MASK) \| PLB1_ACR_WRP_2DEEP;
	404	mtdcr(PLB1_ACR, addr);
c157d8e2 SR	405
	406	return 1;
	407	}
466fff1a	408	#endif /* defined(CONFIG_PCI) */
c157d8e2 SR	409
	410	/*************************************************************************
	411	* pci_target_init
	412	*
	413	* The bootstrap configuration provides default settings for the pci
	414	* inbound map (PIM). But the bootstrap config choices are limited and
	415	* may not be sufficient for a given board.
	416	*
	417	************************************************************************/
6d0f6bcf	418	#if defined(CONFIG_PCI) && defined(CONFIG_SYS_PCI_TARGET_INIT)
c157d8e2 SR	419	void pci_target_init(struct pci_controller *hose)
	420	{
	421	/*--------------------------------------------------------------------------+
	422	* Set up Direct MMIO registers
	423	--------------------------------------------------------------------------/
	424	/*--------------------------------------------------------------------------+
	425	\| PowerPC440 EP PCI Master configuration.
	426	\| Map one 1Gig range of PLB/processor addresses to PCI memory space.
	427	\| PLB address 0xA0000000-0xDFFFFFFF ==> PCI address 0xA0000000-0xDFFFFFFF
	428	\| Use byte reversed out routines to handle endianess.
	429	\| Make this region non-prefetchable.
	430	+--------------------------------------------------------------------------*/
ddc922ff NG	431	out32r(PCIL0_PMM0MA, 0x00000000); /* PMM0 Mask/Attribute - disabled b4 setting */
	432	out32r(PCIL0_PMM0LA, CONFIG_SYS_PCI_MEMBASE); /* PMM0 Local Address */
	433	out32r(PCIL0_PMM0PCILA, CONFIG_SYS_PCI_MEMBASE); /* PMM0 PCI Low Address */
	434	out32r(PCIL0_PMM0PCIHA, 0x00000000); /* PMM0 PCI High Address */
	435	out32r(PCIL0_PMM0MA, 0xE0000001); /* 512M + No prefetching, and enable region */
	436
	437	out32r(PCIL0_PMM1MA, 0x00000000); /* PMM0 Mask/Attribute - disabled b4 setting */
	438	out32r(PCIL0_PMM1LA, CONFIG_SYS_PCI_MEMBASE2); /* PMM0 Local Address */
	439	out32r(PCIL0_PMM1PCILA, CONFIG_SYS_PCI_MEMBASE2); /* PMM0 PCI Low Address */
	440	out32r(PCIL0_PMM1PCIHA, 0x00000000); /* PMM0 PCI High Address */
	441	out32r(PCIL0_PMM1MA, 0xE0000001); /* 512M + No prefetching, and enable region */
	442
	443	out32r(PCIL0_PTM1MS, 0x00000001); /* Memory Size/Attribute */
	444	out32r(PCIL0_PTM1LA, 0); /* Local Addr. Reg */
	445	out32r(PCIL0_PTM2MS, 0); /* Memory Size/Attribute */
	446	out32r(PCIL0_PTM2LA, 0); /* Local Addr. Reg */
c157d8e2 SR	447
	448	/*--------------------------------------------------------------------------+
	449	* Set up Configuration registers
	450	--------------------------------------------------------------------------/
	451
	452	/* Program the board's subsystem id/vendor id */
	453	pci_write_config_word(0, PCI_SUBSYSTEM_VENDOR_ID,
6d0f6bcf JCPV	454	CONFIG_SYS_PCI_SUBSYS_VENDORID);
6d0f6bcf JCPV	455	pci_write_config_word(0, PCI_SUBSYSTEM_ID, CONFIG_SYS_PCI_SUBSYS_ID);
c157d8e2 SR	456
	457	/* Configure command register as bus master */
	458	pci_write_config_word(0, PCI_COMMAND, PCI_COMMAND_MASTER);
	459
	460	/* 240nS PCI clock */
	461	pci_write_config_word(0, PCI_LATENCY_TIMER, 1);
	462
	463	/* No error reporting */
	464	pci_write_config_word(0, PCI_ERREN, 0);
	465
	466	pci_write_config_dword(0, PCI_BRDGOPT2, 0x00000101);
	467
	468	}
6d0f6bcf	469	#endif /* defined(CONFIG_PCI) && defined(CONFIG_SYS_PCI_TARGET_INIT) */
c157d8e2 SR	470
	471	/*************************************************************************
	472	* pci_master_init
	473	*
	474	************************************************************************/
6d0f6bcf	475	#if defined(CONFIG_PCI) && defined(CONFIG_SYS_PCI_MASTER_INIT)
c157d8e2 SR	476	void pci_master_init(struct pci_controller *hose)
	477	{
	478	unsigned short temp_short;
	479
	480	/*--------------------------------------------------------------------------+
	481	\| Write the PowerPC440 EP PCI Configuration regs.
	482	\| Enable PowerPC440 EP to be a master on the PCI bus (PMM).
	483	\| Enable PowerPC440 EP to act as a PCI memory target (PTM).
	484	+--------------------------------------------------------------------------*/
	485	pci_read_config_word(0, PCI_COMMAND, &temp_short);
	486	pci_write_config_word(0, PCI_COMMAND,
	487	temp_short \| PCI_COMMAND_MASTER \|
	488	PCI_COMMAND_MEMORY);
	489	}
6d0f6bcf	490	#endif /* defined(CONFIG_PCI) && defined(CONFIG_SYS_PCI_MASTER_INIT) */
c157d8e2	491
c157d8e2 SR	492	/*************************************************************************
	493	* hw_watchdog_reset
	494	*
	495	* This routine is called to reset (keep alive) the watchdog timer
	496	*
	497	************************************************************************/
	498	#if defined(CONFIG_HW_WATCHDOG)
	499	void hw_watchdog_reset(void)
	500	{
	501
	502	}
	503	#endif
f3443867 SR	504
	505	void board_reset(void)
	506	{
	507	/* give reset to BCSR */
6d0f6bcf	508	(unsigned char )(CONFIG_SYS_BCSR_BASE \| 0x06) = 0x09;
f3443867	509	}