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a350c6a6
MY
1config CREATE_ARCH_SYMLINK
2 bool
3
9a387128
MY
4config HAVE_ARCH_IOREMAP
5 bool
6
35b7ca76
MS
7config NEEDS_MANUAL_RELOC
8 bool
9
ab92b38a
TR
10config SYS_CACHE_SHIFT_4
11 bool
12
13config SYS_CACHE_SHIFT_5
14 bool
15
16config SYS_CACHE_SHIFT_6
17 bool
18
19config SYS_CACHE_SHIFT_7
20 bool
21
22config SYS_CACHELINE_SIZE
23 int
24 default 128 if SYS_CACHE_SHIFT_7
25 default 64 if SYS_CACHE_SHIFT_6
26 default 32 if SYS_CACHE_SHIFT_5
27 default 16 if SYS_CACHE_SHIFT_4
28 # Fall-back for MIPS
29 default 32 if MIPS
30
0b2fa98a
SG
31config LINKER_LIST_ALIGN
32 int
33 default 32 if SANDBOX
34 default 8 if ARM64 || X86
35 default 4
36 help
37 Force the each linker list to be aligned to this boundary. This
38 is required if ll_entry_get() is used, since otherwise the linker
39 may add padding into the table, thus breaking it.
40 See linker_lists.rst for full details.
41
51631259
MY
42choice
43 prompt "Architecture select"
44 default SANDBOX
45
46config ARC
47 bool "ARC architecture"
5ed063d1 48 select ARC_TIMER
3daa7c7b 49 select CLK
7b56432c 50 select DM
5ed063d1
MS
51 select HAVE_PRIVATE_LIBGCC
52 select SUPPORT_OF_CONTROL
ab92b38a 53 select SYS_CACHE_SHIFT_7
3daa7c7b 54 select TIMER
51631259
MY
55
56config ARM
57 bool "ARM architecture"
8f969651 58 select ARCH_SUPPORTS_LTO
a350c6a6 59 select CREATE_ARCH_SYMLINK
64b77ed2 60 select HAVE_PRIVATE_LIBGCC if !ARM64
783e6a72 61 select SUPPORT_OF_CONTROL
51631259 62
51631259
MY
63config M68K
64 bool "M68000 architecture"
6463fd8f 65 select HAVE_PRIVATE_LIBGCC
35b7ca76 66 select NEEDS_MANUAL_RELOC
405fc830
DW
67 select SYS_BOOT_GET_CMDLINE
68 select SYS_BOOT_GET_KBD
ab92b38a 69 select SYS_CACHE_SHIFT_4
abe0f879 70 select SUPPORT_OF_CONTROL
51631259
MY
71
72config MICROBLAZE
73 bool "MicroBlaze architecture"
35b7ca76 74 select NEEDS_MANUAL_RELOC
783e6a72 75 select SUPPORT_OF_CONTROL
1b330894 76 imply CMD_IRQ
51631259
MY
77
78config MIPS
79 bool "MIPS architecture"
9a387128 80 select HAVE_ARCH_IOREMAP
45ccec8f 81 select HAVE_PRIVATE_LIBGCC
0fc13a90 82 select SUPPORT_OF_CONTROL
51631259
MY
83
84config NDS32
85 bool "NDS32 architecture"
86132af7 86 select SUPPORT_OF_CONTROL
51631259
MY
87
88config NIOS2
89 bool "Nios II architecture"
bcae80e9 90 select CPU
5ed063d1
MS
91 select DM
92 select OF_CONTROL
93 select SUPPORT_OF_CONTROL
08a00cba 94 imply CMD_DM
51631259 95
51631259
MY
96config PPC
97 bool "PowerPC architecture"
45ccec8f 98 select HAVE_PRIVATE_LIBGCC
c1c61573 99 select SUPPORT_OF_CONTROL
405fc830
DW
100 select SYS_BOOT_GET_CMDLINE
101 select SYS_BOOT_GET_KBD
51631259 102
068feb9b 103config RISCV
117a433d 104 bool "RISC-V architecture"
7c8d210b 105 select CREATE_ARCH_SYMLINK
068feb9b 106 select SUPPORT_OF_CONTROL
bf6cc82c
BM
107 select OF_CONTROL
108 select DM
cd1f45c2
BM
109 imply DM_SERIAL
110 imply DM_ETH
111 imply DM_MMC
112 imply DM_SPI
113 imply DM_SPI_FLASH
114 imply BLK
115 imply CLK
116 imply MTD
117 imply TIMER
bf6cc82c 118 imply CMD_DM
8c59f202
LA
119 imply SPL_DM
120 imply SPL_OF_CONTROL
121 imply SPL_LIBCOMMON_SUPPORT
122 imply SPL_LIBGENERIC_SUPPORT
2a736066 123 imply SPL_SERIAL
8c59f202 124 imply SPL_TIMER
068feb9b 125
51631259
MY
126config SANDBOX
127 bool "Sandbox"
94bb891e 128 select ARCH_SUPPORTS_LTO
e5ec4815 129 select BOARD_LATE_INIT
efc06448 130 select BZIP2
b1ad4157 131 select CMD_POWEROFF
58d423b8 132 select DM
5ed063d1
MS
133 select DM_GPIO
134 select DM_I2C
558e1257 135 select DM_KEYBOARD
5ed063d1 136 select DM_MMC
58d423b8 137 select DM_SERIAL
58d423b8 138 select DM_SPI
5ed063d1 139 select DM_SPI_FLASH
efc06448 140 select GZIP_COMPRESSED
1811a928 141 select HAVE_BLOCK_DEVICE
d56b4b19 142 select LZO
1c0bc80a 143 select OF_BOARD_SETUP
bb413337 144 select PCI_ENDPOINT
5ed063d1
MS
145 select SPI
146 select SUPPORT_OF_CONTROL
b1ad4157 147 select SYSRESET_CMD_POWEROFF
ab92b38a 148 select SYS_CACHE_SHIFT_4
57c675d6 149 select IRQ
95300f20 150 select SUPPORT_EXTENSION_SCAN
0f1caa98 151 imply BITREVERSE
919e7a8f 152 select BLOBLIST
1b457e75 153 imply LTO
08a00cba 154 imply CMD_DM
6ca5ff3f 155 imply CMD_EXCEPTION
ded48cdc 156 imply CMD_GETTIME
551c3934 157 imply CMD_HASH
594e8d1c 158 imply CMD_IO
7d0f5c13 159 imply CMD_IOTRACE
ee7c0e71 160 imply CMD_LZMADEC
5ed063d1 161 imply CMD_SATA
a4298dda 162 imply CMD_SF
5ed063d1 163 imply CMD_SF_TEST
91d27a17
TR
164 imply CRC32_VERIFY
165 imply FAT_WRITE
31b8217e 166 imply FIRMWARE
221a949e 167 imply HASH_VERIFY
91d27a17 168 imply LZMA
fedb428c 169 imply SCSI
fe39e8e0 170 imply TEE
0a60a81b
JW
171 imply AVB_VERIFY
172 imply LIBAVB
173 imply CMD_AVB
7c591a84
IO
174 imply SCP03
175 imply CMD_SCP03
0a60a81b 176 imply UDP_FUNCTION_FASTBOOT
4f89d494
BM
177 imply VIRTIO_MMIO
178 imply VIRTIO_PCI
179 imply VIRTIO_SANDBOX
180 imply VIRTIO_BLK
181 imply VIRTIO_NET
2a049572 182 imply DM_SOUND
bb413337 183 imply PCI_SANDBOX_EP
c882163b 184 imply PCH
ec9594a5
AM
185 imply PHYLIB
186 imply DM_MDIO
c3d9f3f8 187 imply DM_MDIO_MUX
3b65ee34
SG
188 imply ACPI_PMC
189 imply ACPI_PMC_SANDBOX
190 imply CMD_PMC
4a4830cf 191 imply CMD_CLONE
f158ba15 192 imply SILENT_CONSOLE
51bb3384 193 imply BOOTARGS_SUBST
ff98da06
CM
194 imply PHY_FIXED
195 imply DM_DSA
95300f20 196 imply CMD_EXTENSION
51631259
MY
197
198config SH
199 bool "SuperH architecture"
45ccec8f 200 select HAVE_PRIVATE_LIBGCC
8c2c4635 201 select SUPPORT_OF_CONTROL
51631259 202
51631259
MY
203config X86
204 bool "x86 architecture"
98987902
SG
205 select SUPPORT_SPL
206 select SUPPORT_TPL
a350c6a6 207 select CREATE_ARCH_SYMLINK
58d423b8 208 select DM
3bf9a8e8 209 select HAVE_ARCH_IOMAP
5ed063d1
MS
210 select HAVE_PRIVATE_LIBGCC
211 select OF_CONTROL
4f0faacb 212 select PCI
5ed063d1 213 select SUPPORT_OF_CONTROL
ab92b38a 214 select SYS_CACHE_SHIFT_6
0ce9c576 215 select TIMER
5ed063d1 216 select USE_PRIVATE_LIBGCC
0ce9c576 217 select X86_TSC_TIMER
543d091e 218 select IRQ
bcd4e6f3 219 imply HAS_ROM if X86_RESET_VECTOR
24357dfd 220 imply BLK
08a00cba 221 imply CMD_DM
5ed063d1
MS
222 imply CMD_FPGA_LOADMK
223 imply CMD_GETTIME
224 imply CMD_IO
225 imply CMD_IRQ
226 imply CMD_PCI
a4298dda 227 imply CMD_SF
5ed063d1
MS
228 imply CMD_SF_TEST
229 imply CMD_ZBOOT
4f0faacb
BM
230 imply DM_ETH
231 imply DM_GPIO
232 imply DM_KEYBOARD
b7c6baef 233 imply DM_MMC
4f0faacb 234 imply DM_RTC
24357dfd 235 imply DM_SCSI
5ed063d1 236 imply DM_SERIAL
4f0faacb
BM
237 imply DM_SPI
238 imply DM_SPI_FLASH
239 imply DM_USB
240 imply DM_VIDEO
b37b7b20 241 imply SYSRESET
09259fce 242 imply SPL_SYSRESET
b37b7b20 243 imply SYSRESET_X86
f58ad98a
CP
244 imply USB_ETHER_ASIX
245 imply USB_ETHER_SMSC95XX
5ed063d1 246 imply USB_HOST_ETHER
c882163b 247 imply PCH
31d5261d 248 imply RTC_MC146818
d40d2c57 249 imply ACPIGEN if !QEMU
839d66cd
SG
250 imply SYSINFO if GENERATE_SMBIOS_TABLE
251 imply SYSINFO_SMBIOS if GENERATE_SMBIOS_TABLE
51631259 252
98987902
SG
253 # Thing to enable for when SPL/TPL are enabled: SPL
254 imply SPL_DM
255 imply SPL_OF_LIBFDT
9ca00684 256 imply SPL_DRIVERS_MISC
83061dbd 257 imply SPL_GPIO
e556d3d6 258 imply SPL_PINCTRL
98987902
SG
259 imply SPL_LIBCOMMON_SUPPORT
260 imply SPL_LIBGENERIC_SUPPORT
2a736066 261 imply SPL_SERIAL
98987902 262 imply SPL_SPI_FLASH_SUPPORT
ea2ca7e1 263 imply SPL_SPI
98987902
SG
264 imply SPL_OF_CONTROL
265 imply SPL_TIMER
266 imply SPL_REGMAP
267 imply SPL_SYSCON
268 # TPL
269 imply TPL_DM
9ca00684 270 imply TPL_DRIVERS_MISC
83061dbd 271 imply TPL_GPIO
e556d3d6 272 imply TPL_PINCTRL
98987902
SG
273 imply TPL_LIBCOMMON_SUPPORT
274 imply TPL_LIBGENERIC_SUPPORT
2a736066 275 imply TPL_SERIAL
98987902
SG
276 imply TPL_OF_CONTROL
277 imply TPL_TIMER
278 imply TPL_REGMAP
279 imply TPL_SYSCON
280
c978b524
CZ
281config XTENSA
282 bool "Xtensa architecture"
283 select CREATE_ARCH_SYMLINK
284 select SUPPORT_OF_CONTROL
285
51631259
MY
286endchoice
287
3174e4e8
MY
288config SYS_ARCH
289 string
290 help
291 This option should contain the architecture name to build the
292 appropriate arch/<CONFIG_SYS_ARCH> directory.
293 All the architectures should specify this option correctly.
294
295config SYS_CPU
296 string
297 help
298 This option should contain the CPU name to build the correct
299 arch/<CONFIG_SYS_ARCH>/cpu/<CONFIG_SYS_CPU> directory.
300
301 This is optional. For those targets without the CPU directory,
302 leave this option empty.
303
304config SYS_SOC
305 string
306 help
307 This option should contain the SoC name to build the directory
308 arch/<CONFIG_SYS_ARCH>/cpu/<CONFIG_SYS_CPU>/<CONFIG_SYS_SOC>.
309
310 This is optional. For those targets without the SoC directory,
311 leave this option empty.
312
313config SYS_VENDOR
314 string
315 help
316 This option should contain the vendor name of the target board.
317 If it is set and
318 board/<CONFIG_SYS_VENDOR>/common/Makefile exists, the vendor common
319 directory is compiled.
320 If CONFIG_SYS_BOARD is also set, the sources under
321 board/<CONFIG_SYS_VENDOR>/<CONFIG_SYS_BOARD> directory are compiled.
322
323 This is optional. For those targets without the vendor directory,
324 leave this option empty.
325
326config SYS_BOARD
327 string
328 help
329 This option should contain the name of the target board.
330 If it is set, either board/<CONFIG_SYS_VENDOR>/<CONFIG_SYS_BOARD>
331 or board/<CONFIG_SYS_BOARD> directory is compiled depending on
332 whether CONFIG_SYS_VENDOR is set or not.
333
334 This is optional. For those targets without the board directory,
335 leave this option empty.
336
337config SYS_CONFIG_NAME
338 string
339 help
340 This option should contain the base name of board header file.
341 The header file include/configs/<CONFIG_SYS_CONFIG_NAME>.h
342 should be included from include/config.h.
343
add49671
VR
344config SYS_DISABLE_DCACHE_OPS
345 bool
346 help
347 This option disables dcache flush and dcache invalidation
348 operations. For example, on coherent systems where cache
349 operatios are not required, enable this option to avoid them.
350 Note that, its up to the individual architectures to implement
351 this functionality.
352
a2ac2b96
TR
353config SKIP_LOWLEVEL_INIT
354 bool "Skip the calls to certain low level initialization functions"
355 depends on ARM || NDS32 || MIPS || RISCV
356 help
357 If enabled, then certain low level initializations (like setting up
358 the memory controller) are omitted and/or U-Boot does not relocate
359 itself into RAM.
360 Normally this variable MUST NOT be defined. The only exception is
361 when U-Boot is loaded (to RAM) by some other boot loader or by a
362 debugger which performs these initializations itself.
363
364config SPL_SKIP_LOWLEVEL_INIT
365 bool "Skip the calls to certain low level initialization functions"
366 depends on SPL && (ARM || NDS32 || MIPS || RISCV)
367 help
368 If enabled, then certain low level initializations (like setting up
369 the memory controller) are omitted and/or U-Boot does not relocate
370 itself into RAM.
371 Normally this variable MUST NOT be defined. The only exception is
372 when U-Boot is loaded (to RAM) by some other boot loader or by a
373 debugger which performs these initializations itself.
374
375config TPL_SKIP_LOWLEVEL_INIT
376 bool "Skip the calls to certain low level initialization functions"
377 depends on SPL && ARM
378 help
379 If enabled, then certain low level initializations (like setting up
380 the memory controller) are omitted and/or U-Boot does not relocate
381 itself into RAM.
382 Normally this variable MUST NOT be defined. The only exception is
383 when U-Boot is loaded (to RAM) by some other boot loader or by a
384 debugger which performs these initializations itself.
385
386config SKIP_LOWLEVEL_INIT_ONLY
387 bool "Skip the call to lowlevel_init during early boot ONLY"
388 depends on ARM
389 help
390 This allows just the call to lowlevel_init() to be skipped. The
391 normal CP15 init (such as enabling the instruction cache) is still
392 performed.
393
394config SPL_SKIP_LOWLEVEL_INIT_ONLY
395 bool "Skip the call to lowlevel_init during early boot ONLY"
396 depends on SPL && ARM
397 help
398 This allows just the call to lowlevel_init() to be skipped. The
399 normal CP15 init (such as enabling the instruction cache) is still
400 performed.
401
402config TPL_SKIP_LOWLEVEL_INIT_ONLY
403 bool "Skip the call to lowlevel_init during early boot ONLY"
404 depends on TPL && ARM
405 help
406 This allows just the call to lowlevel_init() to be skipped. The
407 normal CP15 init (such as enabling the instruction cache) is still
408 performed.
409
51631259
MY
410source "arch/arc/Kconfig"
411source "arch/arm/Kconfig"
51631259
MY
412source "arch/m68k/Kconfig"
413source "arch/microblaze/Kconfig"
414source "arch/mips/Kconfig"
415source "arch/nds32/Kconfig"
416source "arch/nios2/Kconfig"
51631259
MY
417source "arch/powerpc/Kconfig"
418source "arch/sandbox/Kconfig"
419source "arch/sh/Kconfig"
51631259 420source "arch/x86/Kconfig"
c978b524 421source "arch/xtensa/Kconfig"
068feb9b 422source "arch/riscv/Kconfig"
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