[J-u-boot.git] / include / configs / csb226.h

/*
 * (C) Copyright 2000, 2001, 2002
 * Robert Schwebel, Pengutronix, [email protected].
 *
 * Configuration for the Cogent CSB226 board. For details see
 * http://www.cogcomp.com/csb_csb226.htm
 *
 * See file CREDITS for list of people who contributed to this
 * project.
 *
 * This program is free software; you can redistribute it and/or
 * modify it under the terms of the GNU General Public License as
 * published by the Free Software Foundation; either version 2 of
 * the License, or (at your option) any later version.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 * GNU General Public License for more details.
 *
 * You should have received a copy of the GNU General Public License
 * along with this program; if not, write to the Free Software
 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
 * MA 02111-1307 USA
 */

/*
 * include/configs/csb226.h - configuration options, board specific
 */

#ifndef __CONFIG_H
#define __CONFIG_H

#define DEBUG 1

/*
 * If we are developing, we might want to start U-Boot from ram
 * so we MUST NOT initialize critical regs like mem-timing ...
 */
#define CONFIG_INIT_CRITICAL		/* undef for developing */

/*
 * High Level Configuration Options
 * (easy to change)
 */
#define CONFIG_PXA250 		1	/* This is an PXA250 CPU            */
#define CONFIG_CSB226		1	/* on a CSB226 board                */

#undef CONFIG_USE_IRQ			/* we don't need IRQ/FIQ stuff      */
					/* for timer/console/ethernet       */
/*
 * Hardware drivers
 */

/*
 * select serial console configuration
 */
#define CONFIG_FFUART		1	/* we use FFUART on CSB226          */

/* allow to overwrite serial and ethaddr */
#define CONFIG_ENV_OVERWRITE

#define CONFIG_BAUDRATE		19200
#undef  CONFIG_MISC_INIT_R		/* not used yet                     */

#define CONFIG_COMMANDS (CFG_CMD_BDI|CFG_CMD_LOADB|CFG_CMD_IMI|CFG_CMD_FLASH|CFG_CMD_MEMORY|CFG_CMD_NET|CFG_CMD_ENV|CFG_CMD_RUN|CFG_CMD_ASKENV|CFG_CMD_ECHO|CFG_CMD_DHCP|CFG_CMD_CACHE)

/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
#include <cmd_confdefs.h>

#define CONFIG_BOOTDELAY	3
#define CONFIG_BOOTARGS		"console=ttyS0,19200 ip=192.168.1.10,192.168.1.5,,255,255,255,0,csb root=/dev/nfs, ether=0,0x08000000,eth0"
#define CONFIG_ETHADDR		FF:FF:FF:FF:FF:FF
#define CONFIG_NETMASK		255.255.255.0
#define CONFIG_IPADDR		192.168.1.56
#define CONFIG_SERVERIP		192.168.1.5
#define CONFIG_BOOTCOMMAND	"bootm 0x40000"
#define CONFIG_SHOW_BOOT_PROGRESS

#define CONFIG_CMDLINE_TAG	1

#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
#define CONFIG_KGDB_BAUDRATE	19200		/* speed to run kgdb serial port */
#define CONFIG_KGDB_SER_INDEX	2		/* which serial port to use */
#endif

/*
 * Miscellaneous configurable options
 */

/*
 * Size of malloc() pool; this lives below the uppermost 128 KiB which are
 * used for the RAM copy of the uboot code
 *
 */
#define CFG_MALLOC_LEN		(128*1024)

#define CFG_LONGHELP				/* undef to save memory         */
#define CFG_PROMPT		"uboot> "	/* Monitor Command Prompt       */
#define CFG_CBSIZE		128		/* Console I/O Buffer Size      */
#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
#define CFG_MAXARGS		16		/* max number of command args   */
#define CFG_BARGSIZE		CFG_CBSIZE	/* Boot Argument Buffer Size    */

#define CFG_MEMTEST_START	0xa0400000      /* memtest works on     */
#define CFG_MEMTEST_END         0xa0800000      /* 4 ... 8 MB in DRAM   */

#undef  CFG_CLKS_IN_HZ          /* everything, incl board info, in Hz */

#define CFG_LOAD_ADDR           0xa3000000	/* default load address */
						/* RS: where is this documented? */
						/* RS: is this where U-Boot is  */
						/* RS: relocated to in RAM?      */

#define CFG_HZ                  3686400         /* incrementer freq: 3.6864 MHz */
						/* RS: the oscillator is actually 3680130?? */
#define CFG_CPUSPEED            0x141           /* set core clock to 200/200/100 MHz */
						/* 0101000001 */
						/*      ^^^^^ Memory Speed 99.53 MHz         */
						/*    ^^      Run Mode Speed = 2x Mem Speed  */
						/* ^^         Turbo Mode Sp. = 1x Run M. Sp. */

#define CFG_MONITOR_LEN		0x20000		/* 128 KiB */

                                                /* valid baudrates */
#define CFG_BAUDRATE_TABLE      { 9600, 19200, 38400, 57600, 115200 }

/*
 * Network chip
 */
#define CONFIG_DRIVER_CS8900	1
#define CS8900_BUS32		1
#define CS8900_BASE		0x08000000

/*
 * Stack sizes
 *
 * The stack sizes are set up in start.S using the settings below
 */
#define CONFIG_STACKSIZE        (128*1024)      /* regular stack */
#ifdef  CONFIG_USE_IRQ
#define CONFIG_STACKSIZE_IRQ    (4*1024)        /* IRQ stack */
#define CONFIG_STACKSIZE_FIQ    (4*1024)        /* FIQ stack */
#endif

/*
 * Physical Memory Map
 */
#define CONFIG_NR_DRAM_BANKS	1		/* we have 1 bank of DRAM   */
#define PHYS_SDRAM_1		0xa0000000	/* SDRAM Bank #1            */
#define PHYS_SDRAM_1_SIZE	0x02000000	/* 32 MB                    */

#define PHYS_FLASH_1		0x00000000	/* Flash Bank #1            */
#define PHYS_FLASH_SIZE		0x02000000	/* 32 MB                    */

#define CFG_DRAM_BASE		0xa0000000	/* RAM starts here          */
#define CFG_DRAM_SIZE		0x02000000

#define CFG_FLASH_BASE          PHYS_FLASH_1

# if 0
/* FIXME: switch to _documented_ registers */
/*
 * GPIO settings
 *
 * GP15 == nCS1      is 1
 * GP24 == SFRM      is 1
 * GP25 == TXD       is 1
 * GP33 == nCS5      is 1
 * GP39 == FFTXD     is 1
 * GP41 == RTS       is 1
 * GP47 == TXD       is 1
 * GP49 == nPWE      is 1
 * GP62 == LED_B     is 1
 * GP63 == TDM_OE    is 1
 * GP78 == nCS2      is 1
 * GP79 == nCS3      is 1
 * GP80 == nCS4      is 1
 */
#define CFG_GPSR0_VAL       0x03008000
#define CFG_GPSR1_VAL       0xC0028282
#define CFG_GPSR2_VAL       0x0001C000

/* GP02 == DON_RST   is 0
 * GP23 == SCLK      is 0
 * GP45 == USB_ACT   is 0
 * GP60 == PLLEN     is 0
 * GP61 == LED_A     is 0
 * GP73 == SWUPD_LED is 0
 */
#define CFG_GPCR0_VAL       0x00800004
#define CFG_GPCR1_VAL       0x30002000
#define CFG_GPCR2_VAL       0x00000100

/* GP00 == DON_READY is input
 * GP01 == DON_OK    is input
 * GP02 == DON_RST   is output
 * GP03 == RESET_IND is input
 * GP07 == RES11     is input
 * GP09 == RES12     is input
 * GP11 == SWUPDATE  is input
 * GP14 == nPOWEROK  is input
 * GP15 == nCS1      is output
 * GP17 == RES22     is input
 * GP18 == RDY       is input
 * GP23 == SCLK      is output
 * GP24 == SFRM      is output
 * GP25 == TXD       is output
 * GP26 == RXD       is input
 * GP32 == RES21     is input
 * GP33 == nCS5      is output
 * GP34 == FFRXD     is input
 * GP35 == CTS       is input
 * GP39 == FFTXD     is output
 * GP41 == RTS       is output
 * GP42 == USB_OK    is input
 * GP45 == USB_ACT   is output
 * GP46 == RXD       is input
 * GP47 == TXD       is output
 * GP49 == nPWE      is output
 * GP58 == nCPUBUSINT is input
 * GP59 == LANINT    is input
 * GP60 == PLLEN     is output
 * GP61 == LED_A     is output
 * GP62 == LED_B     is output
 * GP63 == TDM_OE    is output
 * GP64 == nDSPINT   is input
 * GP65 == STRAP0    is input
 * GP67 == STRAP1    is input
 * GP69 == STRAP2    is input
 * GP70 == STRAP3    is input
 * GP71 == STRAP4    is input
 * GP73 == SWUPD_LED is output
 * GP78 == nCS2      is output
 * GP79 == nCS3      is output
 * GP80 == nCS4      is output
 */
#define CFG_GPDR0_VAL       0x03808004
#define CFG_GPDR1_VAL       0xF002A282
#define CFG_GPDR2_VAL       0x0001C200

/* GP15 == nCS1  is AF10
 * GP18 == RDY   is AF01
 * GP23 == SCLK  is AF10
 * GP24 == SFRM  is AF10
 * GP25 == TXD   is AF10
 * GP26 == RXD   is AF01
 * GP33 == nCS5  is AF10
 * GP34 == FFRXD is AF01
 * GP35 == CTS   is AF01
 * GP39 == FFTXD is AF10
 * GP41 == RTS   is AF10
 * GP46 == RXD   is AF10
 * GP47 == TXD   is AF01
 * GP49 == nPWE  is AF10
 * GP78 == nCS2  is AF10
 * GP79 == nCS3  is AF10
 * GP80 == nCS4  is AF10
 */
#define CFG_GAFR0_L_VAL     0x80000000
#define CFG_GAFR0_U_VAL     0x001A8010
#define CFG_GAFR1_L_VAL     0x60088058
#define CFG_GAFR1_U_VAL     0x00000008
#define CFG_GAFR2_L_VAL     0xA0000000
#define CFG_GAFR2_U_VAL     0x00000002


/* FIXME: set GPIO_RER/FER */

/* RDH = 1
 * PH  = 1
 * VFS = 1
 * BFS = 1
 * SSS = 1
 */
#define CFG_PSSR_VAL		0x37

/*
 * Memory settings
 *
 * This is the configuration for nCS0/1 -> flash banks
 * configuration for nCS1:
 * [31]    0    - Slower Device
 * [30:28] 010  - CS deselect to CS time: 2*(2*MemClk) = 40 ns
 * [27:24] 0101 - Address to data valid in bursts: (5+1)*MemClk = 60 ns
 * [23:20] 1011 - " for first access: (11+2)*MemClk = 130 ns
 * [19]    1    - 16 Bit bus width
 * [18:16] 000  - nonburst RAM or FLASH
 * configuration for nCS0:
 * [15]    0    - Slower Device
 * [14:12] 010  - CS deselect to CS time: 2*(2*MemClk) = 40 ns
 * [11:08] 0101 - Address to data valid in bursts: (5+1)*MemClk = 60 ns
 * [07:04] 1011 - " for first access: (11+2)*MemClk = 130 ns
 * [03]    1    - 16 Bit bus width
 * [02:00] 000  - nonburst RAM or FLASH
 */
#define CFG_MSC0_VAL		0x25b825b8 /* flash banks                   */

/* This is the configuration for nCS2/3 -> TDM-Switch, DSP
 * configuration for nCS3: DSP
 * [31]    0    - Slower Device
 * [30:28] 001  - RRR3: CS deselect to CS time: 1*(2*MemClk) = 20 ns
 * [27:24] 0010 - RDN3: Address to data valid in bursts: (2+1)*MemClk = 30 ns
 * [23:20] 0011 - RDF3: Address for first access: (3+1)*MemClk = 40 ns
 * [19]    1    - 16 Bit bus width
 * [18:16] 100  - variable latency I/O
 * configuration for nCS2: TDM-Switch
 * [15]    0    - Slower Device
 * [14:12] 101  - RRR2: CS deselect to CS time: 5*(2*MemClk) = 100 ns
 * [11:08] 1001 - RDN2: Address to data valid in bursts: (9+1)*MemClk = 100 ns
 * [07:04] 0011 - RDF2: Address for first access: (3+1)*MemClk = 40 ns
 * [03]    1    - 16 Bit bus width
 * [02:00] 100  - variable latency I/O
 */
#define CFG_MSC1_VAL		0x123C593C /* TDM switch, DSP               */

/* This is the configuration for nCS4/5 -> ExtBus, LAN Controller
 *
 * configuration for nCS5: LAN Controller
 * [31]    0    - Slower Device
 * [30:28] 001  - RRR5: CS deselect to CS time: 1*(2*MemClk) = 20 ns
 * [27:24] 0010 - RDN5: Address to data valid in bursts: (2+1)*MemClk = 30 ns
 * [23:20] 0011 - RDF5: Address for first access: (3+1)*MemClk = 40 ns
 * [19]    1    - 16 Bit bus width
 * [18:16] 100  - variable latency I/O
 * configuration for nCS4: ExtBus
 * [15]    0    - Slower Device
 * [14:12] 110  - RRR4: CS deselect to CS time: 6*(2*MemClk) = 120 ns
 * [11:08] 1100 - RDN4: Address to data valid in bursts: (12+1)*MemClk = 130 ns
 * [07:04] 1101 - RDF4: Address for first access: 13->(15+1)*MemClk = 160 ns
 * [03]    1    - 16 Bit bus width
 * [02:00] 100  - variable latency I/O
 */
#define CFG_MSC2_VAL		0x123C6CDC /* extra bus, LAN controller     */

/* MDCNFG: SDRAM Configuration Register
 *
 * [31:29]   000 - reserved
 * [28]      0	 - no SA1111 compatiblity mode
 * [27]      0   - latch return data with return clock
 * [26]      0   - alternate addressing for pair 2/3
 * [25:24]   00  - timings
 * [23]      0   - internal banks in lower partition 2/3 (not used)
 * [22:21]   00  - row address bits for partition 2/3 (not used)
 * [20:19]   00  - column address bits for partition 2/3 (not used)
 * [18]      0   - SDRAM partition 2/3 width is 32 bit
 * [17]      0   - SDRAM partition 3 disabled
 * [16]      0   - SDRAM partition 2 disabled
 * [15:13]   000 - reserved
 * [12]      1	 - SA1111 compatiblity mode
 * [11]      1   - latch return data with return clock
 * [10]      0   - no alternate addressing for pair 0/1
 * [09:08]   01  - tRP=2*MemClk CL=2 tRCD=2*MemClk tRAS=5*MemClk tRC=8*MemClk
 * [7]       1   - 4 internal banks in lower partition pair
 * [06:05]   10  - 13 row address bits for partition 0/1
 * [04:03]   01  - 9 column address bits for partition 0/1
 * [02]      0   - SDRAM partition 0/1 width is 32 bit
 * [01]      0   - disable SDRAM partition 1
 * [00]      1   - enable  SDRAM partition 0
 */
/* use the configuration above but disable partition 0 */
#define CFG_MDCNFG_VAL		0x000019c8

/* MDREFR: SDRAM Refresh Control Register
 *
 * [32:26] 0     - reserved
 * [25]    0     - K2FREE: not free running
 * [24]    0     - K1FREE: not free running
 * [23]    1     - K0FREE: not free running
 * [22]    0     - SLFRSH: self refresh disabled
 * [21]    0     - reserved
 * [20]    0     - APD: no auto power down
 * [19]    0     - K2DB2: SDCLK2 is MemClk
 * [18]    0     - K2RUN: disable SDCLK2
 * [17]    0     - K1DB2: SDCLK1 is MemClk
 * [16]    1     - K1RUN: enable SDCLK1
 * [15]    1     - E1PIN: SDRAM clock enable
 * [14]    1     - K0DB2: SDCLK0 is MemClk
 * [13]    0     - K0RUN: disable SDCLK0
 * [12]    1     - E0PIN: disable SDCKE0
 * [11:00] 000000011000 - (64ms/8192)*MemClkFreq/32 = 24
 */
#define CFG_MDREFR_VAL		0x0081D018

/* MDMRS: Mode Register Set Configuration Register
 *
 * [31]      0       - reserved
 * [30:23]   00000000- MDMRS2: SDRAM2/3 MRS Value. (not used)
 * [22:20]   000     - MDCL2:  SDRAM2/3 Cas Latency.  (not used)
 * [19]      0       - MDADD2: SDRAM2/3 burst Type. Fixed to sequential.  (not used)
 * [18:16]   010     - MDBL2:  SDRAM2/3 burst Length. Fixed to 4.  (not used)
 * [15]      0       - reserved
 * [14:07]   00000000- MDMRS0: SDRAM0/1 MRS Value.
 * [06:04]   010     - MDCL0:  SDRAM0/1 Cas Latency.
 * [03]      0       - MDADD0: SDRAM0/1 burst Type. Fixed to sequential.
 * [02:00]   010     - MDBL0:  SDRAM0/1 burst Length. Fixed to 4.
 */
#define CFG_MDMRS_VAL		0x00020022

/*
 * PCMCIA and CF Interfaces
 */
#define CFG_MECR_VAL		0x00000000
#define CFG_MCMEM0_VAL		0x00000000
#define CFG_MCMEM1_VAL		0x00000000
#define CFG_MCATT0_VAL		0x00000000
#define CFG_MCATT1_VAL		0x00000000
#define CFG_MCIO0_VAL		0x00000000
#define CFG_MCIO1_VAL		0x00000000
#endif

/*
 * GPIO settings
 */
#define CFG_GPSR0_VAL		0xFFFFFFFF
#define CFG_GPSR1_VAL		0xFFFFFFFF
#define CFG_GPSR2_VAL		0xFFFFFFFF
#define CFG_GPCR0_VAL		0x08022080
#define CFG_GPCR1_VAL		0x00000000
#define CFG_GPCR2_VAL		0x00000000
#define CFG_GPDR0_VAL		0xCD82A878
#define CFG_GPDR1_VAL		0xFCFFAB80
#define CFG_GPDR2_VAL		0x0001FFFF
#define CFG_GAFR0_L_VAL		0x80000000
#define CFG_GAFR0_U_VAL		0xA5254010
#define CFG_GAFR1_L_VAL		0x599A9550
#define CFG_GAFR1_U_VAL		0xAAA5AAAA
#define CFG_GAFR2_L_VAL		0xAAAAAAAA
#define CFG_GAFR2_U_VAL		0x00000002

/* FIXME: set GPIO_RER/FER */

#define CFG_PSSR_VAL        0x20

/*
 * Memory settings
 */

#define CFG_MSC0_VAL            0x2ef15af0
#define CFG_MSC1_VAL            0x00003ff4
#define CFG_MSC2_VAL            0x7ff07ff0
#define CFG_MDCNFG_VAL          0x09a909a9
#define CFG_MDREFR_VAL          0x038ff030
#define CFG_MDMRS_VAL           0x00220022

/*
 * PCMCIA and CF Interfaces
 */
#define CFG_MECR_VAL        0x00000000
#define CFG_MCMEM0_VAL      0x00000000
#define CFG_MCMEM1_VAL      0x00000000
#define CFG_MCATT0_VAL      0x00000000
#define CFG_MCATT1_VAL      0x00000000
#define CFG_MCIO0_VAL       0x00000000
#define CFG_MCIO1_VAL       0x00000000

#define CSB226_USER_LED0	0x00000008
#define CSB226_USER_LED1	0x00000010
#define CSB226_USER_LED2	0x00000020


/*
 * FLASH and environment organization
 */
#define CFG_MAX_FLASH_BANKS     1	/* max number of memory banks       */
#define CFG_MAX_FLASH_SECT	128	/* max number of sect. on one chip  */

/* timeout values are in ticks */
#define CFG_FLASH_ERASE_TOUT    (2*CFG_HZ) /* Timeout for Flash Erase       */
#define CFG_FLASH_WRITE_TOUT    (2*CFG_HZ) /* Timeout for Flash Write       */

#define	CFG_ENV_IS_IN_FLASH	1
#define CFG_ENV_ADDR            (PHYS_FLASH_1 + 0x1C000)
					/* Addr of Environment Sector       */
#define CFG_ENV_SIZE            0x4000  /* Total Size of Environment Sector */

#endif  /* __CONFIG_H */
Commit	Line	Data
fe8c2806 WD	1	/*
	2	* (C) Copyright 2000, 2001, 2002
	3	* Robert Schwebel, Pengutronix, [email protected].
	4	*
	5	* Configuration for the Cogent CSB226 board. For details see
	6	* http://www.cogcomp.com/csb_csb226.htm
	7	*
	8	* See file CREDITS for list of people who contributed to this
	9	* project.
	10	*
	11	* This program is free software; you can redistribute it and/or
	12	* modify it under the terms of the GNU General Public License as
	13	* published by the Free Software Foundation; either version 2 of
	14	* the License, or (at your option) any later version.
	15	*
	16	* This program is distributed in the hope that it will be useful,
	17	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	18	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	19	* GNU General Public License for more details.
	20	*
	21	* You should have received a copy of the GNU General Public License
	22	* along with this program; if not, write to the Free Software
	23	* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
	24	* MA 02111-1307 USA
	25	*/
	26
	27	/*
	28	* include/configs/csb226.h - configuration options, board specific
	29	*/
	30
	31	#ifndef __CONFIG_H
	32	#define __CONFIG_H
	33
699b13a6 WD	34	#define DEBUG 1
699b13a6 WD	35
fe8c2806 WD	36	/*
	37	* If we are developing, we might want to start U-Boot from ram
	38	* so we MUST NOT initialize critical regs like mem-timing ...
	39	*/
	40	#define CONFIG_INIT_CRITICAL /* undef for developing */
	41
	42	/*
	43	* High Level Configuration Options
	44	* (easy to change)
	45	*/
	46	#define CONFIG_PXA250 1 /* This is an PXA250 CPU */
	47	#define CONFIG_CSB226 1 /* on a CSB226 board */
	48
	49	#undef CONFIG_USE_IRQ /* we don't need IRQ/FIQ stuff */
	50	/* for timer/console/ethernet */
	51	/*
	52	* Hardware drivers
	53	*/
	54
	55	/*
	56	* select serial console configuration
	57	*/
47cd00fa	58	#define CONFIG_FFUART 1 /* we use FFUART on CSB226 */
fe8c2806 WD	59
	60	/* allow to overwrite serial and ethaddr */
	61	#define CONFIG_ENV_OVERWRITE
	62
	63	#define CONFIG_BAUDRATE 19200
47cd00fa	64	#undef CONFIG_MISC_INIT_R /* not used yet */
fe8c2806	65
993cad93	66	#define CONFIG_COMMANDS (CFG_CMD_BDI\|CFG_CMD_LOADB\|CFG_CMD_IMI\|CFG_CMD_FLASH\|CFG_CMD_MEMORY\|CFG_CMD_NET\|CFG_CMD_ENV\|CFG_CMD_RUN\|CFG_CMD_ASKENV\|CFG_CMD_ECHO\|CFG_CMD_DHCP\|CFG_CMD_CACHE)
fe8c2806 WD	67
	68	/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
	69	#include <cmd_confdefs.h>
	70
699b13a6	71	#define CONFIG_BOOTDELAY 3
993cad93	72	#define CONFIG_BOOTARGS "console=ttyS0,19200 ip=192.168.1.10,192.168.1.5,,255,255,255,0,csb root=/dev/nfs, ether=0,0x08000000,eth0"
fe8c2806 WD	73	#define CONFIG_ETHADDR FF:FF:FF:FF:FF:FF
	74	#define CONFIG_NETMASK 255.255.255.0
	75	#define CONFIG_IPADDR 192.168.1.56
993cad93	76	#define CONFIG_SERVERIP 192.168.1.5
699b13a6	77	#define CONFIG_BOOTCOMMAND "bootm 0x40000"
384ae025	78	#define CONFIG_SHOW_BOOT_PROGRESS
fe8c2806	79
47cd00fa WD	80	#define CONFIG_CMDLINE_TAG 1
47cd00fa WD	81
fe8c2806	82	#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
47cd00fa	83	#define CONFIG_KGDB_BAUDRATE 19200 /* speed to run kgdb serial port */
fe8c2806 WD	84	#define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */
	85	#endif
	86
	87	/*
	88	* Miscellaneous configurable options
	89	*/
	90
	91	/*
	92	* Size of malloc() pool; this lives below the uppermost 128 KiB which are
	93	* used for the RAM copy of the uboot code
	94	*
	95	*/
47cd00fa	96	#define CFG_MALLOC_LEN (128*1024)
fe8c2806 WD	97
fe8c2806 WD	98	#define CFG_LONGHELP /* undef to save memory */
699b13a6 WD	99	#define CFG_PROMPT "uboot> " /* Monitor Command Prompt */
699b13a6 WD	100	#define CFG_CBSIZE 128 /* Console I/O Buffer Size */
fe8c2806 WD	101	#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
	102	#define CFG_MAXARGS 16 /* max number of command args */
	103	#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */
	104
	105	#define CFG_MEMTEST_START 0xa0400000 /* memtest works on */
	106	#define CFG_MEMTEST_END 0xa0800000 /* 4 ... 8 MB in DRAM */
	107
	108	#undef CFG_CLKS_IN_HZ /* everything, incl board info, in Hz */
	109
47cd00fa	110	#define CFG_LOAD_ADDR 0xa3000000 /* default load address */
fe8c2806 WD	111	/* RS: where is this documented? */
	112	/* RS: is this where U-Boot is */
	113	/* RS: relocated to in RAM? */
	114
	115	#define CFG_HZ 3686400 /* incrementer freq: 3.6864 MHz */
	116	/* RS: the oscillator is actually 3680130?? */
	117	#define CFG_CPUSPEED 0x141 /* set core clock to 200/200/100 MHz */
	118	/* 0101000001 */
	119	/* ^^^^^ Memory Speed 99.53 MHz */
	120	/* ^^ Run Mode Speed = 2x Mem Speed */
	121	/* ^^ Turbo Mode Sp. = 1x Run M. Sp. */
	122
	123	#define CFG_MONITOR_LEN 0x20000 /* 128 KiB */
	124
	125	/* valid baudrates */
	126	#define CFG_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 }
	127
993cad93 WD	128	/*
	129	* Network chip
	130	*/
	131	#define CONFIG_DRIVER_CS8900 1
	132	#define CS8900_BUS32 1
	133	#define CS8900_BASE 0x08000000
	134
fe8c2806 WD	135	/*
	136	* Stack sizes
	137	*
	138	* The stack sizes are set up in start.S using the settings below
	139	*/
	140	#define CONFIG_STACKSIZE (1281024) / regular stack */
	141	#ifdef CONFIG_USE_IRQ
	142	#define CONFIG_STACKSIZE_IRQ (41024) / IRQ stack */
	143	#define CONFIG_STACKSIZE_FIQ (41024) / FIQ stack */
	144	#endif
	145
	146	/*
	147	* Physical Memory Map
	148	*/
	149	#define CONFIG_NR_DRAM_BANKS 1 /* we have 1 bank of DRAM */
	150	#define PHYS_SDRAM_1 0xa0000000 /* SDRAM Bank #1 */
	151	#define PHYS_SDRAM_1_SIZE 0x02000000 /* 32 MB */
	152
	153	#define PHYS_FLASH_1 0x00000000 /* Flash Bank #1 */
	154	#define PHYS_FLASH_SIZE 0x02000000 /* 32 MB */
	155
	156	#define CFG_DRAM_BASE 0xa0000000 /* RAM starts here */
	157	#define CFG_DRAM_SIZE 0x02000000
	158
	159	#define CFG_FLASH_BASE PHYS_FLASH_1
	160
993cad93 WD	161	# if 0
993cad93 WD	162	/* FIXME: switch to _documented_ registers */
fe8c2806 WD	163	/*
fe8c2806 WD	164	* GPIO settings
993cad93 WD	165	*
	166	* GP15 == nCS1 is 1
	167	* GP24 == SFRM is 1
	168	* GP25 == TXD is 1
	169	* GP33 == nCS5 is 1
	170	* GP39 == FFTXD is 1
	171	* GP41 == RTS is 1
	172	* GP47 == TXD is 1
	173	* GP49 == nPWE is 1
	174	* GP62 == LED_B is 1
	175	* GP63 == TDM_OE is 1
	176	* GP78 == nCS2 is 1
	177	* GP79 == nCS3 is 1
	178	* GP80 == nCS4 is 1
	179	*/
	180	#define CFG_GPSR0_VAL 0x03008000
	181	#define CFG_GPSR1_VAL 0xC0028282
	182	#define CFG_GPSR2_VAL 0x0001C000
	183
	184	/* GP02 == DON_RST is 0
	185	* GP23 == SCLK is 0
	186	* GP45 == USB_ACT is 0
	187	* GP60 == PLLEN is 0
	188	* GP61 == LED_A is 0
	189	* GP73 == SWUPD_LED is 0
	190	*/
	191	#define CFG_GPCR0_VAL 0x00800004
	192	#define CFG_GPCR1_VAL 0x30002000
	193	#define CFG_GPCR2_VAL 0x00000100
	194
	195	/* GP00 == DON_READY is input
	196	* GP01 == DON_OK is input
	197	* GP02 == DON_RST is output
	198	* GP03 == RESET_IND is input
	199	* GP07 == RES11 is input
	200	* GP09 == RES12 is input
	201	* GP11 == SWUPDATE is input
	202	* GP14 == nPOWEROK is input
	203	* GP15 == nCS1 is output
	204	* GP17 == RES22 is input
	205	* GP18 == RDY is input
	206	* GP23 == SCLK is output
	207	* GP24 == SFRM is output
	208	* GP25 == TXD is output
	209	* GP26 == RXD is input
	210	* GP32 == RES21 is input
	211	* GP33 == nCS5 is output
	212	* GP34 == FFRXD is input
	213	* GP35 == CTS is input
	214	* GP39 == FFTXD is output
	215	* GP41 == RTS is output
	216	* GP42 == USB_OK is input
	217	* GP45 == USB_ACT is output
	218	* GP46 == RXD is input
	219	* GP47 == TXD is output
	220	* GP49 == nPWE is output
	221	* GP58 == nCPUBUSINT is input
	222	* GP59 == LANINT is input
	223	* GP60 == PLLEN is output
	224	* GP61 == LED_A is output
	225	* GP62 == LED_B is output
	226	* GP63 == TDM_OE is output
	227	* GP64 == nDSPINT is input
	228	* GP65 == STRAP0 is input
229	* GP67 == STRAP1 is input
230	* GP69 == STRAP2 is input
231	* GP70 == STRAP3 is input
232	* GP71 == STRAP4 is input
233	* GP73 == SWUPD_LED is output
234	* GP78 == nCS2 is output
235	* GP79 == nCS3 is output
236	* GP80 == nCS4 is output
237	*/
238	#define CFG_GPDR0_VAL 0x03808004
239	#define CFG_GPDR1_VAL 0xF002A282
240	#define CFG_GPDR2_VAL 0x0001C200
241
242	/* GP15 == nCS1 is AF10
243	* GP18 == RDY is AF01
244	* GP23 == SCLK is AF10
245	* GP24 == SFRM is AF10
246	* GP25 == TXD is AF10
247	* GP26 == RXD is AF01
248	* GP33 == nCS5 is AF10
249	* GP34 == FFRXD is AF01
250	* GP35 == CTS is AF01
251	* GP39 == FFTXD is AF10
252	* GP41 == RTS is AF10
253	* GP46 == RXD is AF10
254	* GP47 == TXD is AF01
255	* GP49 == nPWE is AF10
256	* GP78 == nCS2 is AF10
257	* GP79 == nCS3 is AF10
258	* GP80 == nCS4 is AF10
fe8c2806	259	*/
fe8c2806	260	#define CFG_GAFR0_L_VAL 0x80000000
993cad93 WD	261	#define CFG_GAFR0_U_VAL 0x001A8010
	262	#define CFG_GAFR1_L_VAL 0x60088058
	263	#define CFG_GAFR1_U_VAL 0x00000008
	264	#define CFG_GAFR2_L_VAL 0xA0000000
fe8c2806 WD	265	#define CFG_GAFR2_U_VAL 0x00000002
fe8c2806 WD	266
993cad93 WD	267
	268	/* FIXME: set GPIO_RER/FER */
	269
	270	/* RDH = 1
	271	* PH = 1
	272	* VFS = 1
	273	* BFS = 1
	274	* SSS = 1
	275	*/
	276	#define CFG_PSSR_VAL 0x37
	277
	278	/*
	279	* Memory settings
	280	*
	281	* This is the configuration for nCS0/1 -> flash banks
	282	* configuration for nCS1:
	283	* [31] 0 - Slower Device
	284	* [30:28] 010 - CS deselect to CS time: 2(2MemClk) = 40 ns
	285	* [27:24] 0101 - Address to data valid in bursts: (5+1)*MemClk = 60 ns
	286	* [23:20] 1011 - " for first access: (11+2)*MemClk = 130 ns
	287	* [19] 1 - 16 Bit bus width
	288	* [18:16] 000 - nonburst RAM or FLASH
	289	* configuration for nCS0:
	290	* [15] 0 - Slower Device
	291	* [14:12] 010 - CS deselect to CS time: 2(2MemClk) = 40 ns
	292	* [11:08] 0101 - Address to data valid in bursts: (5+1)*MemClk = 60 ns
	293	* [07:04] 1011 - " for first access: (11+2)*MemClk = 130 ns
	294	* [03] 1 - 16 Bit bus width
	295	* [02:00] 000 - nonburst RAM or FLASH
	296	*/
	297	#define CFG_MSC0_VAL 0x25b825b8 /* flash banks */
	298
	299	/* This is the configuration for nCS2/3 -> TDM-Switch, DSP
	300	* configuration for nCS3: DSP
	301	* [31] 0 - Slower Device
	302	* [30:28] 001 - RRR3: CS deselect to CS time: 1(2MemClk) = 20 ns
	303	* [27:24] 0010 - RDN3: Address to data valid in bursts: (2+1)*MemClk = 30 ns
	304	* [23:20] 0011 - RDF3: Address for first access: (3+1)*MemClk = 40 ns
	305	* [19] 1 - 16 Bit bus width
	306	* [18:16] 100 - variable latency I/O
	307	* configuration for nCS2: TDM-Switch
	308	* [15] 0 - Slower Device
	309	* [14:12] 101 - RRR2: CS deselect to CS time: 5(2MemClk) = 100 ns
	310	* [11:08] 1001 - RDN2: Address to data valid in bursts: (9+1)*MemClk = 100 ns
	311	* [07:04] 0011 - RDF2: Address for first access: (3+1)*MemClk = 40 ns
	312	* [03] 1 - 16 Bit bus width
	313	* [02:00] 100 - variable latency I/O
	314	*/
	315	#define CFG_MSC1_VAL 0x123C593C /* TDM switch, DSP */
	316
	317	/* This is the configuration for nCS4/5 -> ExtBus, LAN Controller
	318	*
	319	* configuration for nCS5: LAN Controller
	320	* [31] 0 - Slower Device
	321	* [30:28] 001 - RRR5: CS deselect to CS time: 1(2MemClk) = 20 ns
	322	* [27:24] 0010 - RDN5: Address to data valid in bursts: (2+1)*MemClk = 30 ns
	323	* [23:20] 0011 - RDF5: Address for first access: (3+1)*MemClk = 40 ns
	324	* [19] 1 - 16 Bit bus width
	325	* [18:16] 100 - variable latency I/O
	326	* configuration for nCS4: ExtBus
	327	* [15] 0 - Slower Device
	328	* [14:12] 110 - RRR4: CS deselect to CS time: 6(2MemClk) = 120 ns
	329	* [11:08] 1100 - RDN4: Address to data valid in bursts: (12+1)*MemClk = 130 ns
	330	* [07:04] 1101 - RDF4: Address for first access: 13->(15+1)*MemClk = 160 ns
331	* [03] 1 - 16 Bit bus width
332	* [02:00] 100 - variable latency I/O
333	*/
334	#define CFG_MSC2_VAL 0x123C6CDC /* extra bus, LAN controller */
335
336	/* MDCNFG: SDRAM Configuration Register
337	*
338	* [31:29] 000 - reserved
339	* [28] 0 - no SA1111 compatiblity mode
340	* [27] 0 - latch return data with return clock
341	* [26] 0 - alternate addressing for pair 2/3
342	* [25:24] 00 - timings
343	* [23] 0 - internal banks in lower partition 2/3 (not used)
344	* [22:21] 00 - row address bits for partition 2/3 (not used)
345	* [20:19] 00 - column address bits for partition 2/3 (not used)
346	* [18] 0 - SDRAM partition 2/3 width is 32 bit
347	* [17] 0 - SDRAM partition 3 disabled
348	* [16] 0 - SDRAM partition 2 disabled
349	* [15:13] 000 - reserved
350	* [12] 1 - SA1111 compatiblity mode
351	* [11] 1 - latch return data with return clock
352	* [10] 0 - no alternate addressing for pair 0/1
353	* [09:08] 01 - tRP=2MemClk CL=2 tRCD=2MemClk tRAS=5MemClk tRC=8MemClk
354	* [7] 1 - 4 internal banks in lower partition pair
355	* [06:05] 10 - 13 row address bits for partition 0/1
356	* [04:03] 01 - 9 column address bits for partition 0/1
357	* [02] 0 - SDRAM partition 0/1 width is 32 bit
358	* [01] 0 - disable SDRAM partition 1
359	* [00] 1 - enable SDRAM partition 0
360	*/
361	/* use the configuration above but disable partition 0 */
362	#define CFG_MDCNFG_VAL 0x000019c8
363
364	/* MDREFR: SDRAM Refresh Control Register
365	*
366	* [32:26] 0 - reserved
367	* [25] 0 - K2FREE: not free running
368	* [24] 0 - K1FREE: not free running
369	* [23] 1 - K0FREE: not free running
370	* [22] 0 - SLFRSH: self refresh disabled
371	* [21] 0 - reserved
372	* [20] 0 - APD: no auto power down
373	* [19] 0 - K2DB2: SDCLK2 is MemClk
374	* [18] 0 - K2RUN: disable SDCLK2
375	* [17] 0 - K1DB2: SDCLK1 is MemClk
376	* [16] 1 - K1RUN: enable SDCLK1
377	* [15] 1 - E1PIN: SDRAM clock enable
378	* [14] 1 - K0DB2: SDCLK0 is MemClk
379	* [13] 0 - K0RUN: disable SDCLK0
380	* [12] 1 - E0PIN: disable SDCKE0
381	* [11:00] 000000011000 - (64ms/8192)*MemClkFreq/32 = 24
382	*/
383	#define CFG_MDREFR_VAL 0x0081D018
384
385	/* MDMRS: Mode Register Set Configuration Register
386	*
387	* [31] 0 - reserved
388	* [30:23] 00000000- MDMRS2: SDRAM2/3 MRS Value. (not used)
389	* [22:20] 000 - MDCL2: SDRAM2/3 Cas Latency. (not used)
390	* [19] 0 - MDADD2: SDRAM2/3 burst Type. Fixed to sequential. (not used)
391	* [18:16] 010 - MDBL2: SDRAM2/3 burst Length. Fixed to 4. (not used)
392	* [15] 0 - reserved
393	* [14:07] 00000000- MDMRS0: SDRAM0/1 MRS Value.
394	* [06:04] 010 - MDCL0: SDRAM0/1 Cas Latency.
395	* [03] 0 - MDADD0: SDRAM0/1 burst Type. Fixed to sequential.
396	* [02:00] 010 - MDBL0: SDRAM0/1 burst Length. Fixed to 4.
397	*/
398	#define CFG_MDMRS_VAL 0x00020022
399
400	/*
401	* PCMCIA and CF Interfaces
402	*/
403	#define CFG_MECR_VAL 0x00000000
404	#define CFG_MCMEM0_VAL 0x00000000
405	#define CFG_MCMEM1_VAL 0x00000000
406	#define CFG_MCATT0_VAL 0x00000000
407	#define CFG_MCATT1_VAL 0x00000000
408	#define CFG_MCIO0_VAL 0x00000000
409	#define CFG_MCIO1_VAL 0x00000000
410	#endif
411
412	/*
413	* GPIO settings
414	*/
415	#define CFG_GPSR0_VAL 0xFFFFFFFF
416	#define CFG_GPSR1_VAL 0xFFFFFFFF
417	#define CFG_GPSR2_VAL 0xFFFFFFFF
418	#define CFG_GPCR0_VAL 0x08022080
419	#define CFG_GPCR1_VAL 0x00000000
420	#define CFG_GPCR2_VAL 0x00000000
421	#define CFG_GPDR0_VAL 0xCD82A878
422	#define CFG_GPDR1_VAL 0xFCFFAB80
423	#define CFG_GPDR2_VAL 0x0001FFFF
424	#define CFG_GAFR0_L_VAL 0x80000000
425	#define CFG_GAFR0_U_VAL 0xA5254010
426	#define CFG_GAFR1_L_VAL 0x599A9550
427	#define CFG_GAFR1_U_VAL 0xAAA5AAAA
428	#define CFG_GAFR2_L_VAL 0xAAAAAAAA
429	#define CFG_GAFR2_U_VAL 0x00000002
430
fe8c2806 WD	431	/* FIXME: set GPIO_RER/FER */
	432
	433	#define CFG_PSSR_VAL 0x20
	434
	435	/*
	436	* Memory settings
	437	*/
993cad93 WD	438
	439	#define CFG_MSC0_VAL 0x2ef15af0
	440	#define CFG_MSC1_VAL 0x00003ff4
	441	#define CFG_MSC2_VAL 0x7ff07ff0
	442	#define CFG_MDCNFG_VAL 0x09a909a9
	443	#define CFG_MDREFR_VAL 0x038ff030
	444	#define CFG_MDMRS_VAL 0x00220022
fe8c2806 WD	445
	446	/*
	447	* PCMCIA and CF Interfaces
	448	*/
	449	#define CFG_MECR_VAL 0x00000000
	450	#define CFG_MCMEM0_VAL 0x00000000
	451	#define CFG_MCMEM1_VAL 0x00000000
	452	#define CFG_MCATT0_VAL 0x00000000
	453	#define CFG_MCATT1_VAL 0x00000000
	454	#define CFG_MCIO0_VAL 0x00000000
	455	#define CFG_MCIO1_VAL 0x00000000
	456
384ae025 WD	457	#define CSB226_USER_LED0 0x00000008
	458	#define CSB226_USER_LED1 0x00000010
	459	#define CSB226_USER_LED2 0x00000020
	460
fe8c2806 WD	461
	462	/*
	463	* FLASH and environment organization
	464	*/
	465	#define CFG_MAX_FLASH_BANKS 1 /* max number of memory banks */
	466	#define CFG_MAX_FLASH_SECT 128 /* max number of sect. on one chip */
	467
	468	/* timeout values are in ticks */
	469	#define CFG_FLASH_ERASE_TOUT (2CFG_HZ) / Timeout for Flash Erase */
	470	#define CFG_FLASH_WRITE_TOUT (2CFG_HZ) / Timeout for Flash Write */
	471
	472	#define CFG_ENV_IS_IN_FLASH 1
	473	#define CFG_ENV_ADDR (PHYS_FLASH_1 + 0x1C000)
	474	/* Addr of Environment Sector */
	475	#define CFG_ENV_SIZE 0x4000 /* Total Size of Environment Sector */
	476
	477	#endif /* __CONFIG_H */