[J-u-boot.git] / include / configs / pf5200.h

/*
 * (C) Copyright 2003-2004
 * Wolfgang Denk, DENX Software Engineering, [email protected].
 *
 * See file CREDITS for list of people who contributed to this
 * project.
 *
 * This program is free software; you can redistribute it and/or
 * modify it under the terms of the GNU General Public License as
 * published by the Free Software Foundation; either version 2 of
 * the License, or (at your option) any later version.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
 * GNU General Public License for more details.
 *
 * You should have received a copy of the GNU General Public License
 * along with this program; if not, write to the Free Software
 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
 * MA 02111-1307 USA
 */

/*************************************************************************
 * (c) 2005 esd gmbh Hannover
 *
 *
 * from IceCube.h file
 * by Reinhard Arlt [email protected]
 *
 *************************************************************************/

#ifndef __CONFIG_H
#define __CONFIG_H

/*
 * High Level Configuration Options
 * (easy to change)
 */

#define CONFIG_MPC5200		1	/* This is an MPC5xxx CPU */
#define CONFIG_MPC5xxx		1	/* This is an MPC5xxx CPU */
#define CONFIG_ICECUBE		1	/* ... on IceCube board */
#define CONFIG_PF5200		1	/* ... on PF5200  board */
#define CONFIG_MPC5200_DDR	1	/* ... use DDR RAM	*/

#define CFG_MPC5XXX_CLKIN	33000000	/* ... running at 33.000000MHz */

#define BOOTFLAG_COLD		0x01	/* Normal Power-On: Boot from FLASH  */
#define BOOTFLAG_WARM		0x02	/* Software reboot	     */

#define CFG_CACHELINE_SIZE	32	/* For MPC5xxx CPUs */
#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
#  define CFG_CACHELINE_SHIFT	5	/* log base 2 of the above value */
#endif

/*
 * Serial console configuration
 */
#define CONFIG_PSC_CONSOLE	1	/* console is on PSC1 */
#if 0				/* test-only */
#define CONFIG_BAUDRATE		115200	/* ... at 115200 bps */
#else
#define CONFIG_BAUDRATE		9600	/* ... at 115200 bps */
#endif
#define CFG_BAUDRATE_TABLE	{ 9600, 19200, 38400, 57600, 115200, 230400 }

#ifdef CONFIG_MPC5200		/* MPC5100 PCI is not supported yet. */
/*
 * PCI Mapping:
 * 0x40000000 - 0x4fffffff - PCI Memory
 * 0x50000000 - 0x50ffffff - PCI IO Space
 */
#define CONFIG_PCI		1
#define CONFIG_PCI_PNP		1
#define CONFIG_PCI_SCAN_SHOW	1

#define CONFIG_PCI_MEM_BUS	0x40000000
#define CONFIG_PCI_MEM_PHYS	CONFIG_PCI_MEM_BUS
#define CONFIG_PCI_MEM_SIZE	0x10000000

#define CONFIG_PCI_IO_BUS	0x50000000
#define CONFIG_PCI_IO_PHYS	CONFIG_PCI_IO_BUS
#define CONFIG_PCI_IO_SIZE	0x01000000

#define CONFIG_MII		1
#if 0				/* test-only !!! */
#define CONFIG_NET_MULTI	1
#define CONFIG_EEPRO100		1
#define CFG_RX_ETH_BUFFER	8	/* use 8 rx buffer on eepro100	*/
#define CONFIG_NS8382X		1
#endif

#define ADD_PCI_CMD		CFG_CMD_PCI

#else				/* MPC5100 */

#define ADD_PCI_CMD		0	/* no CFG_CMD_PCI */

#endif

/* Partitions */
#define CONFIG_MAC_PARTITION
#define CONFIG_DOS_PARTITION

/* USB */
#if 0
#define CONFIG_USB_OHCI
#define ADD_USB_CMD		CFG_CMD_USB | CFG_CMD_FAT
#define CONFIG_USB_STORAGE
#else
#define ADD_USB_CMD		0
#endif

/*
 * Supported commands
 */
#define CONFIG_COMMANDS		(CONFIG_CMD_DFL	| \
				 CFG_CMD_EEPROM	| \
				 CFG_CMD_FAT	| \
				 CFG_CMD_I2C	| \
				 CFG_CMD_IDE	| \
				 CFG_CMD_BSP	| \
				 CFG_CMD_ELF	| \
				 ADD_PCI_CMD	  )

/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
#include <cmd_confdefs.h>

#if (TEXT_BASE == 0xFF000000)	/* Boot low with 16 MB Flash */
#   define CFG_LOWBOOT		1
#   define CFG_LOWBOOT16	1
#endif
#if (TEXT_BASE == 0xFF800000)	/* Boot low with  8 MB Flash */
#   define CFG_LOWBOOT		1
#   define CFG_LOWBOOT08	1
#endif

/*
 * Autobooting
 */
#define CONFIG_BOOTDELAY	3	/* autoboot after 5 seconds */

#define CONFIG_PREBOOT	"echo;"	\
	"echo Welcome to ParaFinder pf5200;" \
	"echo"

#undef	CONFIG_BOOTARGS

#define	CONFIG_EXTRA_ENV_SETTINGS \
	"netdev=eth0\0" \
	"flash_vxworks0=run ata_vxworks_args;setenv loadaddr ff000000;bootvx\0" \
	"flash_vxworks1=run ata_vxworks_args;setenv loadaddr ff200000:bootvx\0" \
	"net_vxworks=phypower 1;sleep 2;tftp ${loadaddr} ${image};run vxworks_args;bootvx\0" \
	"vxworks_args=setenv bootargs fec(0,0)${host}:${image} h=${serverip} e=${ipaddr} g=${gatewayip} u=${user} ${pass} tn=${target} s=${script}\0" \
	"ata_vxworks_args=setenv bootargs /ata0/vxWorks h=${serverip} e=${ipaddr} g=${gatewayip} u=${user} ${pass} tn=${target} s=${script} o=fec0 \0" \
	"loadaddr=01000000\0" \
	"serverip=192.168.2.99\0" \
	"gatewayip=10.0.0.79\0" \
	"user=mu\0" \
	"target=pf5200.esd\0" \
	"script=pf5200.bat\0" \
	"image=/tftpboot/vxWorks_pf5200\0" \
	"ipaddr=10.0.13.196\0" \
	"netmask=255.255.0.0\0" \
	""

#define CONFIG_BOOTCOMMAND	"run flash_vxworks0"

#if defined(CONFIG_MPC5200)
/*
 * IPB Bus clocking configuration.
 */
#undef CFG_IPBCLK_EQUALS_XLBCLK		/* define for 133MHz speed */
#endif
/*
 * I2C configuration
 */
#define CONFIG_HARD_I2C		1	/* I2C with hardware support */
#define CFG_I2C_MODULE		2	/* Select I2C module #1 or #2 */

#define CFG_I2C_SPEED		86000	/* 100 kHz */
#define CFG_I2C_SLAVE		0x7F

/*
 * EEPROM configuration
 */
#define CFG_I2C_EEPROM_ADDR		0x50	/* 1010000x */
#define CFG_I2C_EEPROM_ADDR_LEN		2
#define CFG_EEPROM_PAGE_WRITE_BITS	5
#define CFG_EEPROM_PAGE_WRITE_DELAY_MS	20
#define CFG_I2C_MULTI_EEPROMS		1
/*
 * Flash configuration
 */
#define CFG_FLASH_BASE		0xFE000000
#define CFG_FLASH_SIZE		0x02000000
#define CFG_ENV_ADDR		(CFG_FLASH_BASE + 0x00000000)
#define CFG_MAX_FLASH_BANKS	1	/* max num of memory banks	*/
#define CFG_MAX_FLASH_SECT	512

#define CFG_FLASH_ERASE_TOUT	240000	/* Flash Erase Timeout (in ms)	*/
#define CFG_FLASH_WRITE_TOUT	500	/* Flash Write Timeout (in ms)	*/

/*
 * Environment settings
 */
#if 1				/* test-only */
#define CFG_ENV_IS_IN_FLASH	0
#define CFG_ENV_SIZE		0x10000
#define CFG_ENV_SECT_SIZE	0x10000
#define CONFIG_ENV_OVERWRITE	1
#else
#define CFG_ENV_IS_IN_EEPROM	1	/* use EEPROM for environment vars */
#define CFG_ENV_OFFSET		0x0000	/* environment starts at the beginning of the EEPROM */
#define CFG_ENV_SIZE		0x0400	/* 8192 bytes may be used for env vars */
				   /* total size of a CAT24WC32 is 8192 bytes */
#define CONFIG_ENV_OVERWRITE	1
#endif

/*
 * Memory map
 */
#define CFG_MBAR		0xF0000000
#define CFG_SDRAM_BASE		0x00000000
#define CFG_DEFAULT_MBAR	0x80000000

/* Use SRAM until RAM will be available */
#define CFG_INIT_RAM_ADDR	MPC5XXX_SRAM
#define CFG_INIT_RAM_END	MPC5XXX_SRAM_SIZE	/* End of used area in DPRAM */

#define CFG_GBL_DATA_SIZE	128	/* size in bytes reserved for initial data */
#define CFG_GBL_DATA_OFFSET	(CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
#define CFG_INIT_SP_OFFSET	CFG_GBL_DATA_OFFSET

#define CFG_MONITOR_BASE    TEXT_BASE
#if (CFG_MONITOR_BASE < CFG_FLASH_BASE)
#   define CFG_RAMBOOT		1
#endif

#define CFG_MONITOR_LEN		(192 << 10)	/* Reserve 192 kB for Monitor	*/
#define CFG_MALLOC_LEN		(128 << 10)	/* Reserve 128 kB for malloc()	*/
#define CFG_BOOTMAPSZ		(8 << 20)	/* Initial Memory map for Linux */

/*
 * Ethernet configuration
 */
#define CONFIG_MPC5xxx_FEC	1
/*
 * Define CONFIG_FEC_10MBIT to force FEC at 10Mb
 */
/* #define CONFIG_FEC_10MBIT 1 */
#define CONFIG_PHY_ADDR		0x00
#define CONFIG_UDP_CHECKSUM	1

/*
 * GPIO configuration
 */
#define CFG_GPS_PORT_CONFIG	0x01052444

/*
 * Miscellaneous configurable options
 */
#define CFG_LONGHELP		/* undef to save memory	    */
#define CFG_PROMPT		"=> "	/* Monitor Command Prompt   */
#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
#define CFG_CBSIZE		1024	/* Console I/O Buffer Size  */
#else
#define CFG_CBSIZE		256	/* Console I/O Buffer Size  */
#endif
#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16)	/* Print Buffer Size */
#define CFG_MAXARGS		16	/* max number of command args	*/
#define CFG_BARGSIZE		CFG_CBSIZE	/* Boot Argument Buffer Size	*/

#define CFG_MEMTEST_START	0x00100000	/* memtest works on */
#define CFG_MEMTEST_END		0x00f00000	/* 1 ... 15 MB in DRAM	*/

#define CFG_LOAD_ADDR		0x100000	/* default load address */

#define CFG_HZ			1000	/* decrementer freq: 1 ms ticks */

#define CFG_VXWORKS_MAC_PTR	0x00000000	/* Pass Ethernet MAC to VxWorks */

/*
 * Various low-level settings
 */
#if defined(CONFIG_MPC5200)
#define CFG_HID0_INIT		HID0_ICE | HID0_ICFI
#define CFG_HID0_FINAL		HID0_ICE
#else
#define CFG_HID0_INIT		0
#define CFG_HID0_FINAL		0
#endif

#define CFG_BOOTCS_START	CFG_FLASH_BASE
#define CFG_BOOTCS_SIZE		CFG_FLASH_SIZE
#define CFG_BOOTCS_CFG		0x0004DD00

#define CFG_CS0_START		CFG_FLASH_BASE
#define CFG_CS0_SIZE		CFG_FLASH_SIZE

#define CFG_CS1_START		0xfd000000
#define CFG_CS1_SIZE		0x00010000
#define CFG_CS1_CFG		0x10101410

#define CFG_CS_BURST		0x00000000
#define CFG_CS_DEADCYCLE	0x33333333

#define CFG_RESET_ADDRESS	0xff000000

/*-----------------------------------------------------------------------
 * USB stuff
 *-----------------------------------------------------------------------
 */
#define CONFIG_USB_CLOCK	0x0001BBBB
#define CONFIG_USB_CONFIG	0x00001000

/*-----------------------------------------------------------------------
 * IDE/ATA stuff Supports IDE harddisk
 *-----------------------------------------------------------------------
 */

#undef	CONFIG_IDE_8xx_PCCARD	/* Use IDE with PC Card Adapter */

#undef	CONFIG_IDE_8xx_DIRECT	/* Direct IDE	 not supported	*/
#undef	CONFIG_IDE_LED		/* LED	 for ide not supported	*/

#define	CONFIG_IDE_RESET	/* reset for ide supported	*/
#define CONFIG_IDE_PREINIT

#define CFG_IDE_MAXBUS		1	/* max. 1 IDE bus		*/
#define CFG_IDE_MAXDEVICE	1	/* max. 1 drive per IDE bus	*/

#define CFG_ATA_IDE0_OFFSET	0x0000

#define CFG_ATA_BASE_ADDR	MPC5XXX_ATA

/* Offset for data I/O			*/
#define CFG_ATA_DATA_OFFSET	(0x0060)

/* Offset for normal register accesses	*/
#define CFG_ATA_REG_OFFSET	(CFG_ATA_DATA_OFFSET)

/* Offset for alternate registers	*/
#define CFG_ATA_ALT_OFFSET	(0x005C)

/* Interval between registers						     */
#define CFG_ATA_STRIDE		4

/*-----------------------------------------------------------------------
 * CPLD stuff
 */
#define CFG_FPGA_XC95XL		1	/* using Xilinx XC95XL CPLD	 */
#define CFG_FPGA_MAX_SIZE	32*1024	/* 32kByte is enough for CPLD	 */

/* CPLD program pin configuration */
#define CFG_FPGA_PRG		0x20000000	/* JTAG TMS pin (ppc output)	       */
#define CFG_FPGA_CLK		0x10000000	/* JTAG TCK pin (ppc output)	       */
#define CFG_FPGA_DATA		0x20000000	/* JTAG TDO->TDI data pin (ppc output) */
#define CFG_FPGA_DONE		0x10000000	/* JTAG TDI->TDO pin (ppc input)       */

#define JTAG_GPIO_ADDR_TMS	(CFG_MBAR + 0xB10)	/* JTAG TMS pin (GPS data out value reg.)      */
#define JTAG_GPIO_ADDR_TCK	(CFG_MBAR + 0xC0C)	/* JTAG TCK pin (GPW data out value reg.)      */
#define JTAG_GPIO_ADDR_TDI	(CFG_MBAR + 0xC0C)	/* JTAG TDO->TDI pin (GPW data out value reg.) */
#define JTAG_GPIO_ADDR_TDO	(CFG_MBAR + 0xB14)	/* JTAG TDI->TDO pin (GPS data in value reg.)  */

#define JTAG_GPIO_ADDR_CFG	(CFG_MBAR + 0xB00)
#define JTAG_GPIO_CFG_SET	0x00000000
#define JTAG_GPIO_CFG_RESET	0x00F00000

#define JTAG_GPIO_ADDR_EN_TMS	(CFG_MBAR + 0xB04)
#define JTAG_GPIO_TMS_EN_SET	0x20000000	/* Enable for GPIO */
#define JTAG_GPIO_TMS_EN_RESET	0x00000000
#define JTAG_GPIO_ADDR_DDR_TMS	(CFG_MBAR + 0xB0C)
#define JTAG_GPIO_TMS_DDR_SET	0x20000000	/* Set as output   */
#define JTAG_GPIO_TMS_DDR_RESET 0x00000000

#define JTAG_GPIO_ADDR_EN_TCK	(CFG_MBAR + 0xC00)
#define JTAG_GPIO_TCK_EN_SET	0x20000000	/* Enable for GPIO */
#define JTAG_GPIO_TCK_EN_RESET	0x00000000
#define JTAG_GPIO_ADDR_DDR_TCK	(CFG_MBAR + 0xC08)
#define JTAG_GPIO_TCK_DDR_SET	0x20000000	/* Set as output   */
#define JTAG_GPIO_TCK_DDR_RESET 0x00000000

#define JTAG_GPIO_ADDR_EN_TDI	(CFG_MBAR + 0xC00)
#define JTAG_GPIO_TDI_EN_SET	0x10000000	/* Enable as GPIO  */
#define JTAG_GPIO_TDI_EN_RESET	0x00000000
#define JTAG_GPIO_ADDR_DDR_TDI	(CFG_MBAR + 0xC08)
#define JTAG_GPIO_TDI_DDR_SET	0x10000000	/* Set as output   */
#define JTAG_GPIO_TDI_DDR_RESET 0x00000000

#define JTAG_GPIO_ADDR_EN_TDO	(CFG_MBAR + 0xB04)
#define JTAG_GPIO_TDO_EN_SET	0x10000000	/* Enable as GPIO  */
#define JTAG_GPIO_TDO_EN_RESET	0x00000000
#define JTAG_GPIO_ADDR_DDR_TDO	(CFG_MBAR + 0xB0C)
#define JTAG_GPIO_TDO_DDR_SET	0x00000000
#define JTAG_GPIO_TDO_DDR_RESET 0x10000000	/* Set as input	   */

#endif				/* __CONFIG_H */
Commit	Line	Data
5e4b3361 SR	1	/*
	2	* (C) Copyright 2003-2004
	3	* Wolfgang Denk, DENX Software Engineering, [email protected].
	4	*
	5	* See file CREDITS for list of people who contributed to this
	6	* project.
	7	*
	8	* This program is free software; you can redistribute it and/or
	9	* modify it under the terms of the GNU General Public License as
	10	* published by the Free Software Foundation; either version 2 of
	11	* the License, or (at your option) any later version.
	12	*
	13	* This program is distributed in the hope that it will be useful,
	14	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	15	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	16	* GNU General Public License for more details.
	17	*
	18	* You should have received a copy of the GNU General Public License
	19	* along with this program; if not, write to the Free Software
	20	* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
	21	* MA 02111-1307 USA
	22	*/
	23
	24	/*************************************************************************
	25	* (c) 2005 esd gmbh Hannover
	26	*
	27	*
	28	* from IceCube.h file
	29	* by Reinhard Arlt [email protected]
	30	*
	31	*************************************************************************/
	32
	33	#ifndef __CONFIG_H
	34	#define __CONFIG_H
	35
	36	/*
	37	* High Level Configuration Options
	38	* (easy to change)
	39	*/
	40
	41	#define CONFIG_MPC5200 1 /* This is an MPC5xxx CPU */
	42	#define CONFIG_MPC5xxx 1 /* This is an MPC5xxx CPU */
	43	#define CONFIG_ICECUBE 1 /* ... on IceCube board */
	44	#define CONFIG_PF5200 1 /* ... on PF5200 board */
	45	#define CONFIG_MPC5200_DDR 1 /* ... use DDR RAM */
	46
	47	#define CFG_MPC5XXX_CLKIN 33000000 /* ... running at 33.000000MHz */
	48
	49	#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */
	50	#define BOOTFLAG_WARM 0x02 /* Software reboot */
	51
	52	#define CFG_CACHELINE_SIZE 32 /* For MPC5xxx CPUs */
	53	#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
	54	# define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */
	55	#endif
	56
	57	/*
	58	* Serial console configuration
	59	*/
	60	#define CONFIG_PSC_CONSOLE 1 /* console is on PSC1 */
	61	#if 0 /* test-only */
	62	#define CONFIG_BAUDRATE 115200 /* ... at 115200 bps */
	63	#else
	64	#define CONFIG_BAUDRATE 9600 /* ... at 115200 bps */
65	#endif
66	#define CFG_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200, 230400 }
67
68	#ifdef CONFIG_MPC5200 /* MPC5100 PCI is not supported yet. */
69	/*
70	* PCI Mapping:
71	* 0x40000000 - 0x4fffffff - PCI Memory
72	* 0x50000000 - 0x50ffffff - PCI IO Space
73	*/
74	#define CONFIG_PCI 1
75	#define CONFIG_PCI_PNP 1
76	#define CONFIG_PCI_SCAN_SHOW 1
77
78	#define CONFIG_PCI_MEM_BUS 0x40000000
79	#define CONFIG_PCI_MEM_PHYS CONFIG_PCI_MEM_BUS
80	#define CONFIG_PCI_MEM_SIZE 0x10000000
81
82	#define CONFIG_PCI_IO_BUS 0x50000000
83	#define CONFIG_PCI_IO_PHYS CONFIG_PCI_IO_BUS
84	#define CONFIG_PCI_IO_SIZE 0x01000000
85
63ff004c	86	#define CONFIG_MII 1
5e4b3361 SR	87	#if 0 /* test-only !!! */
	88	#define CONFIG_NET_MULTI 1
	89	#define CONFIG_EEPRO100 1
	90	#define CFG_RX_ETH_BUFFER 8 /* use 8 rx buffer on eepro100 */
	91	#define CONFIG_NS8382X 1
	92	#endif
	93
	94	#define ADD_PCI_CMD CFG_CMD_PCI
	95
	96	#else /* MPC5100 */
	97
	98	#define ADD_PCI_CMD 0 /* no CFG_CMD_PCI */
	99
	100	#endif
	101
	102	/* Partitions */
	103	#define CONFIG_MAC_PARTITION
	104	#define CONFIG_DOS_PARTITION
	105
	106	/* USB */
	107	#if 0
	108	#define CONFIG_USB_OHCI
	109	#define ADD_USB_CMD CFG_CMD_USB \| CFG_CMD_FAT
	110	#define CONFIG_USB_STORAGE
	111	#else
	112	#define ADD_USB_CMD 0
	113	#endif
	114
	115	/*
	116	* Supported commands
	117	*/
	118	#define CONFIG_COMMANDS (CONFIG_CMD_DFL \| \
	119	CFG_CMD_EEPROM \| \
	120	CFG_CMD_FAT \| \
	121	CFG_CMD_I2C \| \
	122	CFG_CMD_IDE \| \
	123	CFG_CMD_BSP \| \
	124	CFG_CMD_ELF \| \
	125	ADD_PCI_CMD )
	126
	127	/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
	128	#include <cmd_confdefs.h>
	129
	130	#if (TEXT_BASE == 0xFF000000) /* Boot low with 16 MB Flash */
	131	# define CFG_LOWBOOT 1
	132	# define CFG_LOWBOOT16 1
	133	#endif
	134	#if (TEXT_BASE == 0xFF800000) /* Boot low with 8 MB Flash */
	135	# define CFG_LOWBOOT 1
	136	# define CFG_LOWBOOT08 1
	137	#endif
	138
	139	/*
	140	* Autobooting
	141	*/
	142	#define CONFIG_BOOTDELAY 3 /* autoboot after 5 seconds */
	143
	144	#define CONFIG_PREBOOT "echo;" \
	145	"echo Welcome to ParaFinder pf5200;" \
	146	"echo"
	147
	148	#undef CONFIG_BOOTARGS
	149
	150	#define CONFIG_EXTRA_ENV_SETTINGS \
151	"netdev=eth0\0" \
152	"flash_vxworks0=run ata_vxworks_args;setenv loadaddr ff000000;bootvx\0" \
153	"flash_vxworks1=run ata_vxworks_args;setenv loadaddr ff200000:bootvx\0" \
fe126d8b WD	154	"net_vxworks=phypower 1;sleep 2;tftp ${loadaddr} ${image};run vxworks_args;bootvx\0" \
	155	"vxworks_args=setenv bootargs fec(0,0)${host}:${image} h=${serverip} e=${ipaddr} g=${gatewayip} u=${user} ${pass} tn=${target} s=${script}\0" \
	156	"ata_vxworks_args=setenv bootargs /ata0/vxWorks h=${serverip} e=${ipaddr} g=${gatewayip} u=${user} ${pass} tn=${target} s=${script} o=fec0 \0" \
5e4b3361 SR	157	"loadaddr=01000000\0" \
	158	"serverip=192.168.2.99\0" \
	159	"gatewayip=10.0.0.79\0" \
	160	"user=mu\0" \
	161	"target=pf5200.esd\0" \
	162	"script=pf5200.bat\0" \
	163	"image=/tftpboot/vxWorks_pf5200\0" \
	164	"ipaddr=10.0.13.196\0" \
	165	"netmask=255.255.0.0\0" \
	166	""
	167
	168	#define CONFIG_BOOTCOMMAND "run flash_vxworks0"
	169
	170	#if defined(CONFIG_MPC5200)
	171	/*
	172	* IPB Bus clocking configuration.
	173	*/
c99512d6	174	#undef CFG_IPBCLK_EQUALS_XLBCLK /* define for 133MHz speed */
5e4b3361 SR	175	#endif
	176	/*
	177	* I2C configuration
	178	*/
	179	#define CONFIG_HARD_I2C 1 /* I2C with hardware support */
	180	#define CFG_I2C_MODULE 2 /* Select I2C module #1 or #2 */
	181
	182	#define CFG_I2C_SPEED 86000 /* 100 kHz */
	183	#define CFG_I2C_SLAVE 0x7F
	184
	185	/*
	186	* EEPROM configuration
	187	*/
	188	#define CFG_I2C_EEPROM_ADDR 0x50 /* 1010000x */
	189	#define CFG_I2C_EEPROM_ADDR_LEN 2
	190	#define CFG_EEPROM_PAGE_WRITE_BITS 5
	191	#define CFG_EEPROM_PAGE_WRITE_DELAY_MS 20
	192	#define CFG_I2C_MULTI_EEPROMS 1
	193	/*
	194	* Flash configuration
	195	*/
	196	#define CFG_FLASH_BASE 0xFE000000
	197	#define CFG_FLASH_SIZE 0x02000000
	198	#define CFG_ENV_ADDR (CFG_FLASH_BASE + 0x00000000)
	199	#define CFG_MAX_FLASH_BANKS 1 /* max num of memory banks */
	200	#define CFG_MAX_FLASH_SECT 512
	201
	202	#define CFG_FLASH_ERASE_TOUT 240000 /* Flash Erase Timeout (in ms) */
	203	#define CFG_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (in ms) */
	204
	205	/*
	206	* Environment settings
	207	*/
	208	#if 1 /* test-only */
	209	#define CFG_ENV_IS_IN_FLASH 0
	210	#define CFG_ENV_SIZE 0x10000
	211	#define CFG_ENV_SECT_SIZE 0x10000
	212	#define CONFIG_ENV_OVERWRITE 1
	213	#else
	214	#define CFG_ENV_IS_IN_EEPROM 1 /* use EEPROM for environment vars */
	215	#define CFG_ENV_OFFSET 0x0000 /* environment starts at the beginning of the EEPROM */
	216	#define CFG_ENV_SIZE 0x0400 /* 8192 bytes may be used for env vars */
	217	/* total size of a CAT24WC32 is 8192 bytes */
	218	#define CONFIG_ENV_OVERWRITE 1
	219	#endif
	220
	221	/*
	222	* Memory map
	223	*/
	224	#define CFG_MBAR 0xF0000000
	225	#define CFG_SDRAM_BASE 0x00000000
	226	#define CFG_DEFAULT_MBAR 0x80000000
	227
	228	/* Use SRAM until RAM will be available */
	229	#define CFG_INIT_RAM_ADDR MPC5XXX_SRAM
	230	#define CFG_INIT_RAM_END MPC5XXX_SRAM_SIZE /* End of used area in DPRAM */
	231
	232	#define CFG_GBL_DATA_SIZE 128 /* size in bytes reserved for initial data */
	233	#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
	234	#define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET
	235
	236	#define CFG_MONITOR_BASE TEXT_BASE
	237	#if (CFG_MONITOR_BASE < CFG_FLASH_BASE)
	238	# define CFG_RAMBOOT 1
239	#endif
240
241	#define CFG_MONITOR_LEN (192 << 10) /* Reserve 192 kB for Monitor */
242	#define CFG_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */
243	#define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
244
245	/*
246	* Ethernet configuration
247	*/
248	#define CONFIG_MPC5xxx_FEC 1
249	/*
250	* Define CONFIG_FEC_10MBIT to force FEC at 10Mb
251	*/
252	/* #define CONFIG_FEC_10MBIT 1 */
253	#define CONFIG_PHY_ADDR 0x00
254	#define CONFIG_UDP_CHECKSUM 1
255
256	/*
257	* GPIO configuration
258	*/
259	#define CFG_GPS_PORT_CONFIG 0x01052444
260
261	/*
262	* Miscellaneous configurable options
263	*/
264	#define CFG_LONGHELP /* undef to save memory */
265	#define CFG_PROMPT "=> " /* Monitor Command Prompt */
266	#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
267	#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */
268	#else
269	#define CFG_CBSIZE 256 /* Console I/O Buffer Size */
270	#endif
271	#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
272	#define CFG_MAXARGS 16 /* max number of command args */
273	#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */
274
275	#define CFG_MEMTEST_START 0x00100000 /* memtest works on */
276	#define CFG_MEMTEST_END 0x00f00000 /* 1 ... 15 MB in DRAM */
277
278	#define CFG_LOAD_ADDR 0x100000 /* default load address */
279
280	#define CFG_HZ 1000 /* decrementer freq: 1 ms ticks */
281
282	#define CFG_VXWORKS_MAC_PTR 0x00000000 /* Pass Ethernet MAC to VxWorks */
283
284	/*
285	* Various low-level settings
286	*/
287	#if defined(CONFIG_MPC5200)
288	#define CFG_HID0_INIT HID0_ICE \| HID0_ICFI
289	#define CFG_HID0_FINAL HID0_ICE
290	#else
291	#define CFG_HID0_INIT 0
292	#define CFG_HID0_FINAL 0
293	#endif
294
295	#define CFG_BOOTCS_START CFG_FLASH_BASE
296	#define CFG_BOOTCS_SIZE CFG_FLASH_SIZE
297	#define CFG_BOOTCS_CFG 0x0004DD00
298
299	#define CFG_CS0_START CFG_FLASH_BASE
300	#define CFG_CS0_SIZE CFG_FLASH_SIZE
301
302	#define CFG_CS1_START 0xfd000000
303	#define CFG_CS1_SIZE 0x00010000
304	#define CFG_CS1_CFG 0x10101410
305
306	#define CFG_CS_BURST 0x00000000
307	#define CFG_CS_DEADCYCLE 0x33333333
308
309	#define CFG_RESET_ADDRESS 0xff000000
310
311	/*-----------------------------------------------------------------------
312	* USB stuff
313	*-----------------------------------------------------------------------
314	*/
315	#define CONFIG_USB_CLOCK 0x0001BBBB
316	#define CONFIG_USB_CONFIG 0x00001000
317
318	/*-----------------------------------------------------------------------
319	* IDE/ATA stuff Supports IDE harddisk
320	*-----------------------------------------------------------------------
321	*/
322
323	#undef CONFIG_IDE_8xx_PCCARD /* Use IDE with PC Card Adapter */
324
325	#undef CONFIG_IDE_8xx_DIRECT /* Direct IDE not supported */
326	#undef CONFIG_IDE_LED /* LED for ide not supported */
327
328	#define CONFIG_IDE_RESET /* reset for ide supported */
329	#define CONFIG_IDE_PREINIT
330
331	#define CFG_IDE_MAXBUS 1 /* max. 1 IDE bus */
332	#define CFG_IDE_MAXDEVICE 1 /* max. 1 drive per IDE bus */
333
334	#define CFG_ATA_IDE0_OFFSET 0x0000
335
336	#define CFG_ATA_BASE_ADDR MPC5XXX_ATA
337
338	/* Offset for data I/O */
339	#define CFG_ATA_DATA_OFFSET (0x0060)
340
341	/* Offset for normal register accesses */
342	#define CFG_ATA_REG_OFFSET (CFG_ATA_DATA_OFFSET)
343
344	/* Offset for alternate registers */
345	#define CFG_ATA_ALT_OFFSET (0x005C)
346
347	/* Interval between registers */
348	#define CFG_ATA_STRIDE 4
349
350	/*-----------------------------------------------------------------------
351	* CPLD stuff
352	*/
353	#define CFG_FPGA_XC95XL 1 /* using Xilinx XC95XL CPLD */
354	#define CFG_FPGA_MAX_SIZE 321024 / 32kByte is enough for CPLD */
355
356	/* CPLD program pin configuration */
357	#define CFG_FPGA_PRG 0x20000000 /* JTAG TMS pin (ppc output) */
358	#define CFG_FPGA_CLK 0x10000000 /* JTAG TCK pin (ppc output) */
359	#define CFG_FPGA_DATA 0x20000000 /* JTAG TDO->TDI data pin (ppc output) */
360	#define CFG_FPGA_DONE 0x10000000 /* JTAG TDI->TDO pin (ppc input) */
361
362	#define JTAG_GPIO_ADDR_TMS (CFG_MBAR + 0xB10) /* JTAG TMS pin (GPS data out value reg.) */
363	#define JTAG_GPIO_ADDR_TCK (CFG_MBAR + 0xC0C) /* JTAG TCK pin (GPW data out value reg.) */
364	#define JTAG_GPIO_ADDR_TDI (CFG_MBAR + 0xC0C) /* JTAG TDO->TDI pin (GPW data out value reg.) */
365	#define JTAG_GPIO_ADDR_TDO (CFG_MBAR + 0xB14) /* JTAG TDI->TDO pin (GPS data in value reg.) */
366
367	#define JTAG_GPIO_ADDR_CFG (CFG_MBAR + 0xB00)
368	#define JTAG_GPIO_CFG_SET 0x00000000
369	#define JTAG_GPIO_CFG_RESET 0x00F00000
370
371	#define JTAG_GPIO_ADDR_EN_TMS (CFG_MBAR + 0xB04)
372	#define JTAG_GPIO_TMS_EN_SET 0x20000000 /* Enable for GPIO */
373	#define JTAG_GPIO_TMS_EN_RESET 0x00000000
374	#define JTAG_GPIO_ADDR_DDR_TMS (CFG_MBAR + 0xB0C)
375	#define JTAG_GPIO_TMS_DDR_SET 0x20000000 /* Set as output */
376	#define JTAG_GPIO_TMS_DDR_RESET 0x00000000
377
378	#define JTAG_GPIO_ADDR_EN_TCK (CFG_MBAR + 0xC00)
379	#define JTAG_GPIO_TCK_EN_SET 0x20000000 /* Enable for GPIO */
380	#define JTAG_GPIO_TCK_EN_RESET 0x00000000
381	#define JTAG_GPIO_ADDR_DDR_TCK (CFG_MBAR + 0xC08)
382	#define JTAG_GPIO_TCK_DDR_SET 0x20000000 /* Set as output */
383	#define JTAG_GPIO_TCK_DDR_RESET 0x00000000
384
385	#define JTAG_GPIO_ADDR_EN_TDI (CFG_MBAR + 0xC00)
386	#define JTAG_GPIO_TDI_EN_SET 0x10000000 /* Enable as GPIO */
387	#define JTAG_GPIO_TDI_EN_RESET 0x00000000
388	#define JTAG_GPIO_ADDR_DDR_TDI (CFG_MBAR + 0xC08)
389	#define JTAG_GPIO_TDI_DDR_SET 0x10000000 /* Set as output */
390	#define JTAG_GPIO_TDI_DDR_RESET 0x00000000
391
392	#define JTAG_GPIO_ADDR_EN_TDO (CFG_MBAR + 0xB04)
393	#define JTAG_GPIO_TDO_EN_SET 0x10000000 /* Enable as GPIO */
394	#define JTAG_GPIO_TDO_EN_RESET 0x00000000
395	#define JTAG_GPIO_ADDR_DDR_TDO (CFG_MBAR + 0xB0C)
396	#define JTAG_GPIO_TDO_DDR_SET 0x00000000
397	#define JTAG_GPIO_TDO_DDR_RESET 0x10000000 /* Set as input */
398
399	#endif /* __CONFIG_H */